2 * i2c driver for Freescale i.MX series
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/errno.h>
21 #include <asm/imx-common/mxc_i2c.h>
26 #include <dm/pinctrl.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define I2C_QUIRK_FLAG (1 << 0)
33 #define IMX_I2C_REGSHIFT 2
34 #define VF610_I2C_REGSHIFT 0
42 #define I2CR_IIEN (1 << 6)
43 #define I2CR_MSTA (1 << 5)
44 #define I2CR_MTX (1 << 4)
45 #define I2CR_TX_NO_AK (1 << 3)
46 #define I2CR_RSTA (1 << 2)
48 #define I2SR_ICF (1 << 7)
49 #define I2SR_IBB (1 << 5)
50 #define I2SR_IAL (1 << 4)
51 #define I2SR_IIF (1 << 1)
52 #define I2SR_RX_NO_AK (1 << 0)
55 #define I2CR_IEN (0 << 7)
56 #define I2CR_IDIS (1 << 7)
57 #define I2SR_IIF_CLEAR (1 << 1)
59 #define I2CR_IEN (1 << 7)
60 #define I2CR_IDIS (0 << 7)
61 #define I2SR_IIF_CLEAR (0 << 1)
64 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
65 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
69 static u16 i2c_clk_div[60][2] = {
70 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
71 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
72 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
73 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
74 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
75 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
76 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
77 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
78 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
79 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
80 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
81 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
82 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
83 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
84 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
87 static u16 i2c_clk_div[50][2] = {
88 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
89 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
90 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
91 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
92 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
93 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
94 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
95 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
96 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
97 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
98 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
99 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
100 { 3072, 0x1E }, { 3840, 0x1F }
104 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
105 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
107 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
108 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
110 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
111 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
113 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
114 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
117 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
118 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
120 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
121 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
123 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
124 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
126 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
127 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
131 * Calculate and set proper clock divider
133 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
135 unsigned int i2c_clk_rate;
139 #if defined(CONFIG_MX31)
140 struct clock_control_regs *sc_regs =
141 (struct clock_control_regs *)CCM_BASE;
143 /* start the required I2C clock */
144 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
148 /* Divider value calculation */
149 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
150 div = (i2c_clk_rate + rate - 1) / rate;
151 if (div < i2c_clk_div[0][0])
153 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
154 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
156 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
159 /* Store divider value */
166 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
168 ulong base = i2c_bus->base;
169 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
170 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
171 u8 idx = i2c_clk_div[clk_idx][1];
172 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
177 /* Store divider value */
178 writeb(idx, base + (IFDR << reg_shift));
181 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
182 writeb(0, base + (I2SR << reg_shift));
186 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
187 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
188 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
190 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
194 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
195 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
196 ulong base = i2c_bus->base;
197 ulong start_time = get_timer(0);
199 sr = readb(base + (I2SR << reg_shift));
202 writeb(sr | I2SR_IAL, base +
203 (I2SR << reg_shift));
205 writeb(sr & ~I2SR_IAL, base +
206 (I2SR << reg_shift));
207 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
208 __func__, sr, readb(base + (I2CR << reg_shift)),
212 if ((sr & (state >> 8)) == (unsigned char)state)
215 elapsed = get_timer(start_time);
216 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
219 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
220 sr, readb(base + (I2CR << reg_shift)), state);
224 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
227 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
228 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
229 ulong base = i2c_bus->base;
231 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
232 writeb(byte, base + (I2DR << reg_shift));
234 ret = wait_for_sr_state(i2c_bus, ST_IIF);
237 if (ret & I2SR_RX_NO_AK)
243 * Stub implementations for outer i2c slave operations.
245 void __i2c_force_reset_slave(void)
248 void i2c_force_reset_slave(void)
249 __attribute__((weak, alias("__i2c_force_reset_slave")));
252 * Stop I2C transaction
254 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
257 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
258 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
259 ulong base = i2c_bus->base;
260 unsigned int temp = readb(base + (I2CR << reg_shift));
262 temp &= ~(I2CR_MSTA | I2CR_MTX);
263 writeb(temp, base + (I2CR << reg_shift));
264 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
266 printf("%s:trigger stop failed\n", __func__);
270 * Send start signal, chip address and
271 * write register address
273 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
278 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
279 ulong base = i2c_bus->base;
280 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
282 /* Reset i2c slave */
283 i2c_force_reset_slave();
285 /* Enable I2C controller */
287 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
289 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
292 writeb(I2CR_IEN, base + (I2CR << reg_shift));
293 /* Wait for controller to be stable */
297 if (readb(base + (IADR << reg_shift)) == (chip << 1))
298 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
299 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
300 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
304 /* Start I2C transaction */
305 temp = readb(base + (I2CR << reg_shift));
307 writeb(temp, base + (I2CR << reg_shift));
309 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
313 temp |= I2CR_MTX | I2CR_TX_NO_AK;
314 writeb(temp, base + (I2CR << reg_shift));
316 /* write slave address */
317 ret = tx_byte(i2c_bus, chip << 1);
322 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
329 #ifndef CONFIG_DM_I2C
330 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
332 if (i2c_bus && i2c_bus->idle_bus_fn)
333 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
338 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
340 * scl-gpios: specify the gpio related to SCL pin
341 * sda-gpios: specify the gpio related to SDA pin
342 * add pinctrl to configure i2c pins to gpio function for i2c
343 * bus recovery, call it "gpio" state
346 * The i2c_idle_bus is an implementation following Linux Kernel.
348 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
350 struct udevice *bus = i2c_bus->bus;
351 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
352 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
355 ulong elapsed, start_time;
357 if (pinctrl_select_state(bus, "gpio")) {
358 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
360 * GPIO pinctrl for i2c force idle is not a must,
361 * but it is strongly recommended to be used.
362 * Because it can help you to recover from bad
363 * i2c bus state. Do not return failure, because
369 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
370 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
371 scl = dm_gpio_get_value(scl_gpio);
372 sda = dm_gpio_get_value(sda_gpio);
374 if ((sda & scl) == 1)
375 goto exit; /* Bus is idle already */
377 /* Send high and low on the SCL line */
378 for (i = 0; i < 9; i++) {
379 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
380 dm_gpio_set_value(scl_gpio, 0);
382 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
385 start_time = get_timer(0);
387 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
388 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
389 scl = dm_gpio_get_value(scl_gpio);
390 sda = dm_gpio_get_value(sda_gpio);
391 if ((sda & scl) == 1)
394 elapsed = get_timer(start_time);
395 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
397 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
403 pinctrl_select_state(bus, "default");
408 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
413 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
414 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
419 for (retry = 0; retry < 3; retry++) {
420 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
423 i2c_imx_stop(i2c_bus);
427 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
429 if (ret != -ERESTART)
430 /* Disable controller */
431 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
433 if (i2c_idle_bus(i2c_bus) < 0)
436 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
441 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
446 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
447 debug("write_data: ");
448 /* use rc for counter */
449 for (i = 0; i < len; ++i)
450 debug(" 0x%02x", buf[i]);
453 for (i = 0; i < len; i++) {
454 ret = tx_byte(i2c_bus, buf[i]);
456 debug("i2c_write_data(): rc=%d\n", ret);
464 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
470 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
471 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
472 ulong base = i2c_bus->base;
474 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
476 /* setup bus to read data */
477 temp = readb(base + (I2CR << reg_shift));
478 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
480 temp |= I2CR_TX_NO_AK;
481 writeb(temp, base + (I2CR << reg_shift));
482 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
483 /* dummy read to clear ICF */
484 readb(base + (I2DR << reg_shift));
487 for (i = 0; i < len; i++) {
488 ret = wait_for_sr_state(i2c_bus, ST_IIF);
490 debug("i2c_read_data(): ret=%d\n", ret);
491 i2c_imx_stop(i2c_bus);
496 * It must generate STOP before read I2DR to prevent
497 * controller from generating another clock cycle
499 if (i == (len - 1)) {
500 i2c_imx_stop(i2c_bus);
501 } else if (i == (len - 2)) {
502 temp = readb(base + (I2CR << reg_shift));
503 temp |= I2CR_TX_NO_AK;
504 writeb(temp, base + (I2CR << reg_shift));
506 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
507 buf[i] = readb(base + (I2DR << reg_shift));
510 /* reuse ret for counter*/
511 for (ret = 0; ret < len; ++ret)
512 debug(" 0x%02x", buf[ret]);
515 i2c_imx_stop(i2c_bus);
519 #ifndef CONFIG_DM_I2C
521 * Read data from I2C device
523 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
524 int alen, u8 *buf, int len)
528 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
529 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
530 ulong base = i2c_bus->base;
532 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
536 temp = readb(base + (I2CR << reg_shift));
538 writeb(temp, base + (I2CR << reg_shift));
540 ret = tx_byte(i2c_bus, (chip << 1) | 1);
542 i2c_imx_stop(i2c_bus);
546 ret = i2c_read_data(i2c_bus, chip, buf, len);
548 i2c_imx_stop(i2c_bus);
553 * Write data to I2C device
555 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
556 int alen, const u8 *buf, int len)
560 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
564 ret = i2c_write_data(i2c_bus, chip, buf, len);
566 i2c_imx_stop(i2c_bus);
571 #if !defined(I2C2_BASE_ADDR)
572 #define I2C2_BASE_ADDR 0
575 #if !defined(I2C3_BASE_ADDR)
576 #define I2C3_BASE_ADDR 0
579 #if !defined(I2C4_BASE_ADDR)
580 #define I2C4_BASE_ADDR 0
583 static struct mxc_i2c_bus mxc_i2c_buses[] = {
584 #if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \
585 defined(CONFIG_FSL_LAYERSCAPE)
586 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
587 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
588 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
589 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
591 { 0, I2C1_BASE_ADDR, 0 },
592 { 1, I2C2_BASE_ADDR, 0 },
593 { 2, I2C3_BASE_ADDR, 0 },
594 { 3, I2C4_BASE_ADDR, 0 },
598 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
600 return &mxc_i2c_buses[adap->hwadapnr];
603 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
604 uint addr, int alen, uint8_t *buffer,
607 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
610 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
611 uint addr, int alen, uint8_t *buffer,
614 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
618 * Test if a chip at a given address responds (probe the chip)
620 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
622 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
625 int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
629 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
630 __attribute__((weak, alias("__enable_i2c_clk")));
632 void bus_i2c_init(int index, int speed, int unused,
633 int (*idle_bus_fn)(void *p), void *idle_bus_data)
637 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
638 debug("Error i2c index\n");
643 * Warning: Be careful to allow the assignment to a static
644 * variable here. This function could be called while U-Boot is
645 * still running in flash memory. So such assignment is equal
646 * to write data to flash without erasing.
649 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
651 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
653 ret = enable_i2c_clk(1, index);
655 debug("I2C-%d clk fail to enable.\n", index);
659 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
665 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
667 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
673 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
675 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
679 * Register mxc i2c adapters
681 #ifdef CONFIG_SYS_I2C_MXC_I2C1
682 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
683 mxc_i2c_read, mxc_i2c_write,
684 mxc_i2c_set_bus_speed,
685 CONFIG_SYS_MXC_I2C1_SPEED,
686 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
689 #ifdef CONFIG_SYS_I2C_MXC_I2C2
690 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
691 mxc_i2c_read, mxc_i2c_write,
692 mxc_i2c_set_bus_speed,
693 CONFIG_SYS_MXC_I2C2_SPEED,
694 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
697 #ifdef CONFIG_SYS_I2C_MXC_I2C3
698 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
699 mxc_i2c_read, mxc_i2c_write,
700 mxc_i2c_set_bus_speed,
701 CONFIG_SYS_MXC_I2C3_SPEED,
702 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
705 #ifdef CONFIG_SYS_I2C_MXC_I2C4
706 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
707 mxc_i2c_read, mxc_i2c_write,
708 mxc_i2c_set_bus_speed,
709 CONFIG_SYS_MXC_I2C4_SPEED,
710 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
715 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
717 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
719 return bus_i2c_set_bus_speed(i2c_bus, speed);
722 static int mxc_i2c_probe(struct udevice *bus)
724 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
725 const void *fdt = gd->fdt_blob;
726 int node = bus->of_offset;
730 i2c_bus->driver_data = dev_get_driver_data(bus);
732 addr = dev_get_addr(bus);
733 if (addr == FDT_ADDR_T_NONE)
736 i2c_bus->base = addr;
737 i2c_bus->index = bus->seq;
741 ret = enable_i2c_clk(1, bus->seq);
746 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
747 * Use gpio to force bus idle when necessary.
749 ret = fdt_find_string(fdt, node, "pinctrl-names", "gpio");
751 dev_info(dev, "i2c bus %d at %lu, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
753 ret = gpio_request_by_name_nodev(fdt, node, "scl-gpios",
754 0, &i2c_bus->scl_gpio,
756 ret2 = gpio_request_by_name_nodev(fdt, node, "sda-gpios",
757 0, &i2c_bus->sda_gpio,
759 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) |
760 !dm_gpio_is_valid(&i2c_bus->scl_gpio) |
762 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
767 ret = i2c_idle_bus(i2c_bus);
770 enable_i2c_clk(0, bus->seq);
775 * Pinmux settings are in board file now, until pinmux is supported,
776 * we can set pinmux here in probe function.
779 debug("i2c : controller bus %d at %lu , speed %d: ",
780 bus->seq, i2c_bus->base,
786 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
790 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
792 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
794 debug("%s failed, ret = %d\n", __func__, ret);
798 i2c_imx_stop(i2c_bus);
803 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
805 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
807 ulong base = i2c_bus->base;
808 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
809 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
812 * Here the 3rd parameter addr and the 4th one alen are set to 0,
813 * because here we only want to send out chip address. The register
814 * address is wrapped in msg.
816 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
818 debug("i2c_init_transfer error: %d\n", ret);
822 for (; nmsgs > 0; nmsgs--, msg++) {
823 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
824 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
825 if (msg->flags & I2C_M_RD)
826 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
829 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
835 ret = readb(base + (I2CR << reg_shift));
837 writeb(ret, base + (I2CR << reg_shift));
839 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
841 i2c_imx_stop(i2c_bus);
849 debug("i2c_write: error sending\n");
851 i2c_imx_stop(i2c_bus);
856 static const struct dm_i2c_ops mxc_i2c_ops = {
857 .xfer = mxc_i2c_xfer,
858 .probe_chip = mxc_i2c_probe_chip,
859 .set_bus_speed = mxc_i2c_set_bus_speed,
862 static const struct udevice_id mxc_i2c_ids[] = {
863 { .compatible = "fsl,imx21-i2c", },
864 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
868 U_BOOT_DRIVER(i2c_mxc) = {
871 .of_match = mxc_i2c_ids,
872 .probe = mxc_i2c_probe,
873 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),