drivers/i2c/mxc_i2c.c

   1 /*
   2  * i2c driver for Freescale i.MX series
   3  *
   4  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   5  * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Based on i2c-imx.c from linux kernel:
   8  *  Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
   9  *  Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  10  *  Copyright (C) 2007 RightHand Technologies, Inc.
  11  *  Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  12  *
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #include <common.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/imx-regs.h>
  20 #include <linux/errno.h>
  21 #include <asm/mach-imx/mxc_i2c.h>
  22 #include <asm/io.h>
  23 #include <i2c.h>
  24 #include <watchdog.h>
  25 #include <dm.h>
  26 #include <dm/pinctrl.h>
  27 #include <fdtdec.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define I2C_QUIRK_FLAG          (1 << 0)
  32
  33 #define IMX_I2C_REGSHIFT        2
  34 #define VF610_I2C_REGSHIFT      0
  35
  36 #define I2C_EARLY_INIT_INDEX            0
  37 #ifdef CONFIG_SYS_I2C_IFDR_DIV
  38 #define I2C_IFDR_DIV_CONSERVATIVE       CONFIG_SYS_I2C_IFDR_DIV
  39 #else
  40 #define I2C_IFDR_DIV_CONSERVATIVE       0x7e
  41 #endif
  42
  43 /* Register index */
  44 #define IADR    0
  45 #define IFDR    1
  46 #define I2CR    2
  47 #define I2SR    3
  48 #define I2DR    4
  49
  50 #define I2CR_IIEN       (1 << 6)
  51 #define I2CR_MSTA       (1 << 5)
  52 #define I2CR_MTX        (1 << 4)
  53 #define I2CR_TX_NO_AK   (1 << 3)
  54 #define I2CR_RSTA       (1 << 2)
  55
  56 #define I2SR_ICF        (1 << 7)
  57 #define I2SR_IBB        (1 << 5)
  58 #define I2SR_IAL        (1 << 4)
  59 #define I2SR_IIF        (1 << 1)
  60 #define I2SR_RX_NO_AK   (1 << 0)
  61
  62 #ifdef I2C_QUIRK_REG
  63 #define I2CR_IEN        (0 << 7)
  64 #define I2CR_IDIS       (1 << 7)
  65 #define I2SR_IIF_CLEAR  (1 << 1)
  66 #else
  67 #define I2CR_IEN        (1 << 7)
  68 #define I2CR_IDIS       (0 << 7)
  69 #define I2SR_IIF_CLEAR  (0 << 1)
  70 #endif
  71
  72 #ifdef I2C_QUIRK_REG
  73 static u16 i2c_clk_div[60][2] = {
  74         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
  75         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
  76         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
  77         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
  78         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
  79         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
  80         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
  81         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
  82         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
  83         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
  84         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
  85         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
  86         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
  87         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
  88         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
  89 };
  90 #else
  91 static u16 i2c_clk_div[50][2] = {
  92         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
  93         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
  94         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
  95         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
  96         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
  97         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
  98         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
  99         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
 100         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 101         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 102         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 103         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 104         { 3072, 0x1E }, { 3840, 0x1F }
 105 };
 106 #endif
 107
 108 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
 109 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
 110 #endif
 111 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
 112 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
 113 #endif
 114 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
 115 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
 116 #endif
 117 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
 118 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
 119 #endif
 120
 121 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
 122 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
 123 #endif
 124 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
 125 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
 126 #endif
 127 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
 128 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
 129 #endif
 130 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
 131 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
 132 #endif
 133
 134 /*
 135  * Calculate and set proper clock divider
 136  */
 137 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
 138 {
 139         unsigned int i2c_clk_rate;
 140         unsigned int div;
 141         u8 clk_div;
 142
 143 #if defined(CONFIG_MX31)
 144         struct clock_control_regs *sc_regs =
 145                 (struct clock_control_regs *)CCM_BASE;
 146
 147         /* start the required I2C clock */
 148         writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
 149                 &sc_regs->cgr0);
 150 #endif
 151
 152         /* Divider value calculation */
 153         i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
 154         div = (i2c_clk_rate + rate - 1) / rate;
 155         if (div < i2c_clk_div[0][0])
 156                 clk_div = 0;
 157         else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
 158                 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
 159         else
 160                 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
 161                         ;
 162
 163         /* Store divider value */
 164         return clk_div;
 165 }
 166
 167 /*
 168  * Set I2C Bus speed
 169  */
 170 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
 171 {
 172         ulong base = i2c_bus->base;
 173         bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
 174         u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
 175         u8 idx = i2c_clk_div[clk_idx][1];
 176         int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 177
 178         if (!base)
 179                 return -EINVAL;
 180
 181         /* Store divider value */
 182         writeb(idx, base + (IFDR << reg_shift));
 183
 184         /* Reset module */
 185         writeb(I2CR_IDIS, base + (I2CR << reg_shift));
 186         writeb(0, base + (I2SR << reg_shift));
 187         return 0;
 188 }
 189
 190 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
 191 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
 192 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
 193
 194 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
 195 {
 196         unsigned sr;
 197         ulong elapsed;
 198         bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
 199         int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 200         ulong base = i2c_bus->base;
 201         ulong start_time = get_timer(0);
 202         for (;;) {
 203                 sr = readb(base + (I2SR << reg_shift));
 204                 if (sr & I2SR_IAL) {
 205                         if (quirk)
 206                                 writeb(sr | I2SR_IAL, base +
 207                                        (I2SR << reg_shift));
 208                         else
 209                                 writeb(sr & ~I2SR_IAL, base +
 210                                        (I2SR << reg_shift));
 211                         printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
 212                                 __func__, sr, readb(base + (I2CR << reg_shift)),
 213                                 state);
 214                         return -ERESTART;
 215                 }
 216                 if ((sr & (state >> 8)) == (unsigned char)state)
 217                         return sr;
 218                 WATCHDOG_RESET();
 219                 elapsed = get_timer(start_time);
 220                 if (elapsed > (CONFIG_SYS_HZ / 10))     /* .1 seconds */
 221                         break;
 222         }
 223         printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
 224                sr, readb(base + (I2CR << reg_shift)), state);
 225         return -ETIMEDOUT;
 226 }
 227
 228 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
 229 {
 230         int ret;
 231         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 232                         VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 233         ulong base = i2c_bus->base;
 234
 235         writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 236         writeb(byte, base + (I2DR << reg_shift));
 237
 238         ret = wait_for_sr_state(i2c_bus, ST_IIF);
 239         if (ret < 0)
 240                 return ret;
 241         if (ret & I2SR_RX_NO_AK)
 242                 return -EREMOTEIO;
 243         return 0;
 244 }
 245
 246 /*
 247  * Stub implementations for outer i2c slave operations.
 248  */
 249 void __i2c_force_reset_slave(void)
 250 {
 251 }
 252 void i2c_force_reset_slave(void)
 253         __attribute__((weak, alias("__i2c_force_reset_slave")));
 254
 255 /*
 256  * Stop I2C transaction
 257  */
 258 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
 259 {
 260         int ret;
 261         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 262                         VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 263         ulong base = i2c_bus->base;
 264         unsigned int temp = readb(base + (I2CR << reg_shift));
 265
 266         temp &= ~(I2CR_MSTA | I2CR_MTX);
 267         writeb(temp, base + (I2CR << reg_shift));
 268         ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
 269         if (ret < 0)
 270                 printf("%s:trigger stop failed\n", __func__);
 271 }
 272
 273 /*
 274  * Send start signal, chip address and
 275  * write register address
 276  */
 277 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
 278                               u32 addr, int alen)
 279 {
 280         unsigned int temp;
 281         int ret;
 282         bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
 283         ulong base = i2c_bus->base;
 284         int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 285
 286         /* Reset i2c slave */
 287         i2c_force_reset_slave();
 288
 289         /* Enable I2C controller */
 290         if (quirk)
 291                 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
 292         else
 293                 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
 294
 295         if (ret) {
 296                 writeb(I2CR_IEN, base + (I2CR << reg_shift));
 297                 /* Wait for controller to be stable */
 298                 udelay(50);
 299         }
 300
 301         if (readb(base + (IADR << reg_shift)) == (chip << 1))
 302                 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
 303         writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 304         ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
 305         if (ret < 0)
 306                 return ret;
 307
 308         /* Start I2C transaction */
 309         temp = readb(base + (I2CR << reg_shift));
 310         temp |= I2CR_MSTA;
 311         writeb(temp, base + (I2CR << reg_shift));
 312
 313         ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
 314         if (ret < 0)
 315                 return ret;
 316
 317         temp |= I2CR_MTX | I2CR_TX_NO_AK;
 318         writeb(temp, base + (I2CR << reg_shift));
 319
 320         if (alen >= 0)  {
 321                 /* write slave address */
 322                 ret = tx_byte(i2c_bus, chip << 1);
 323                 if (ret < 0)
 324                         return ret;
 325
 326                 while (alen--) {
 327                         ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
 328                         if (ret < 0)
 329                                 return ret;
 330                 }
 331         }
 332
 333         return 0;
 334 }
 335
 336 #ifndef CONFIG_DM_I2C
 337 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
 338 {
 339         if (i2c_bus && i2c_bus->idle_bus_fn)
 340                 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
 341         return 0;
 342 }
 343 #else
 344 /*
 345  * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
 346  * "
 347  *  scl-gpios: specify the gpio related to SCL pin
 348  *  sda-gpios: specify the gpio related to SDA pin
 349  *  add pinctrl to configure i2c pins to gpio function for i2c
 350  *  bus recovery, call it "gpio" state
 351  * "
 352  *
 353  * The i2c_idle_bus is an implementation following Linux Kernel.
 354  */
 355 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
 356 {
 357         struct udevice *bus = i2c_bus->bus;
 358         struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
 359         struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
 360         int sda, scl;
 361         int i, ret = 0;
 362         ulong elapsed, start_time;
 363
 364         if (pinctrl_select_state(bus, "gpio")) {
 365                 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
 366                 /*
 367                  * GPIO pinctrl for i2c force idle is not a must,
 368                  * but it is strongly recommended to be used.
 369                  * Because it can help you to recover from bad
 370                  * i2c bus state. Do not return failure, because
 371                  * it is not a must.
 372                  */
 373                 return 0;
 374         }
 375
 376         dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
 377         dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
 378         scl = dm_gpio_get_value(scl_gpio);
 379         sda = dm_gpio_get_value(sda_gpio);
 380
 381         if ((sda & scl) == 1)
 382                 goto exit;              /* Bus is idle already */
 383
 384         /* Send high and low on the SCL line */
 385         for (i = 0; i < 9; i++) {
 386                 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
 387                 dm_gpio_set_value(scl_gpio, 0);
 388                 udelay(50);
 389                 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
 390                 udelay(50);
 391         }
 392         start_time = get_timer(0);
 393         for (;;) {
 394                 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
 395                 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
 396                 scl = dm_gpio_get_value(scl_gpio);
 397                 sda = dm_gpio_get_value(sda_gpio);
 398                 if ((sda & scl) == 1)
 399                         break;
 400                 WATCHDOG_RESET();
 401                 elapsed = get_timer(start_time);
 402                 if (elapsed > (CONFIG_SYS_HZ / 5)) {    /* .2 seconds */
 403                         ret = -EBUSY;
 404                         printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
 405                         break;
 406                 }
 407         }
 408
 409 exit:
 410         pinctrl_select_state(bus, "default");
 411         return ret;
 412 }
 413 #endif
 414
 415 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
 416                              u32 addr, int alen)
 417 {
 418         int retry;
 419         int ret;
 420         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 421                         VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 422
 423         if (!i2c_bus->base)
 424                 return -EINVAL;
 425
 426         for (retry = 0; retry < 3; retry++) {
 427                 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
 428                 if (ret >= 0)
 429                         return 0;
 430                 i2c_imx_stop(i2c_bus);
 431                 if (ret == -EREMOTEIO)
 432                         return ret;
 433
 434                 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
 435                                 retry);
 436                 if (ret != -ERESTART)
 437                         /* Disable controller */
 438                         writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
 439                 udelay(100);
 440                 if (i2c_idle_bus(i2c_bus) < 0)
 441                         break;
 442         }
 443         printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
 444         return ret;
 445 }
 446
 447
 448 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
 449                           int len)
 450 {
 451         int i, ret = 0;
 452
 453         debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
 454         debug("write_data: ");
 455         /* use rc for counter */
 456         for (i = 0; i < len; ++i)
 457                 debug(" 0x%02x", buf[i]);
 458         debug("\n");
 459
 460         for (i = 0; i < len; i++) {
 461                 ret = tx_byte(i2c_bus, buf[i]);
 462                 if (ret < 0) {
 463                         debug("i2c_write_data(): rc=%d\n", ret);
 464                         break;
 465                 }
 466         }
 467
 468         return ret;
 469 }
 470
 471 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
 472                          int len)
 473 {
 474         int ret;
 475         unsigned int temp;
 476         int i;
 477         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 478                         VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 479         ulong base = i2c_bus->base;
 480
 481         debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
 482
 483         /* setup bus to read data */
 484         temp = readb(base + (I2CR << reg_shift));
 485         temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
 486         if (len == 1)
 487                 temp |= I2CR_TX_NO_AK;
 488         writeb(temp, base + (I2CR << reg_shift));
 489         writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 490         /* dummy read to clear ICF */
 491         readb(base + (I2DR << reg_shift));
 492
 493         /* read data */
 494         for (i = 0; i < len; i++) {
 495                 ret = wait_for_sr_state(i2c_bus, ST_IIF);
 496                 if (ret < 0) {
 497                         debug("i2c_read_data(): ret=%d\n", ret);
 498                         i2c_imx_stop(i2c_bus);
 499                         return ret;
 500                 }
 501
 502                 /*
 503                  * It must generate STOP before read I2DR to prevent
 504                  * controller from generating another clock cycle
 505                  */
 506                 if (i == (len - 1)) {
 507                         i2c_imx_stop(i2c_bus);
 508                 } else if (i == (len - 2)) {
 509                         temp = readb(base + (I2CR << reg_shift));
 510                         temp |= I2CR_TX_NO_AK;
 511                         writeb(temp, base + (I2CR << reg_shift));
 512                 }
 513                 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 514                 buf[i] = readb(base + (I2DR << reg_shift));
 515         }
 516
 517         /* reuse ret for counter*/
 518         for (ret = 0; ret < len; ++ret)
 519                 debug(" 0x%02x", buf[ret]);
 520         debug("\n");
 521
 522         i2c_imx_stop(i2c_bus);
 523         return 0;
 524 }
 525
 526 #ifndef CONFIG_DM_I2C
 527 /*
 528  * Read data from I2C device
 529  */
 530 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
 531                         int alen, u8 *buf, int len)
 532 {
 533         int ret = 0;
 534         u32 temp;
 535         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 536                 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 537         ulong base = i2c_bus->base;
 538
 539         ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
 540         if (ret < 0)
 541                 return ret;
 542
 543         if (alen >= 0) {
 544                 temp = readb(base + (I2CR << reg_shift));
 545                 temp |= I2CR_RSTA;
 546                 writeb(temp, base + (I2CR << reg_shift));
 547         }
 548
 549         ret = tx_byte(i2c_bus, (chip << 1) | 1);
 550         if (ret < 0) {
 551                 i2c_imx_stop(i2c_bus);
 552                 return ret;
 553         }
 554
 555         ret = i2c_read_data(i2c_bus, chip, buf, len);
 556
 557         i2c_imx_stop(i2c_bus);
 558         return ret;
 559 }
 560
 561 /*
 562  * Write data to I2C device
 563  */
 564 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
 565                          int alen, const u8 *buf, int len)
 566 {
 567         int ret = 0;
 568
 569         ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
 570         if (ret < 0)
 571                 return ret;
 572
 573         ret = i2c_write_data(i2c_bus, chip, buf, len);
 574
 575         i2c_imx_stop(i2c_bus);
 576
 577         return ret;
 578 }
 579
 580 #if !defined(I2C2_BASE_ADDR)
 581 #define I2C2_BASE_ADDR  0
 582 #endif
 583
 584 #if !defined(I2C3_BASE_ADDR)
 585 #define I2C3_BASE_ADDR  0
 586 #endif
 587
 588 #if !defined(I2C4_BASE_ADDR)
 589 #define I2C4_BASE_ADDR  0
 590 #endif
 591
 592 #if !defined(I2C5_BASE_ADDR)
 593 #define I2C5_BASE_ADDR 0
 594 #endif
 595
 596 #if !defined(I2C6_BASE_ADDR)
 597 #define I2C6_BASE_ADDR 0
 598 #endif
 599
 600 #if !defined(I2C7_BASE_ADDR)
 601 #define I2C7_BASE_ADDR 0
 602 #endif
 603
 604 #if !defined(I2C8_BASE_ADDR)
 605 #define I2C8_BASE_ADDR 0
 606 #endif
 607
 608 static struct mxc_i2c_bus mxc_i2c_buses[] = {
 609 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
 610         defined(CONFIG_FSL_LAYERSCAPE)
 611         { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
 612         { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
 613         { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
 614         { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
 615         { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
 616         { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
 617         { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
 618         { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
 619 #else
 620         { 0, I2C1_BASE_ADDR, 0 },
 621         { 1, I2C2_BASE_ADDR, 0 },
 622         { 2, I2C3_BASE_ADDR, 0 },
 623         { 3, I2C4_BASE_ADDR, 0 },
 624         { 4, I2C5_BASE_ADDR, 0 },
 625         { 5, I2C6_BASE_ADDR, 0 },
 626         { 6, I2C7_BASE_ADDR, 0 },
 627         { 7, I2C8_BASE_ADDR, 0 },
 628 #endif
 629 };
 630
 631 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
 632 {
 633         return &mxc_i2c_buses[adap->hwadapnr];
 634 }
 635
 636 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
 637                                 uint addr, int alen, uint8_t *buffer,
 638                                 int len)
 639 {
 640         return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
 641 }
 642
 643 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
 644                                 uint addr, int alen, uint8_t *buffer,
 645                                 int len)
 646 {
 647         return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
 648 }
 649
 650 /*
 651  * Test if a chip at a given address responds (probe the chip)
 652  */
 653 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 654 {
 655         return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
 656 }
 657
 658 int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 659 {
 660         return 1;
 661 }
 662 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 663         __attribute__((weak, alias("__enable_i2c_clk")));
 664
 665 void bus_i2c_init(int index, int speed, int unused,
 666                   int (*idle_bus_fn)(void *p), void *idle_bus_data)
 667 {
 668         int ret;
 669
 670         if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
 671                 debug("Error i2c index\n");
 672                 return;
 673         }
 674
 675         /*
 676          * Warning: Be careful to allow the assignment to a static
 677          * variable here. This function could be called while U-Boot is
 678          * still running in flash memory. So such assignment is equal
 679          * to write data to flash without erasing.
 680          */
 681         if (idle_bus_fn)
 682                 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
 683         if (idle_bus_data)
 684                 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
 685
 686         ret = enable_i2c_clk(1, index);
 687         if (ret < 0) {
 688                 debug("I2C-%d clk fail to enable.\n", index);
 689                 return;
 690         }
 691
 692         bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
 693 }
 694
 695 /*
 696  * Early init I2C for prepare read the clk through I2C.
 697  */
 698 void i2c_early_init_f(void)
 699 {
 700         ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
 701         bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
 702                                         & I2C_QUIRK_FLAG ? true : false;
 703         int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 704
 705         /* Set I2C divider value */
 706         writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
 707         /* Reset module */
 708         writeb(I2CR_IDIS, base + (I2CR << reg_shift));
 709         writeb(0, base + (I2SR << reg_shift));
 710         /* Enable I2C */
 711         writeb(I2CR_IEN, base + (I2CR << reg_shift));
 712 }
 713
 714 /*
 715  * Init I2C Bus
 716  */
 717 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 718 {
 719         bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
 720 }
 721
 722 /*
 723  * Set I2C Speed
 724  */
 725 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 726 {
 727         return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
 728 }
 729
 730 /*
 731  * Register mxc i2c adapters
 732  */
 733 #ifdef CONFIG_SYS_I2C_MXC_I2C1
 734 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
 735                          mxc_i2c_read, mxc_i2c_write,
 736                          mxc_i2c_set_bus_speed,
 737                          CONFIG_SYS_MXC_I2C1_SPEED,
 738                          CONFIG_SYS_MXC_I2C1_SLAVE, 0)
 739 #endif
 740
 741 #ifdef CONFIG_SYS_I2C_MXC_I2C2
 742 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 743                          mxc_i2c_read, mxc_i2c_write,
 744                          mxc_i2c_set_bus_speed,
 745                          CONFIG_SYS_MXC_I2C2_SPEED,
 746                          CONFIG_SYS_MXC_I2C2_SLAVE, 1)
 747 #endif
 748
 749 #ifdef CONFIG_SYS_I2C_MXC_I2C3
 750 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
 751                          mxc_i2c_read, mxc_i2c_write,
 752                          mxc_i2c_set_bus_speed,
 753                          CONFIG_SYS_MXC_I2C3_SPEED,
 754                          CONFIG_SYS_MXC_I2C3_SLAVE, 2)
 755 #endif
 756
 757 #ifdef CONFIG_SYS_I2C_MXC_I2C4
 758 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
 759                          mxc_i2c_read, mxc_i2c_write,
 760                          mxc_i2c_set_bus_speed,
 761                          CONFIG_SYS_MXC_I2C4_SPEED,
 762                          CONFIG_SYS_MXC_I2C4_SLAVE, 3)
 763 #endif
 764
 765 #ifdef CONFIG_SYS_I2C_MXC_I2C5
 766 U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
 767                          mxc_i2c_read, mxc_i2c_write,
 768                          mxc_i2c_set_bus_speed,
 769                          CONFIG_SYS_MXC_I2C5_SPEED,
 770                          CONFIG_SYS_MXC_I2C5_SLAVE, 4)
 771 #endif
 772
 773 #ifdef CONFIG_SYS_I2C_MXC_I2C6
 774 U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
 775                          mxc_i2c_read, mxc_i2c_write,
 776                          mxc_i2c_set_bus_speed,
 777                          CONFIG_SYS_MXC_I2C6_SPEED,
 778                          CONFIG_SYS_MXC_I2C6_SLAVE, 5)
 779 #endif
 780
 781 #ifdef CONFIG_SYS_I2C_MXC_I2C7
 782 U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
 783                          mxc_i2c_read, mxc_i2c_write,
 784                          mxc_i2c_set_bus_speed,
 785                          CONFIG_SYS_MXC_I2C7_SPEED,
 786                          CONFIG_SYS_MXC_I2C7_SLAVE, 6)
 787 #endif
 788
 789 #ifdef CONFIG_SYS_I2C_MXC_I2C8
 790 U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
 791                          mxc_i2c_read, mxc_i2c_write,
 792                          mxc_i2c_set_bus_speed,
 793                          CONFIG_SYS_MXC_I2C8_SPEED,
 794                          CONFIG_SYS_MXC_I2C8_SLAVE, 7)
 795 #endif
 796
 797 #else
 798
 799 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 800 {
 801         struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 802
 803         return bus_i2c_set_bus_speed(i2c_bus, speed);
 804 }
 805
 806 static int mxc_i2c_probe(struct udevice *bus)
 807 {
 808         struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 809         const void *fdt = gd->fdt_blob;
 810         int node = dev_of_offset(bus);
 811         fdt_addr_t addr;
 812         int ret, ret2;
 813
 814         i2c_bus->driver_data = dev_get_driver_data(bus);
 815
 816         addr = devfdt_get_addr(bus);
 817         if (addr == FDT_ADDR_T_NONE)
 818                 return -EINVAL;
 819
 820         i2c_bus->base = addr;
 821         i2c_bus->index = bus->seq;
 822         i2c_bus->bus = bus;
 823
 824         /* Enable clk */
 825         ret = enable_i2c_clk(1, bus->seq);
 826         if (ret < 0)
 827                 return ret;
 828
 829         /*
 830          * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
 831          * Use gpio to force bus idle when necessary.
 832          */
 833         ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
 834         if (ret < 0) {
 835                 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
 836         } else {
 837                 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
 838                                 "scl-gpios", 0, &i2c_bus->scl_gpio,
 839                                 GPIOD_IS_OUT);
 840                 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
 841                                 "sda-gpios", 0, &i2c_bus->sda_gpio,
 842                                 GPIOD_IS_OUT);
 843                 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
 844                     !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
 845                     ret || ret2) {
 846                         dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
 847                         return -EINVAL;
 848                 }
 849         }
 850
 851         ret = i2c_idle_bus(i2c_bus);
 852         if (ret < 0) {
 853                 /* Disable clk */
 854                 enable_i2c_clk(0, bus->seq);
 855                 return ret;
 856         }
 857
 858         /*
 859          * Pinmux settings are in board file now, until pinmux is supported,
 860          * we can set pinmux here in probe function.
 861          */
 862
 863         debug("i2c : controller bus %d at %lu , speed %d: ",
 864               bus->seq, i2c_bus->base,
 865               i2c_bus->speed);
 866
 867         return 0;
 868 }
 869
 870 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 871                               u32 chip_flags)
 872 {
 873         int ret;
 874         struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 875
 876         ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
 877         if (ret < 0) {
 878                 debug("%s failed, ret = %d\n", __func__, ret);
 879                 return ret;
 880         }
 881
 882         i2c_imx_stop(i2c_bus);
 883
 884         return 0;
 885 }
 886
 887 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 888 {
 889         struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 890         int ret = 0;
 891         ulong base = i2c_bus->base;
 892         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 893                 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 894
 895         /*
 896          * Here the 3rd parameter addr and the 4th one alen are set to 0,
 897          * because here we only want to send out chip address. The register
 898          * address is wrapped in msg.
 899          */
 900         ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
 901         if (ret < 0) {
 902                 debug("i2c_init_transfer error: %d\n", ret);
 903                 return ret;
 904         }
 905
 906         for (; nmsgs > 0; nmsgs--, msg++) {
 907                 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
 908                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 909                 if (msg->flags & I2C_M_RD)
 910                         ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
 911                                             msg->len);
 912                 else {
 913                         ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
 914                                              msg->len);
 915                         if (ret)
 916                                 break;
 917                         if (next_is_read) {
 918                                 /* Reuse ret */
 919                                 ret = readb(base + (I2CR << reg_shift));
 920                                 ret |= I2CR_RSTA;
 921                                 writeb(ret, base + (I2CR << reg_shift));
 922
 923                                 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
 924                                 if (ret < 0) {
 925                                         i2c_imx_stop(i2c_bus);
 926                                         break;
 927                                 }
 928                         }
 929                 }
 930         }
 931
 932         if (ret)
 933                 debug("i2c_write: error sending\n");
 934
 935         i2c_imx_stop(i2c_bus);
 936
 937         return ret;
 938 }
 939
 940 static const struct dm_i2c_ops mxc_i2c_ops = {
 941         .xfer           = mxc_i2c_xfer,
 942         .probe_chip     = mxc_i2c_probe_chip,
 943         .set_bus_speed  = mxc_i2c_set_bus_speed,
 944 };
 945
 946 static const struct udevice_id mxc_i2c_ids[] = {
 947         { .compatible = "fsl,imx21-i2c", },
 948         { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
 949         {}
 950 };
 951
 952 U_BOOT_DRIVER(i2c_mxc) = {
 953         .name = "i2c_mxc",
 954         .id = UCLASS_I2C,
 955         .of_match = mxc_i2c_ids,
 956         .probe = mxc_i2c_probe,
 957         .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
 958         .ops = &mxc_i2c_ops,
 959 };
 960 #endif