1 // SPDX-License-Identifier: GPL-2.0+
3 * i2c driver for Freescale i.MX series
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
9 * Based on i2c-imx.c from linux kernel:
10 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
11 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
12 * Copyright (C) 2007 RightHand Technologies, Inc.
13 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
21 #include <dm/device_compat.h>
22 #include <linux/delay.h>
23 #include <linux/errno.h>
24 #include <asm/mach-imx/mxc_i2c.h>
25 #include <asm/mach-imx/sys_proto.h>
30 #include <dm/pinctrl.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define I2C_QUIRK_FLAG (1 << 0)
37 #define IMX_I2C_REGSHIFT 2
38 #define VF610_I2C_REGSHIFT 0
40 #define I2C_EARLY_INIT_INDEX 0
41 #ifdef CONFIG_SYS_I2C_IFDR_DIV
42 #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
44 #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
54 #define I2CR_IIEN (1 << 6)
55 #define I2CR_MSTA (1 << 5)
56 #define I2CR_MTX (1 << 4)
57 #define I2CR_TX_NO_AK (1 << 3)
58 #define I2CR_RSTA (1 << 2)
60 #define I2SR_ICF (1 << 7)
61 #define I2SR_IBB (1 << 5)
62 #define I2SR_IAL (1 << 4)
63 #define I2SR_IIF (1 << 1)
64 #define I2SR_RX_NO_AK (1 << 0)
67 #define I2CR_IEN (0 << 7)
68 #define I2CR_IDIS (1 << 7)
69 #define I2SR_IIF_CLEAR (1 << 1)
71 #define I2CR_IEN (1 << 7)
72 #define I2CR_IDIS (0 << 7)
73 #define I2SR_IIF_CLEAR (0 << 1)
77 static u16 i2c_clk_div[60][2] = {
78 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
79 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
80 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
81 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
82 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
83 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
84 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
85 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
86 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
87 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
88 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
89 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
90 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
91 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
92 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
95 static u16 i2c_clk_div[50][2] = {
96 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
97 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
98 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
99 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
100 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
101 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
102 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
103 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
104 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
105 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
106 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
107 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
108 { 3072, 0x1E }, { 3840, 0x1F }
112 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
113 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
115 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
116 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
118 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
119 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
121 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
122 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
125 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
126 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
128 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
129 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
131 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
132 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
134 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
135 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
139 * Calculate and set proper clock divider
141 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
143 unsigned int i2c_clk_rate;
147 #if defined(CONFIG_MX31)
148 struct clock_control_regs *sc_regs =
149 (struct clock_control_regs *)CCM_BASE;
151 /* start the required I2C clock */
152 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
156 /* Divider value calculation */
157 #if CONFIG_IS_ENABLED(CLK)
158 i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
160 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
163 div = (i2c_clk_rate + rate - 1) / rate;
164 if (div < i2c_clk_div[0][0])
166 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
167 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
169 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
172 /* Store divider value */
179 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
181 ulong base = i2c_bus->base;
182 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
183 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
184 u8 idx = i2c_clk_div[clk_idx][1];
185 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
190 /* Store divider value */
191 writeb(idx, base + (IFDR << reg_shift));
194 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
195 writeb(0, base + (I2SR << reg_shift));
199 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
200 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
201 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
203 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
207 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
208 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
209 ulong base = i2c_bus->base;
210 ulong start_time = get_timer(0);
212 sr = readb(base + (I2SR << reg_shift));
215 writeb(sr | I2SR_IAL, base +
216 (I2SR << reg_shift));
218 writeb(sr & ~I2SR_IAL, base +
219 (I2SR << reg_shift));
220 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
221 __func__, sr, readb(base + (I2CR << reg_shift)),
225 if ((sr & (state >> 8)) == (unsigned char)state)
228 elapsed = get_timer(start_time);
229 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
232 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
233 sr, readb(base + (I2CR << reg_shift)), state);
237 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
240 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
241 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
242 ulong base = i2c_bus->base;
244 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
245 writeb(byte, base + (I2DR << reg_shift));
247 ret = wait_for_sr_state(i2c_bus, ST_IIF);
250 if (ret & I2SR_RX_NO_AK)
256 * Stub implementations for outer i2c slave operations.
258 void __i2c_force_reset_slave(void)
261 void i2c_force_reset_slave(void)
262 __attribute__((weak, alias("__i2c_force_reset_slave")));
265 * Stop I2C transaction
267 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
270 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
271 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
272 ulong base = i2c_bus->base;
273 unsigned int temp = readb(base + (I2CR << reg_shift));
275 temp &= ~(I2CR_MSTA | I2CR_MTX);
276 writeb(temp, base + (I2CR << reg_shift));
277 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
279 printf("%s:trigger stop failed\n", __func__);
283 * Send start signal, chip address and
284 * write register address
286 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
291 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
292 ulong base = i2c_bus->base;
293 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
295 /* Reset i2c slave */
296 i2c_force_reset_slave();
298 /* Enable I2C controller */
300 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
302 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
305 writeb(I2CR_IEN, base + (I2CR << reg_shift));
306 /* Wait for controller to be stable */
310 if (readb(base + (IADR << reg_shift)) == (chip << 1))
311 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
312 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
313 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
317 /* Start I2C transaction */
318 temp = readb(base + (I2CR << reg_shift));
320 writeb(temp, base + (I2CR << reg_shift));
322 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
326 temp |= I2CR_MTX | I2CR_TX_NO_AK;
327 writeb(temp, base + (I2CR << reg_shift));
330 /* write slave address */
331 ret = tx_byte(i2c_bus, chip << 1);
336 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
345 #if !defined(I2C2_BASE_ADDR)
346 #define I2C2_BASE_ADDR 0
349 #if !defined(I2C3_BASE_ADDR)
350 #define I2C3_BASE_ADDR 0
353 #if !defined(I2C4_BASE_ADDR)
354 #define I2C4_BASE_ADDR 0
357 #if !defined(I2C5_BASE_ADDR)
358 #define I2C5_BASE_ADDR 0
361 #if !defined(I2C6_BASE_ADDR)
362 #define I2C6_BASE_ADDR 0
365 #if !defined(I2C7_BASE_ADDR)
366 #define I2C7_BASE_ADDR 0
369 #if !defined(I2C8_BASE_ADDR)
370 #define I2C8_BASE_ADDR 0
373 static struct mxc_i2c_bus mxc_i2c_buses[] = {
374 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
375 defined(CONFIG_FSL_LAYERSCAPE)
376 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
377 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
378 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
379 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
380 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
381 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
382 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
383 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
385 { 0, I2C1_BASE_ADDR, 0 },
386 { 1, I2C2_BASE_ADDR, 0 },
387 { 2, I2C3_BASE_ADDR, 0 },
388 { 3, I2C4_BASE_ADDR, 0 },
389 { 4, I2C5_BASE_ADDR, 0 },
390 { 5, I2C6_BASE_ADDR, 0 },
391 { 6, I2C7_BASE_ADDR, 0 },
392 { 7, I2C8_BASE_ADDR, 0 },
396 #ifndef CONFIG_DM_I2C
397 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
399 if (i2c_bus && i2c_bus->idle_bus_fn)
400 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
405 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
407 * scl-gpios: specify the gpio related to SCL pin
408 * sda-gpios: specify the gpio related to SDA pin
409 * add pinctrl to configure i2c pins to gpio function for i2c
410 * bus recovery, call it "gpio" state
413 * The i2c_idle_bus is an implementation following Linux Kernel.
415 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
417 struct udevice *bus = i2c_bus->bus;
418 struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
419 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
420 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
421 int sda, scl, idle_sclks;
423 ulong elapsed, start_time;
425 if (pinctrl_select_state(bus, "gpio")) {
426 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
428 * GPIO pinctrl for i2c force idle is not a must,
429 * but it is strongly recommended to be used.
430 * Because it can help you to recover from bad
431 * i2c bus state. Do not return failure, because
437 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
438 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
439 scl = dm_gpio_get_value(scl_gpio);
440 sda = dm_gpio_get_value(sda_gpio);
442 if ((sda & scl) == 1)
443 goto exit; /* Bus is idle already */
446 * In most cases it is just enough to generate 8 + 1 SCLK
447 * clocks to recover I2C slave device from 'stuck' state
448 * (when for example SW reset was performed, in the middle of
451 * However, there are devices which send data in packets of
452 * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
457 if (i2c->max_transaction_bytes > 0)
458 idle_sclks = i2c->max_transaction_bytes * 8 + 1;
459 /* Send high and low on the SCL line */
460 for (i = 0; i < idle_sclks; i++) {
461 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
462 dm_gpio_set_value(scl_gpio, 0);
464 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
467 start_time = get_timer(0);
469 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
470 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
471 scl = dm_gpio_get_value(scl_gpio);
472 sda = dm_gpio_get_value(sda_gpio);
473 if ((sda & scl) == 1)
476 elapsed = get_timer(start_time);
477 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
479 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
485 pinctrl_select_state(bus, "default");
490 * Early init I2C for prepare read the clk through I2C.
492 void i2c_early_init_f(void)
494 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
495 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
496 & I2C_QUIRK_FLAG ? true : false;
497 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
499 /* Set I2C divider value */
500 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
502 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
503 writeb(0, base + (I2SR << reg_shift));
505 writeb(I2CR_IEN, base + (I2CR << reg_shift));
508 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
513 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
514 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
519 for (retry = 0; retry < 3; retry++) {
520 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
523 i2c_imx_stop(i2c_bus);
524 if (ret == -EREMOTEIO)
527 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
529 if (ret != -ERESTART)
530 /* Disable controller */
531 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
533 if (i2c_idle_bus(i2c_bus) < 0)
536 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
541 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
546 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
547 debug("write_data: ");
548 /* use rc for counter */
549 for (i = 0; i < len; ++i)
550 debug(" 0x%02x", buf[i]);
553 for (i = 0; i < len; i++) {
554 ret = tx_byte(i2c_bus, buf[i]);
556 debug("i2c_write_data(): rc=%d\n", ret);
564 /* Will generate a STOP after the last byte if "last" is true, i.e. this is the
565 * final message of a transaction. If not, it switches the bus back to TX mode
566 * and does not send a STOP, leaving the bus in a state where a repeated start
567 * and address can be sent for another message.
569 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
575 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
576 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
577 ulong base = i2c_bus->base;
579 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
581 /* setup bus to read data */
582 temp = readb(base + (I2CR << reg_shift));
583 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
585 temp |= I2CR_TX_NO_AK;
586 writeb(temp, base + (I2CR << reg_shift));
587 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
588 /* dummy read to clear ICF */
589 readb(base + (I2DR << reg_shift));
592 for (i = 0; i < len; i++) {
593 ret = wait_for_sr_state(i2c_bus, ST_IIF);
595 debug("i2c_read_data(): ret=%d\n", ret);
596 i2c_imx_stop(i2c_bus);
600 if (i == (len - 1)) {
601 /* Final byte has already been received by master! When
602 * we read it from I2DR, the master will start another
603 * cycle. We must program it first to send a STOP or
604 * switch to TX to avoid this.
607 i2c_imx_stop(i2c_bus);
609 /* Final read, no stop, switch back to tx */
610 temp = readb(base + (I2CR << reg_shift));
611 temp |= I2CR_MTX | I2CR_TX_NO_AK;
612 writeb(temp, base + (I2CR << reg_shift));
614 } else if (i == (len - 2)) {
615 /* Master has already recevied penultimate byte. When
616 * we read it from I2DR, master will start RX of final
617 * byte. We must set TX_NO_AK now so it does not ACK
620 temp = readb(base + (I2CR << reg_shift));
621 temp |= I2CR_TX_NO_AK;
622 writeb(temp, base + (I2CR << reg_shift));
625 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
626 buf[i] = readb(base + (I2DR << reg_shift));
629 /* reuse ret for counter*/
630 for (ret = 0; ret < len; ++ret)
631 debug(" 0x%02x", buf[ret]);
634 /* It is not clear to me that this is necessary */
636 i2c_imx_stop(i2c_bus);
640 int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
645 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
646 __attribute__((weak, alias("__enable_i2c_clk")));
648 #ifndef CONFIG_DM_I2C
650 * Read data from I2C device
652 * The transactions use the syntax defined in the Linux kernel I2C docs.
654 * If alen is > 0, then this function will send a transaction of the form:
655 * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
656 * This is a normal I2C register read: writing the register address, then doing
657 * a repeated start and reading the data.
659 * If alen == 0, then we get this transaction:
660 * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
661 * This is somewhat unusual, though valid, transaction. It addresses the chip
662 * in write mode, but doesn't actually write any register address or data, then
663 * does a repeated start and reads data.
665 * If alen < 0, then we get this transaction:
666 * S Chip Rd [A] [data] A ... NA P
667 * The chip is addressed in read mode and then data is read. No register
668 * address is written first. This is perfectly valid on most devices and
669 * required on some (usually those that don't act like an array of registers).
671 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
672 int alen, u8 *buf, int len)
676 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
677 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
678 ulong base = i2c_bus->base;
680 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
685 temp = readb(base + (I2CR << reg_shift));
687 writeb(temp, base + (I2CR << reg_shift));
690 ret = tx_byte(i2c_bus, (chip << 1) | 1);
692 i2c_imx_stop(i2c_bus);
696 ret = i2c_read_data(i2c_bus, chip, buf, len, true);
698 i2c_imx_stop(i2c_bus);
703 * Write data to I2C device
705 * If alen > 0, we get this transaction:
706 * S Chip Wr [A] addr [A] data [A] ... [A] P
707 * An ordinary write register command.
709 * If alen == 0, then we get this:
710 * S Chip Wr [A] data [A] ... [A] P
711 * This is a simple I2C write.
713 * If alen < 0, then we get this:
714 * S data [A] ... [A] P
715 * This is most likely NOT something that should be used. It doesn't send the
716 * chip address first, so in effect, the first byte of data will be used as the
719 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
720 int alen, const u8 *buf, int len)
724 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
728 ret = i2c_write_data(i2c_bus, chip, buf, len);
730 i2c_imx_stop(i2c_bus);
735 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
737 return &mxc_i2c_buses[adap->hwadapnr];
740 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
741 uint addr, int alen, uint8_t *buffer,
744 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
747 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
748 uint addr, int alen, uint8_t *buffer,
751 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
755 * Test if a chip at a given address responds (probe the chip)
757 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
759 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
762 void bus_i2c_init(int index, int speed, int unused,
763 int (*idle_bus_fn)(void *p), void *idle_bus_data)
767 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
768 debug("Error i2c index\n");
772 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
773 if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
774 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
775 (ulong)mxc_i2c_buses[index].base);
781 * Warning: Be careful to allow the assignment to a static
782 * variable here. This function could be called while U-Boot is
783 * still running in flash memory. So such assignment is equal
784 * to write data to flash without erasing.
787 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
789 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
791 ret = enable_i2c_clk(1, index);
793 debug("I2C-%d clk fail to enable.\n", index);
797 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
805 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
807 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
813 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
815 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
819 * Register mxc i2c adapters
821 #ifdef CONFIG_SYS_I2C_MXC_I2C1
822 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
823 mxc_i2c_read, mxc_i2c_write,
824 mxc_i2c_set_bus_speed,
825 CONFIG_SYS_MXC_I2C1_SPEED,
826 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
829 #ifdef CONFIG_SYS_I2C_MXC_I2C2
830 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
831 mxc_i2c_read, mxc_i2c_write,
832 mxc_i2c_set_bus_speed,
833 CONFIG_SYS_MXC_I2C2_SPEED,
834 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
837 #ifdef CONFIG_SYS_I2C_MXC_I2C3
838 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
839 mxc_i2c_read, mxc_i2c_write,
840 mxc_i2c_set_bus_speed,
841 CONFIG_SYS_MXC_I2C3_SPEED,
842 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
845 #ifdef CONFIG_SYS_I2C_MXC_I2C4
846 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
847 mxc_i2c_read, mxc_i2c_write,
848 mxc_i2c_set_bus_speed,
849 CONFIG_SYS_MXC_I2C4_SPEED,
850 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
853 #ifdef CONFIG_SYS_I2C_MXC_I2C5
854 U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
855 mxc_i2c_read, mxc_i2c_write,
856 mxc_i2c_set_bus_speed,
857 CONFIG_SYS_MXC_I2C5_SPEED,
858 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
861 #ifdef CONFIG_SYS_I2C_MXC_I2C6
862 U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
863 mxc_i2c_read, mxc_i2c_write,
864 mxc_i2c_set_bus_speed,
865 CONFIG_SYS_MXC_I2C6_SPEED,
866 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
869 #ifdef CONFIG_SYS_I2C_MXC_I2C7
870 U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
871 mxc_i2c_read, mxc_i2c_write,
872 mxc_i2c_set_bus_speed,
873 CONFIG_SYS_MXC_I2C7_SPEED,
874 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
877 #ifdef CONFIG_SYS_I2C_MXC_I2C8
878 U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
879 mxc_i2c_read, mxc_i2c_write,
880 mxc_i2c_set_bus_speed,
881 CONFIG_SYS_MXC_I2C8_SPEED,
882 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
887 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
889 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
891 return bus_i2c_set_bus_speed(i2c_bus, speed);
894 static int mxc_i2c_probe(struct udevice *bus)
896 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
897 const void *fdt = gd->fdt_blob;
898 int node = dev_of_offset(bus);
902 i2c_bus->driver_data = dev_get_driver_data(bus);
904 addr = devfdt_get_addr(bus);
905 if (addr == FDT_ADDR_T_NONE)
908 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
909 if (i2c_fused((ulong)addr)) {
910 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
916 i2c_bus->base = addr;
917 i2c_bus->index = bus->seq;
921 #if CONFIG_IS_ENABLED(CLK)
922 ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
924 printf("Failed to get i2c clk\n");
927 ret = clk_enable(&i2c_bus->per_clk);
929 printf("Failed to enable i2c clk\n");
933 ret = enable_i2c_clk(1, bus->seq);
939 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
940 * Use gpio to force bus idle when necessary.
942 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
944 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
946 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
947 "scl-gpios", 0, &i2c_bus->scl_gpio,
949 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
950 "sda-gpios", 0, &i2c_bus->sda_gpio,
952 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
953 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
955 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
961 * Pinmux settings are in board file now, until pinmux is supported,
962 * we can set pinmux here in probe function.
965 debug("i2c : controller bus %d at %lu , speed %d: ",
966 bus->seq, i2c_bus->base,
972 /* Sends: S Addr Wr [A|NA] P */
973 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
977 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
979 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
981 debug("%s failed, ret = %d\n", __func__, ret);
985 i2c_imx_stop(i2c_bus);
990 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
992 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
994 ulong base = i2c_bus->base;
995 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
996 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
999 /* Here address len is set to -1 to not send any address at first.
1000 * Otherwise i2c_init_transfer will send the chip address with write
1001 * mode set. This is wrong if the 1st message is read.
1003 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
1005 debug("i2c_init_transfer error: %d\n", ret);
1009 read_mode = -1; /* So it's always different on the first message */
1010 for (; nmsgs > 0; nmsgs--, msg++) {
1011 const int msg_is_read = !!(msg->flags & I2C_M_RD);
1013 debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
1014 msg->len, msg_is_read ? 'R' : 'W');
1016 if (msg_is_read != read_mode) {
1017 /* Send repeated start if not 1st message */
1018 if (read_mode != -1) {
1019 debug("i2c_xfer: [RSTART]\n");
1020 ret = readb(base + (I2CR << reg_shift));
1022 writeb(ret, base + (I2CR << reg_shift));
1024 debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
1025 msg_is_read ? 'R' : 'W');
1026 ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
1028 debug("i2c_xfer: [STOP]\n");
1029 i2c_imx_stop(i2c_bus);
1032 read_mode = msg_is_read;
1035 if (msg->flags & I2C_M_RD)
1036 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1037 msg->len, nmsgs == 1 ||
1038 (msg->flags & I2C_M_STOP));
1040 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1048 debug("i2c_write: error sending\n");
1050 i2c_imx_stop(i2c_bus);
1055 static const struct dm_i2c_ops mxc_i2c_ops = {
1056 .xfer = mxc_i2c_xfer,
1057 .probe_chip = mxc_i2c_probe_chip,
1058 .set_bus_speed = mxc_i2c_set_bus_speed,
1061 static const struct udevice_id mxc_i2c_ids[] = {
1062 { .compatible = "fsl,imx21-i2c", },
1063 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
1067 U_BOOT_DRIVER(i2c_mxc) = {
1070 .of_match = mxc_i2c_ids,
1071 .probe = mxc_i2c_probe,
1072 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
1073 .ops = &mxc_i2c_ops,
1074 .flags = DM_FLAG_PRE_RELOC,