drivers/i2c/mxc_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * i2c driver for Freescale i.MX series
   4  *
   5  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   6  * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
   7  *
   8  * Based on i2c-imx.c from linux kernel:
   9  *  Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
  10  *  Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  11  *  Copyright (C) 2007 RightHand Technologies, Inc.
  12  *  Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  13  *
  14  */
  15
  16 #include <common.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <linux/errno.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/io.h>
  22 #include <i2c.h>
  23 #include <watchdog.h>
  24 #include <dm.h>
  25 #include <dm/pinctrl.h>
  26 #include <fdtdec.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #define I2C_QUIRK_FLAG          (1 << 0)
  31
  32 #define IMX_I2C_REGSHIFT        2
  33 #define VF610_I2C_REGSHIFT      0
  34
  35 #define I2C_EARLY_INIT_INDEX            0
  36 #ifdef CONFIG_SYS_I2C_IFDR_DIV
  37 #define I2C_IFDR_DIV_CONSERVATIVE       CONFIG_SYS_I2C_IFDR_DIV
  38 #else
  39 #define I2C_IFDR_DIV_CONSERVATIVE       0x7e
  40 #endif
  41
  42 /* Register index */
  43 #define IADR    0
  44 #define IFDR    1
  45 #define I2CR    2
  46 #define I2SR    3
  47 #define I2DR    4
  48
  49 #define I2CR_IIEN       (1 << 6)
  50 #define I2CR_MSTA       (1 << 5)
  51 #define I2CR_MTX        (1 << 4)
  52 #define I2CR_TX_NO_AK   (1 << 3)
  53 #define I2CR_RSTA       (1 << 2)
  54
  55 #define I2SR_ICF        (1 << 7)
  56 #define I2SR_IBB        (1 << 5)
  57 #define I2SR_IAL        (1 << 4)
  58 #define I2SR_IIF        (1 << 1)
  59 #define I2SR_RX_NO_AK   (1 << 0)
  60
  61 #ifdef I2C_QUIRK_REG
  62 #define I2CR_IEN        (0 << 7)
  63 #define I2CR_IDIS       (1 << 7)
  64 #define I2SR_IIF_CLEAR  (1 << 1)
  65 #else
  66 #define I2CR_IEN        (1 << 7)
  67 #define I2CR_IDIS       (0 << 7)
  68 #define I2SR_IIF_CLEAR  (0 << 1)
  69 #endif
  70
  71 #ifdef I2C_QUIRK_REG
  72 static u16 i2c_clk_div[60][2] = {
  73         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
  74         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
  75         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
  76         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
  77         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
  78         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
  79         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
  80         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
  81         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
  82         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
  83         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
  84         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
  85         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
  86         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
  87         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
  88 };
  89 #else
  90 static u16 i2c_clk_div[50][2] = {
  91         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
  92         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
  93         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
  94         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
  95         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
  96         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
  97         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
  98         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
  99         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 100         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 101         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 102         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 103         { 3072, 0x1E }, { 3840, 0x1F }
 104 };
 105 #endif
 106
 107 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
 108 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
 109 #endif
 110 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
 111 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
 112 #endif
 113 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
 114 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
 115 #endif
 116 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
 117 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
 118 #endif
 119
 120 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
 121 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
 122 #endif
 123 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
 124 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
 125 #endif
 126 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
 127 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
 128 #endif
 129 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
 130 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
 131 #endif
 132
 133 /*
 134  * Calculate and set proper clock divider
 135  */
 136 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
 137 {
 138         unsigned int i2c_clk_rate;
 139         unsigned int div;
 140         u8 clk_div;
 141
 142 #if defined(CONFIG_MX31)
 143         struct clock_control_regs *sc_regs =
 144                 (struct clock_control_regs *)CCM_BASE;
 145
 146         /* start the required I2C clock */
 147         writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
 148                 &sc_regs->cgr0);
 149 #endif
 150
 151         /* Divider value calculation */
 152         i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
 153         div = (i2c_clk_rate + rate - 1) / rate;
 154         if (div < i2c_clk_div[0][0])
 155                 clk_div = 0;
 156         else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
 157                 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
 158         else
 159                 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
 160                         ;
 161
 162         /* Store divider value */
 163         return clk_div;
 164 }
 165
 166 /*
 167  * Set I2C Bus speed
 168  */
 169 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
 170 {
 171         ulong base = i2c_bus->base;
 172         bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
 173         u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
 174         u8 idx = i2c_clk_div[clk_idx][1];
 175         int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 176
 177         if (!base)
 178                 return -EINVAL;
 179
 180         /* Store divider value */
 181         writeb(idx, base + (IFDR << reg_shift));
 182
 183         /* Reset module */
 184         writeb(I2CR_IDIS, base + (I2CR << reg_shift));
 185         writeb(0, base + (I2SR << reg_shift));
 186         return 0;
 187 }
 188
 189 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
 190 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
 191 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
 192
 193 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
 194 {
 195         unsigned sr;
 196         ulong elapsed;
 197         bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
 198         int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 199         ulong base = i2c_bus->base;
 200         ulong start_time = get_timer(0);
 201         for (;;) {
 202                 sr = readb(base + (I2SR << reg_shift));
 203                 if (sr & I2SR_IAL) {
 204                         if (quirk)
 205                                 writeb(sr | I2SR_IAL, base +
 206                                        (I2SR << reg_shift));
 207                         else
 208                                 writeb(sr & ~I2SR_IAL, base +
 209                                        (I2SR << reg_shift));
 210                         printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
 211                                 __func__, sr, readb(base + (I2CR << reg_shift)),
 212                                 state);
 213                         return -ERESTART;
 214                 }
 215                 if ((sr & (state >> 8)) == (unsigned char)state)
 216                         return sr;
 217                 WATCHDOG_RESET();
 218                 elapsed = get_timer(start_time);
 219                 if (elapsed > (CONFIG_SYS_HZ / 10))     /* .1 seconds */
 220                         break;
 221         }
 222         printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
 223                sr, readb(base + (I2CR << reg_shift)), state);
 224         return -ETIMEDOUT;
 225 }
 226
 227 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
 228 {
 229         int ret;
 230         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 231                         VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 232         ulong base = i2c_bus->base;
 233
 234         writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 235         writeb(byte, base + (I2DR << reg_shift));
 236
 237         ret = wait_for_sr_state(i2c_bus, ST_IIF);
 238         if (ret < 0)
 239                 return ret;
 240         if (ret & I2SR_RX_NO_AK)
 241                 return -EREMOTEIO;
 242         return 0;
 243 }
 244
 245 /*
 246  * Stub implementations for outer i2c slave operations.
 247  */
 248 void __i2c_force_reset_slave(void)
 249 {
 250 }
 251 void i2c_force_reset_slave(void)
 252         __attribute__((weak, alias("__i2c_force_reset_slave")));
 253
 254 /*
 255  * Stop I2C transaction
 256  */
 257 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
 258 {
 259         int ret;
 260         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 261                         VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 262         ulong base = i2c_bus->base;
 263         unsigned int temp = readb(base + (I2CR << reg_shift));
 264
 265         temp &= ~(I2CR_MSTA | I2CR_MTX);
 266         writeb(temp, base + (I2CR << reg_shift));
 267         ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
 268         if (ret < 0)
 269                 printf("%s:trigger stop failed\n", __func__);
 270 }
 271
 272 /*
 273  * Send start signal, chip address and
 274  * write register address
 275  */
 276 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
 277                               u32 addr, int alen)
 278 {
 279         unsigned int temp;
 280         int ret;
 281         bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
 282         ulong base = i2c_bus->base;
 283         int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 284
 285         /* Reset i2c slave */
 286         i2c_force_reset_slave();
 287
 288         /* Enable I2C controller */
 289         if (quirk)
 290                 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
 291         else
 292                 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
 293
 294         if (ret) {
 295                 writeb(I2CR_IEN, base + (I2CR << reg_shift));
 296                 /* Wait for controller to be stable */
 297                 udelay(50);
 298         }
 299
 300         if (readb(base + (IADR << reg_shift)) == (chip << 1))
 301                 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
 302         writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 303         ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
 304         if (ret < 0)
 305                 return ret;
 306
 307         /* Start I2C transaction */
 308         temp = readb(base + (I2CR << reg_shift));
 309         temp |= I2CR_MSTA;
 310         writeb(temp, base + (I2CR << reg_shift));
 311
 312         ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
 313         if (ret < 0)
 314                 return ret;
 315
 316         temp |= I2CR_MTX | I2CR_TX_NO_AK;
 317         writeb(temp, base + (I2CR << reg_shift));
 318
 319         if (alen >= 0)  {
 320                 /* write slave address */
 321                 ret = tx_byte(i2c_bus, chip << 1);
 322                 if (ret < 0)
 323                         return ret;
 324
 325                 while (alen--) {
 326                         ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
 327                         if (ret < 0)
 328                                 return ret;
 329                 }
 330         }
 331
 332         return 0;
 333 }
 334
 335 #ifndef CONFIG_DM_I2C
 336 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
 337 {
 338         if (i2c_bus && i2c_bus->idle_bus_fn)
 339                 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
 340         return 0;
 341 }
 342 #else
 343 /*
 344  * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
 345  * "
 346  *  scl-gpios: specify the gpio related to SCL pin
 347  *  sda-gpios: specify the gpio related to SDA pin
 348  *  add pinctrl to configure i2c pins to gpio function for i2c
 349  *  bus recovery, call it "gpio" state
 350  * "
 351  *
 352  * The i2c_idle_bus is an implementation following Linux Kernel.
 353  */
 354 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
 355 {
 356         struct udevice *bus = i2c_bus->bus;
 357         struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
 358         struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
 359         struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
 360         int sda, scl, idle_sclks;
 361         int i, ret = 0;
 362         ulong elapsed, start_time;
 363
 364         if (pinctrl_select_state(bus, "gpio")) {
 365                 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
 366                 /*
 367                  * GPIO pinctrl for i2c force idle is not a must,
 368                  * but it is strongly recommended to be used.
 369                  * Because it can help you to recover from bad
 370                  * i2c bus state. Do not return failure, because
 371                  * it is not a must.
 372                  */
 373                 return 0;
 374         }
 375
 376         dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
 377         dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
 378         scl = dm_gpio_get_value(scl_gpio);
 379         sda = dm_gpio_get_value(sda_gpio);
 380
 381         if ((sda & scl) == 1)
 382                 goto exit;              /* Bus is idle already */
 383
 384         /*
 385          * In most cases it is just enough to generate 8 + 1 SCLK
 386          * clocks to recover I2C slave device from 'stuck' state
 387          * (when for example SW reset was performed, in the middle of
 388          * I2C transmission).
 389          *
 390          * However, there are devices which send data in packets of
 391          * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
 392          * clocks.
 393          */
 394         idle_sclks = 8 + 1;
 395
 396         if (i2c->max_transaction_bytes > 0)
 397                 idle_sclks = i2c->max_transaction_bytes * 8 + 1;
 398         /* Send high and low on the SCL line */
 399         for (i = 0; i < idle_sclks; i++) {
 400                 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
 401                 dm_gpio_set_value(scl_gpio, 0);
 402                 udelay(50);
 403                 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
 404                 udelay(50);
 405         }
 406         start_time = get_timer(0);
 407         for (;;) {
 408                 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
 409                 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
 410                 scl = dm_gpio_get_value(scl_gpio);
 411                 sda = dm_gpio_get_value(sda_gpio);
 412                 if ((sda & scl) == 1)
 413                         break;
 414                 WATCHDOG_RESET();
 415                 elapsed = get_timer(start_time);
 416                 if (elapsed > (CONFIG_SYS_HZ / 5)) {    /* .2 seconds */
 417                         ret = -EBUSY;
 418                         printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
 419                         break;
 420                 }
 421         }
 422
 423 exit:
 424         pinctrl_select_state(bus, "default");
 425         return ret;
 426 }
 427 #endif
 428
 429 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
 430                              u32 addr, int alen)
 431 {
 432         int retry;
 433         int ret;
 434         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 435                         VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 436
 437         if (!i2c_bus->base)
 438                 return -EINVAL;
 439
 440         for (retry = 0; retry < 3; retry++) {
 441                 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
 442                 if (ret >= 0)
 443                         return 0;
 444                 i2c_imx_stop(i2c_bus);
 445                 if (ret == -EREMOTEIO)
 446                         return ret;
 447
 448                 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
 449                                 retry);
 450                 if (ret != -ERESTART)
 451                         /* Disable controller */
 452                         writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
 453                 udelay(100);
 454                 if (i2c_idle_bus(i2c_bus) < 0)
 455                         break;
 456         }
 457         printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
 458         return ret;
 459 }
 460
 461
 462 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
 463                           int len)
 464 {
 465         int i, ret = 0;
 466
 467         debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
 468         debug("write_data: ");
 469         /* use rc for counter */
 470         for (i = 0; i < len; ++i)
 471                 debug(" 0x%02x", buf[i]);
 472         debug("\n");
 473
 474         for (i = 0; i < len; i++) {
 475                 ret = tx_byte(i2c_bus, buf[i]);
 476                 if (ret < 0) {
 477                         debug("i2c_write_data(): rc=%d\n", ret);
 478                         break;
 479                 }
 480         }
 481
 482         return ret;
 483 }
 484
 485 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
 486                          int len)
 487 {
 488         int ret;
 489         unsigned int temp;
 490         int i;
 491         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 492                         VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 493         ulong base = i2c_bus->base;
 494
 495         debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
 496
 497         /* setup bus to read data */
 498         temp = readb(base + (I2CR << reg_shift));
 499         temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
 500         if (len == 1)
 501                 temp |= I2CR_TX_NO_AK;
 502         writeb(temp, base + (I2CR << reg_shift));
 503         writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 504         /* dummy read to clear ICF */
 505         readb(base + (I2DR << reg_shift));
 506
 507         /* read data */
 508         for (i = 0; i < len; i++) {
 509                 ret = wait_for_sr_state(i2c_bus, ST_IIF);
 510                 if (ret < 0) {
 511                         debug("i2c_read_data(): ret=%d\n", ret);
 512                         i2c_imx_stop(i2c_bus);
 513                         return ret;
 514                 }
 515
 516                 /*
 517                  * It must generate STOP before read I2DR to prevent
 518                  * controller from generating another clock cycle
 519                  */
 520                 if (i == (len - 1)) {
 521                         i2c_imx_stop(i2c_bus);
 522                 } else if (i == (len - 2)) {
 523                         temp = readb(base + (I2CR << reg_shift));
 524                         temp |= I2CR_TX_NO_AK;
 525                         writeb(temp, base + (I2CR << reg_shift));
 526                 }
 527                 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 528                 buf[i] = readb(base + (I2DR << reg_shift));
 529         }
 530
 531         /* reuse ret for counter*/
 532         for (ret = 0; ret < len; ++ret)
 533                 debug(" 0x%02x", buf[ret]);
 534         debug("\n");
 535
 536         i2c_imx_stop(i2c_bus);
 537         return 0;
 538 }
 539
 540 #ifndef CONFIG_DM_I2C
 541 /*
 542  * Read data from I2C device
 543  */
 544 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
 545                         int alen, u8 *buf, int len)
 546 {
 547         int ret = 0;
 548         u32 temp;
 549         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 550                 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 551         ulong base = i2c_bus->base;
 552
 553         ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
 554         if (ret < 0)
 555                 return ret;
 556
 557         if (alen >= 0) {
 558                 temp = readb(base + (I2CR << reg_shift));
 559                 temp |= I2CR_RSTA;
 560                 writeb(temp, base + (I2CR << reg_shift));
 561         }
 562
 563         ret = tx_byte(i2c_bus, (chip << 1) | 1);
 564         if (ret < 0) {
 565                 i2c_imx_stop(i2c_bus);
 566                 return ret;
 567         }
 568
 569         ret = i2c_read_data(i2c_bus, chip, buf, len);
 570
 571         i2c_imx_stop(i2c_bus);
 572         return ret;
 573 }
 574
 575 /*
 576  * Write data to I2C device
 577  */
 578 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
 579                          int alen, const u8 *buf, int len)
 580 {
 581         int ret = 0;
 582
 583         ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
 584         if (ret < 0)
 585                 return ret;
 586
 587         ret = i2c_write_data(i2c_bus, chip, buf, len);
 588
 589         i2c_imx_stop(i2c_bus);
 590
 591         return ret;
 592 }
 593
 594 #if !defined(I2C2_BASE_ADDR)
 595 #define I2C2_BASE_ADDR  0
 596 #endif
 597
 598 #if !defined(I2C3_BASE_ADDR)
 599 #define I2C3_BASE_ADDR  0
 600 #endif
 601
 602 #if !defined(I2C4_BASE_ADDR)
 603 #define I2C4_BASE_ADDR  0
 604 #endif
 605
 606 #if !defined(I2C5_BASE_ADDR)
 607 #define I2C5_BASE_ADDR 0
 608 #endif
 609
 610 #if !defined(I2C6_BASE_ADDR)
 611 #define I2C6_BASE_ADDR 0
 612 #endif
 613
 614 #if !defined(I2C7_BASE_ADDR)
 615 #define I2C7_BASE_ADDR 0
 616 #endif
 617
 618 #if !defined(I2C8_BASE_ADDR)
 619 #define I2C8_BASE_ADDR 0
 620 #endif
 621
 622 static struct mxc_i2c_bus mxc_i2c_buses[] = {
 623 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
 624         defined(CONFIG_FSL_LAYERSCAPE)
 625         { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
 626         { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
 627         { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
 628         { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
 629         { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
 630         { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
 631         { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
 632         { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
 633 #else
 634         { 0, I2C1_BASE_ADDR, 0 },
 635         { 1, I2C2_BASE_ADDR, 0 },
 636         { 2, I2C3_BASE_ADDR, 0 },
 637         { 3, I2C4_BASE_ADDR, 0 },
 638         { 4, I2C5_BASE_ADDR, 0 },
 639         { 5, I2C6_BASE_ADDR, 0 },
 640         { 6, I2C7_BASE_ADDR, 0 },
 641         { 7, I2C8_BASE_ADDR, 0 },
 642 #endif
 643 };
 644
 645 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
 646 {
 647         return &mxc_i2c_buses[adap->hwadapnr];
 648 }
 649
 650 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
 651                                 uint addr, int alen, uint8_t *buffer,
 652                                 int len)
 653 {
 654         return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
 655 }
 656
 657 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
 658                                 uint addr, int alen, uint8_t *buffer,
 659                                 int len)
 660 {
 661         return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
 662 }
 663
 664 /*
 665  * Test if a chip at a given address responds (probe the chip)
 666  */
 667 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 668 {
 669         return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
 670 }
 671
 672 int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 673 {
 674         return 1;
 675 }
 676 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 677         __attribute__((weak, alias("__enable_i2c_clk")));
 678
 679 void bus_i2c_init(int index, int speed, int unused,
 680                   int (*idle_bus_fn)(void *p), void *idle_bus_data)
 681 {
 682         int ret;
 683
 684         if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
 685                 debug("Error i2c index\n");
 686                 return;
 687         }
 688
 689         /*
 690          * Warning: Be careful to allow the assignment to a static
 691          * variable here. This function could be called while U-Boot is
 692          * still running in flash memory. So such assignment is equal
 693          * to write data to flash without erasing.
 694          */
 695         if (idle_bus_fn)
 696                 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
 697         if (idle_bus_data)
 698                 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
 699
 700         ret = enable_i2c_clk(1, index);
 701         if (ret < 0) {
 702                 debug("I2C-%d clk fail to enable.\n", index);
 703                 return;
 704         }
 705
 706         bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
 707 }
 708
 709 /*
 710  * Early init I2C for prepare read the clk through I2C.
 711  */
 712 void i2c_early_init_f(void)
 713 {
 714         ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
 715         bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
 716                                         & I2C_QUIRK_FLAG ? true : false;
 717         int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 718
 719         /* Set I2C divider value */
 720         writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
 721         /* Reset module */
 722         writeb(I2CR_IDIS, base + (I2CR << reg_shift));
 723         writeb(0, base + (I2SR << reg_shift));
 724         /* Enable I2C */
 725         writeb(I2CR_IEN, base + (I2CR << reg_shift));
 726 }
 727
 728 /*
 729  * Init I2C Bus
 730  */
 731 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 732 {
 733         bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
 734 }
 735
 736 /*
 737  * Set I2C Speed
 738  */
 739 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 740 {
 741         return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
 742 }
 743
 744 /*
 745  * Register mxc i2c adapters
 746  */
 747 #ifdef CONFIG_SYS_I2C_MXC_I2C1
 748 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
 749                          mxc_i2c_read, mxc_i2c_write,
 750                          mxc_i2c_set_bus_speed,
 751                          CONFIG_SYS_MXC_I2C1_SPEED,
 752                          CONFIG_SYS_MXC_I2C1_SLAVE, 0)
 753 #endif
 754
 755 #ifdef CONFIG_SYS_I2C_MXC_I2C2
 756 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 757                          mxc_i2c_read, mxc_i2c_write,
 758                          mxc_i2c_set_bus_speed,
 759                          CONFIG_SYS_MXC_I2C2_SPEED,
 760                          CONFIG_SYS_MXC_I2C2_SLAVE, 1)
 761 #endif
 762
 763 #ifdef CONFIG_SYS_I2C_MXC_I2C3
 764 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
 765                          mxc_i2c_read, mxc_i2c_write,
 766                          mxc_i2c_set_bus_speed,
 767                          CONFIG_SYS_MXC_I2C3_SPEED,
 768                          CONFIG_SYS_MXC_I2C3_SLAVE, 2)
 769 #endif
 770
 771 #ifdef CONFIG_SYS_I2C_MXC_I2C4
 772 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
 773                          mxc_i2c_read, mxc_i2c_write,
 774                          mxc_i2c_set_bus_speed,
 775                          CONFIG_SYS_MXC_I2C4_SPEED,
 776                          CONFIG_SYS_MXC_I2C4_SLAVE, 3)
 777 #endif
 778
 779 #ifdef CONFIG_SYS_I2C_MXC_I2C5
 780 U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
 781                          mxc_i2c_read, mxc_i2c_write,
 782                          mxc_i2c_set_bus_speed,
 783                          CONFIG_SYS_MXC_I2C5_SPEED,
 784                          CONFIG_SYS_MXC_I2C5_SLAVE, 4)
 785 #endif
 786
 787 #ifdef CONFIG_SYS_I2C_MXC_I2C6
 788 U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
 789                          mxc_i2c_read, mxc_i2c_write,
 790                          mxc_i2c_set_bus_speed,
 791                          CONFIG_SYS_MXC_I2C6_SPEED,
 792                          CONFIG_SYS_MXC_I2C6_SLAVE, 5)
 793 #endif
 794
 795 #ifdef CONFIG_SYS_I2C_MXC_I2C7
 796 U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
 797                          mxc_i2c_read, mxc_i2c_write,
 798                          mxc_i2c_set_bus_speed,
 799                          CONFIG_SYS_MXC_I2C7_SPEED,
 800                          CONFIG_SYS_MXC_I2C7_SLAVE, 6)
 801 #endif
 802
 803 #ifdef CONFIG_SYS_I2C_MXC_I2C8
 804 U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
 805                          mxc_i2c_read, mxc_i2c_write,
 806                          mxc_i2c_set_bus_speed,
 807                          CONFIG_SYS_MXC_I2C8_SPEED,
 808                          CONFIG_SYS_MXC_I2C8_SLAVE, 7)
 809 #endif
 810
 811 #else
 812
 813 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 814 {
 815         struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 816
 817         return bus_i2c_set_bus_speed(i2c_bus, speed);
 818 }
 819
 820 static int mxc_i2c_probe(struct udevice *bus)
 821 {
 822         struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 823         const void *fdt = gd->fdt_blob;
 824         int node = dev_of_offset(bus);
 825         fdt_addr_t addr;
 826         int ret, ret2;
 827
 828         i2c_bus->driver_data = dev_get_driver_data(bus);
 829
 830         addr = devfdt_get_addr(bus);
 831         if (addr == FDT_ADDR_T_NONE)
 832                 return -EINVAL;
 833
 834         i2c_bus->base = addr;
 835         i2c_bus->index = bus->seq;
 836         i2c_bus->bus = bus;
 837
 838         /* Enable clk */
 839         ret = enable_i2c_clk(1, bus->seq);
 840         if (ret < 0)
 841                 return ret;
 842
 843         /*
 844          * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
 845          * Use gpio to force bus idle when necessary.
 846          */
 847         ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
 848         if (ret < 0) {
 849                 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
 850         } else {
 851                 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
 852                                 "scl-gpios", 0, &i2c_bus->scl_gpio,
 853                                 GPIOD_IS_OUT);
 854                 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
 855                                 "sda-gpios", 0, &i2c_bus->sda_gpio,
 856                                 GPIOD_IS_OUT);
 857                 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
 858                     !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
 859                     ret || ret2) {
 860                         dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
 861                         return -EINVAL;
 862                 }
 863         }
 864
 865         ret = i2c_idle_bus(i2c_bus);
 866         if (ret < 0) {
 867                 /* Disable clk */
 868                 enable_i2c_clk(0, bus->seq);
 869                 return ret;
 870         }
 871
 872         /*
 873          * Pinmux settings are in board file now, until pinmux is supported,
 874          * we can set pinmux here in probe function.
 875          */
 876
 877         debug("i2c : controller bus %d at %lu , speed %d: ",
 878               bus->seq, i2c_bus->base,
 879               i2c_bus->speed);
 880
 881         return 0;
 882 }
 883
 884 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 885                               u32 chip_flags)
 886 {
 887         int ret;
 888         struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 889
 890         ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
 891         if (ret < 0) {
 892                 debug("%s failed, ret = %d\n", __func__, ret);
 893                 return ret;
 894         }
 895
 896         i2c_imx_stop(i2c_bus);
 897
 898         return 0;
 899 }
 900
 901 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 902 {
 903         struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 904         int ret = 0;
 905         ulong base = i2c_bus->base;
 906         int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 907                 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 908
 909         /*
 910          * Here the 3rd parameter addr and the 4th one alen are set to 0,
 911          * because here we only want to send out chip address. The register
 912          * address is wrapped in msg.
 913          */
 914         ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
 915         if (ret < 0) {
 916                 debug("i2c_init_transfer error: %d\n", ret);
 917                 return ret;
 918         }
 919
 920         for (; nmsgs > 0; nmsgs--, msg++) {
 921                 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
 922                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 923                 if (msg->flags & I2C_M_RD)
 924                         ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
 925                                             msg->len);
 926                 else {
 927                         ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
 928                                              msg->len);
 929                         if (ret)
 930                                 break;
 931                         if (next_is_read) {
 932                                 /* Reuse ret */
 933                                 ret = readb(base + (I2CR << reg_shift));
 934                                 ret |= I2CR_RSTA;
 935                                 writeb(ret, base + (I2CR << reg_shift));
 936
 937                                 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
 938                                 if (ret < 0) {
 939                                         i2c_imx_stop(i2c_bus);
 940                                         break;
 941                                 }
 942                         }
 943                 }
 944         }
 945
 946         if (ret)
 947                 debug("i2c_write: error sending\n");
 948
 949         i2c_imx_stop(i2c_bus);
 950
 951         return ret;
 952 }
 953
 954 static const struct dm_i2c_ops mxc_i2c_ops = {
 955         .xfer           = mxc_i2c_xfer,
 956         .probe_chip     = mxc_i2c_probe_chip,
 957         .set_bus_speed  = mxc_i2c_set_bus_speed,
 958 };
 959
 960 static const struct udevice_id mxc_i2c_ids[] = {
 961         { .compatible = "fsl,imx21-i2c", },
 962         { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
 963         {}
 964 };
 965
 966 U_BOOT_DRIVER(i2c_mxc) = {
 967         .name = "i2c_mxc",
 968         .id = UCLASS_I2C,
 969         .of_match = mxc_i2c_ids,
 970         .probe = mxc_i2c_probe,
 971         .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
 972         .ops = &mxc_i2c_ops,
 973 };
 974 #endif