2 * Driver for the TWSI (i2c) controller found on the Marvell
3 * orion5x and kirkwood SoC families.
5 * Author: Albert Aribaud <albert.u.boot@aribaud.net>
6 * Copyright (c) 2010 Albert Aribaud.
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
17 * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
21 #if defined(CONFIG_ORION5X)
22 #include <asm/arch/orion5x.h>
23 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
24 #include <asm/arch/soc.h>
25 #elif defined(CONFIG_SUNXI)
26 #include <asm/arch/i2c.h>
28 #error Driver mvtwsi not supported by SoC or board
32 * TWSI register structure
37 struct mvtwsi_registers {
49 struct mvtwsi_registers {
54 u32 status; /* When reading */
55 u32 baudrate; /* When writing */
65 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
68 enum mvtwsi_ctrl_register_fields {
70 MVTWSI_CONTROL_ACK = 0x00000004,
72 MVTWSI_CONTROL_IFLG = 0x00000008,
74 MVTWSI_CONTROL_STOP = 0x00000010,
76 MVTWSI_CONTROL_START = 0x00000020,
78 MVTWSI_CONTROL_TWSIEN = 0x00000040,
79 /* Interrupt enable */
80 MVTWSI_CONTROL_INTEN = 0x00000080,
84 * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
85 * on other platforms, it is a normal r/w bit, which is cleared by writing 0.
88 #ifdef CONFIG_SUNXI_GEN_SUN6I
89 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
91 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
95 * enum mvstwsi_status_values - Possible values of I2C controller's status
98 * Only those statuses expected in normal master operation on
99 * non-10-bit-address devices are specified.
101 * Every status that's unexpected during normal operation (bus errors,
102 * arbitration losses, missing ACKs...) is passed back to the caller as an error
105 enum mvstwsi_status_values {
106 /* START condition transmitted */
107 MVTWSI_STATUS_START = 0x08,
108 /* Repeated START condition transmitted */
109 MVTWSI_STATUS_REPEATED_START = 0x10,
110 /* Address + write bit transmitted, ACK received */
111 MVTWSI_STATUS_ADDR_W_ACK = 0x18,
112 /* Data transmitted, ACK received */
113 MVTWSI_STATUS_DATA_W_ACK = 0x28,
114 /* Address + read bit transmitted, ACK received */
115 MVTWSI_STATUS_ADDR_R_ACK = 0x40,
116 /* Address + read bit transmitted, ACK not received */
117 MVTWSI_STATUS_ADDR_R_NAK = 0x48,
118 /* Data received, ACK transmitted */
119 MVTWSI_STATUS_DATA_R_ACK = 0x50,
120 /* Data received, ACK not transmitted */
121 MVTWSI_STATUS_DATA_R_NAK = 0x58,
122 /* No relevant status */
123 MVTWSI_STATUS_IDLE = 0xF8,
127 * enum mvstwsi_ack_flags - Determine whether a read byte should be
128 * acknowledged or not.
130 enum mvtwsi_ack_flags {
131 /* Send NAK after received byte */
133 /* Send ACK after received byte */
138 * MVTWSI controller base
141 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
143 switch (adap->hwadapnr) {
144 #ifdef CONFIG_I2C_MVTWSI_BASE0
146 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
148 #ifdef CONFIG_I2C_MVTWSI_BASE1
150 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
152 #ifdef CONFIG_I2C_MVTWSI_BASE2
154 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
156 #ifdef CONFIG_I2C_MVTWSI_BASE3
158 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
160 #ifdef CONFIG_I2C_MVTWSI_BASE4
162 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
164 #ifdef CONFIG_I2C_MVTWSI_BASE5
166 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
169 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
177 * enum mvtwsi_error_class - types of I2C errors
179 enum mvtwsi_error_class {
180 /* The controller returned a different status than expected */
181 MVTWSI_ERROR_WRONG_STATUS = 0x01,
182 /* The controller timed out */
183 MVTWSI_ERROR_TIMEOUT = 0x02,
187 * mvtwsi_error() - Build I2C return code from error information
189 * For debugging purposes, this function packs some information of an occurred
190 * error into a return code. These error codes are returned from I2C API
191 * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
193 * @ec: The error class of the error (enum mvtwsi_error_class).
194 * @lc: The last value of the control register.
195 * @ls: The last value of the status register.
196 * @es: The expected value of the status register.
197 * @return The generated error code.
199 inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
201 return ((ec << 24) & 0xFF000000)
202 | ((lc << 16) & 0x00FF0000)
203 | ((ls << 8) & 0x0000FF00)
208 * Wait for IFLG to raise, or return 'timeout.' Then, if the status is as
209 * expected, return 0 (ok) or 'wrong status' otherwise.
211 static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status)
217 control = readl(&twsi->control);
218 if (control & MVTWSI_CONTROL_IFLG) {
219 status = readl(&twsi->status);
220 if (status == expected_status)
224 MVTWSI_ERROR_WRONG_STATUS,
225 control, status, expected_status);
227 udelay(10); /* One clock cycle at 100 kHz */
229 status = readl(&twsi->status);
230 return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
235 * Assert the START condition, either in a single I2C transaction
236 * or inside back-to-back ones (repeated starts).
238 static int twsi_start(struct mvtwsi_registers *twsi, int expected_status)
241 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
242 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
243 /* Wait for controller to process START */
244 return twsi_wait(twsi, expected_status);
248 * Send a byte (i2c address or data).
250 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
253 /* Write byte to data register for sending */
254 writel(byte, &twsi->data);
255 /* Clear any pending interrupt -- that will cause sending */
256 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
258 /* Wait for controller to receive byte, and check ACK */
259 return twsi_wait(twsi, expected_status);
265 static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag)
267 int expected_status, status, control;
269 /* Compute expected status based on passed ACK flag */
270 expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
271 MVTWSI_STATUS_DATA_R_NAK;
272 /* Acknowledge *previous state*, and launch receive */
273 control = MVTWSI_CONTROL_TWSIEN;
274 control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
275 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
276 /* Wait for controller to receive byte, and assert ACK or NAK */
277 status = twsi_wait(twsi, expected_status);
278 /* If we did receive the expected byte, store it */
280 *byte = readl(&twsi->data);
285 * Assert the STOP condition.
286 * This is also used to force the bus back to idle (SDA = SCL = 1).
288 static int twsi_stop(struct mvtwsi_registers *twsi)
290 int control, stop_status;
295 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
296 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
297 /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
299 stop_status = readl(&twsi->status);
300 if (stop_status == MVTWSI_STATUS_IDLE)
302 udelay(10); /* One clock cycle at 100 kHz */
304 control = readl(&twsi->control);
305 if (stop_status != MVTWSI_STATUS_IDLE)
306 status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
307 control, status, MVTWSI_STATUS_IDLE);
311 static uint twsi_calc_freq(const int n, const int m)
314 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
316 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
322 * Controller reset also resets the baud rate and slave address, so
323 * they must be re-established afterwards.
325 static void twsi_reset(struct mvtwsi_registers *twsi)
327 /* Reset controller */
328 writel(0, &twsi->soft_reset);
329 /* Wait 2 ms -- this is what the Marvell LSP does */
334 * Sets baud to the highest possible value not exceeding the requested one.
336 static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
337 uint requested_speed)
339 uint tmp_speed, highest_speed, n, m;
340 uint baud = 0x44; /* Baud rate after controller reset */
343 /* Successively try m, n combinations, and use the combination
344 * resulting in the largest speed that's not above the requested
346 for (n = 0; n < 8; n++) {
347 for (m = 0; m < 16; m++) {
348 tmp_speed = twsi_calc_freq(n, m);
349 if ((tmp_speed <= requested_speed) &&
350 (tmp_speed > highest_speed)) {
351 highest_speed = tmp_speed;
356 writel(baud, &twsi->baudrate);
360 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
363 /* Reset controller */
366 __twsi_i2c_set_bus_speed(twsi, speed);
367 /* Set slave address; even though we don't use it */
368 writel(slaveadd, &twsi->slave_address);
369 writel(0, &twsi->xtnd_slave_addr);
370 /* Assert STOP, but don't care for the result */
371 (void) twsi_stop(twsi);
375 * Begin I2C transaction with expected start status, at given address.
376 * Expected address status will derive from direction bit (bit 0) in addr.
378 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
381 int status, expected_addr_status;
383 /* Compute the expected address status from the direction bit in
384 * the address byte */
385 if (addr & 1) /* Reading */
386 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
388 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
390 status = twsi_start(twsi, expected_start_status);
391 /* Send out the address if the start went well */
393 status = twsi_send(twsi, addr, expected_addr_status);
394 /* Return 0, or the status of the first failure */
399 * Begin read, nak data byte, end.
401 static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip)
407 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1);
408 /* Dummy read was accepted: receive byte, but NAK it. */
410 status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK);
411 /* Stop transaction */
413 /* Return 0, or the status of the first failure */
418 * Begin write, send address byte(s), begin read, receive data bytes, end.
420 * NOTE: Some devices want a stop right before the second start, while some
421 * will choke if it is there. Since deciding this is not yet supported in
422 * higher level APIs, we need to make a decision here, and for the moment that
423 * will be a repeated start without a preceding stop.
425 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
426 u8 *addr, int alen, uchar *data, int length)
431 /* Begin i2c write to send the address bytes */
432 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1));
433 /* Send address bytes */
434 while ((status == 0) && alen--)
435 status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK);
436 /* Begin i2c read to receive data bytes */
438 status = i2c_begin(twsi, MVTWSI_STATUS_REPEATED_START,
440 /* Receive actual data bytes; set NAK if we if we have nothing more to
442 while ((status == 0) && length--)
443 status = twsi_recv(twsi, data++,
445 MVTWSI_READ_ACK : MVTWSI_READ_NAK);
446 /* Stop transaction */
447 stop_status = twsi_stop(twsi);
448 /* Return 0, or the status of the first failure */
449 return status != 0 ? status : stop_status;
453 * Begin write, send address byte(s), send data bytes, end.
455 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
456 u8 *addr, int alen, uchar *data, int length)
458 int status, stop_status;
460 /* Begin i2c write to send first the address bytes, then the
462 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1));
463 /* Send address bytes */
464 while ((status == 0) && (alen-- > 0))
465 status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK);
466 /* Send data bytes */
467 while ((status == 0) && (length-- > 0))
468 status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK);
469 /* Stop transaction */
470 stop_status = twsi_stop(twsi);
471 /* Return 0, or the status of the first failure */
472 return status != 0 ? status : stop_status;
475 static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
478 struct mvtwsi_registers *twsi = twsi_get_base(adap);
479 __twsi_i2c_init(twsi, speed, slaveadd);
482 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
483 uint requested_speed)
485 struct mvtwsi_registers *twsi = twsi_get_base(adap);
486 return __twsi_i2c_set_bus_speed(twsi, requested_speed);
489 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
491 struct mvtwsi_registers *twsi = twsi_get_base(adap);
492 return __twsi_i2c_probe_chip(twsi, chip);
495 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
496 int alen, uchar *data, int length)
498 struct mvtwsi_registers *twsi = twsi_get_base(adap);
501 addr_bytes[0] = (addr >> 0) & 0xFF;
502 addr_bytes[1] = (addr >> 8) & 0xFF;
503 addr_bytes[2] = (addr >> 16) & 0xFF;
504 addr_bytes[3] = (addr >> 24) & 0xFF;
506 return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length);
509 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
510 int alen, uchar *data, int length)
512 struct mvtwsi_registers *twsi = twsi_get_base(adap);
515 addr_bytes[0] = (addr >> 0) & 0xFF;
516 addr_bytes[1] = (addr >> 8) & 0xFF;
517 addr_bytes[2] = (addr >> 16) & 0xFF;
518 addr_bytes[3] = (addr >> 24) & 0xFF;
520 return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length);
523 #ifdef CONFIG_I2C_MVTWSI_BASE0
524 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
525 twsi_i2c_read, twsi_i2c_write,
526 twsi_i2c_set_bus_speed,
527 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
529 #ifdef CONFIG_I2C_MVTWSI_BASE1
530 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
531 twsi_i2c_read, twsi_i2c_write,
532 twsi_i2c_set_bus_speed,
533 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
536 #ifdef CONFIG_I2C_MVTWSI_BASE2
537 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
538 twsi_i2c_read, twsi_i2c_write,
539 twsi_i2c_set_bus_speed,
540 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
543 #ifdef CONFIG_I2C_MVTWSI_BASE3
544 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
545 twsi_i2c_read, twsi_i2c_write,
546 twsi_i2c_set_bus_speed,
547 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
550 #ifdef CONFIG_I2C_MVTWSI_BASE4
551 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
552 twsi_i2c_read, twsi_i2c_write,
553 twsi_i2c_set_bus_speed,
554 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
557 #ifdef CONFIG_I2C_MVTWSI_BASE5
558 U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
559 twsi_i2c_read, twsi_i2c_write,
560 twsi_i2c_set_bus_speed,
561 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)