2 * Driver for the TWSI (i2c) controller found on the Marvell
3 * orion5x and kirkwood SoC families.
5 * Author: Albert Aribaud <albert.u.boot@aribaud.net>
6 * Copyright (c) 2010 Albert Aribaud.
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
15 #include <linux/compat.h>
20 DECLARE_GLOBAL_DATA_PTR;
23 * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
28 #if defined(CONFIG_ORION5X)
29 #include <asm/arch/orion5x.h>
30 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
31 #include <asm/arch/soc.h>
32 #elif defined(CONFIG_SUNXI)
33 #include <asm/arch/i2c.h>
35 #error Driver mvtwsi not supported by SoC or board
37 #endif /* CONFIG_DM_I2C */
40 * TWSI register structure
45 struct mvtwsi_registers {
57 struct mvtwsi_registers {
62 u32 status; /* When reading */
63 u32 baudrate; /* When writing */
73 struct mvtwsi_i2c_dev {
74 /* TWSI Register base for the device */
75 struct mvtwsi_registers *base;
76 /* Number of the device (determined from cell-index property) */
78 /* The I2C slave address for the device */
80 /* The configured I2C speed in Hz */
82 /* The current length of a clock period (depending on speed) */
85 #endif /* CONFIG_DM_I2C */
88 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
91 enum mvtwsi_ctrl_register_fields {
93 MVTWSI_CONTROL_ACK = 0x00000004,
95 MVTWSI_CONTROL_IFLG = 0x00000008,
97 MVTWSI_CONTROL_STOP = 0x00000010,
99 MVTWSI_CONTROL_START = 0x00000020,
101 MVTWSI_CONTROL_TWSIEN = 0x00000040,
102 /* Interrupt enable */
103 MVTWSI_CONTROL_INTEN = 0x00000080,
107 * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
108 * on other platforms, it is a normal r/w bit, which is cleared by writing 0.
111 #ifdef CONFIG_SUNXI_GEN_SUN6I
112 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
114 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
118 * enum mvstwsi_status_values - Possible values of I2C controller's status
121 * Only those statuses expected in normal master operation on
122 * non-10-bit-address devices are specified.
124 * Every status that's unexpected during normal operation (bus errors,
125 * arbitration losses, missing ACKs...) is passed back to the caller as an error
128 enum mvstwsi_status_values {
129 /* START condition transmitted */
130 MVTWSI_STATUS_START = 0x08,
131 /* Repeated START condition transmitted */
132 MVTWSI_STATUS_REPEATED_START = 0x10,
133 /* Address + write bit transmitted, ACK received */
134 MVTWSI_STATUS_ADDR_W_ACK = 0x18,
135 /* Data transmitted, ACK received */
136 MVTWSI_STATUS_DATA_W_ACK = 0x28,
137 /* Address + read bit transmitted, ACK received */
138 MVTWSI_STATUS_ADDR_R_ACK = 0x40,
139 /* Address + read bit transmitted, ACK not received */
140 MVTWSI_STATUS_ADDR_R_NAK = 0x48,
141 /* Data received, ACK transmitted */
142 MVTWSI_STATUS_DATA_R_ACK = 0x50,
143 /* Data received, ACK not transmitted */
144 MVTWSI_STATUS_DATA_R_NAK = 0x58,
145 /* No relevant status */
146 MVTWSI_STATUS_IDLE = 0xF8,
150 * enum mvstwsi_ack_flags - Determine whether a read byte should be
151 * acknowledged or not.
153 enum mvtwsi_ack_flags {
154 /* Send NAK after received byte */
156 /* Send ACK after received byte */
160 inline uint calc_tick(uint speed)
162 /* One tick = the duration of a period at the specified speed in ns (we
163 * add 100 ns to be on the safe side) */
164 return (1000000000u / speed) + 100;
167 #ifndef CONFIG_DM_I2C
170 * MVTWSI controller base
173 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
175 switch (adap->hwadapnr) {
176 #ifdef CONFIG_I2C_MVTWSI_BASE0
178 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
180 #ifdef CONFIG_I2C_MVTWSI_BASE1
182 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
184 #ifdef CONFIG_I2C_MVTWSI_BASE2
186 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
188 #ifdef CONFIG_I2C_MVTWSI_BASE3
190 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
192 #ifdef CONFIG_I2C_MVTWSI_BASE4
194 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
196 #ifdef CONFIG_I2C_MVTWSI_BASE5
198 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
201 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
210 * enum mvtwsi_error_class - types of I2C errors
212 enum mvtwsi_error_class {
213 /* The controller returned a different status than expected */
214 MVTWSI_ERROR_WRONG_STATUS = 0x01,
215 /* The controller timed out */
216 MVTWSI_ERROR_TIMEOUT = 0x02,
220 * mvtwsi_error() - Build I2C return code from error information
222 * For debugging purposes, this function packs some information of an occurred
223 * error into a return code. These error codes are returned from I2C API
224 * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
226 * @ec: The error class of the error (enum mvtwsi_error_class).
227 * @lc: The last value of the control register.
228 * @ls: The last value of the status register.
229 * @es: The expected value of the status register.
230 * @return The generated error code.
232 inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
234 return ((ec << 24) & 0xFF000000)
235 | ((lc << 16) & 0x00FF0000)
236 | ((ls << 8) & 0x0000FF00)
241 * Wait for IFLG to raise, or return 'timeout.' Then, if the status is as
242 * expected, return 0 (ok) or 'wrong status' otherwise.
244 static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
251 control = readl(&twsi->control);
252 if (control & MVTWSI_CONTROL_IFLG) {
253 status = readl(&twsi->status);
254 if (status == expected_status)
258 MVTWSI_ERROR_WRONG_STATUS,
259 control, status, expected_status);
261 ndelay(tick); /* One clock cycle */
263 status = readl(&twsi->status);
264 return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
269 * Assert the START condition, either in a single I2C transaction
270 * or inside back-to-back ones (repeated starts).
272 static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
276 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
277 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
278 /* Wait for controller to process START */
279 return twsi_wait(twsi, expected_status, tick);
283 * Send a byte (i2c address or data).
285 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
286 int expected_status, uint tick)
288 /* Write byte to data register for sending */
289 writel(byte, &twsi->data);
290 /* Clear any pending interrupt -- that will cause sending */
291 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
293 /* Wait for controller to receive byte, and check ACK */
294 return twsi_wait(twsi, expected_status, tick);
300 static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
303 int expected_status, status, control;
305 /* Compute expected status based on passed ACK flag */
306 expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
307 MVTWSI_STATUS_DATA_R_NAK;
308 /* Acknowledge *previous state*, and launch receive */
309 control = MVTWSI_CONTROL_TWSIEN;
310 control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
311 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
312 /* Wait for controller to receive byte, and assert ACK or NAK */
313 status = twsi_wait(twsi, expected_status, tick);
314 /* If we did receive the expected byte, store it */
316 *byte = readl(&twsi->data);
321 * Assert the STOP condition.
322 * This is also used to force the bus back to idle (SDA = SCL = 1).
324 static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
326 int control, stop_status;
331 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
332 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
333 /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
335 stop_status = readl(&twsi->status);
336 if (stop_status == MVTWSI_STATUS_IDLE)
338 ndelay(tick); /* One clock cycle */
340 control = readl(&twsi->control);
341 if (stop_status != MVTWSI_STATUS_IDLE)
342 status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
343 control, status, MVTWSI_STATUS_IDLE);
347 static uint twsi_calc_freq(const int n, const int m)
350 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
352 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
358 * Controller reset also resets the baud rate and slave address, so
359 * they must be re-established afterwards.
361 static void twsi_reset(struct mvtwsi_registers *twsi)
363 /* Reset controller */
364 writel(0, &twsi->soft_reset);
365 /* Wait 2 ms -- this is what the Marvell LSP does */
370 * Sets baud to the highest possible value not exceeding the requested one.
372 static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
373 uint requested_speed)
375 uint tmp_speed, highest_speed, n, m;
376 uint baud = 0x44; /* Baud rate after controller reset */
379 /* Successively try m, n combinations, and use the combination
380 * resulting in the largest speed that's not above the requested
382 for (n = 0; n < 8; n++) {
383 for (m = 0; m < 16; m++) {
384 tmp_speed = twsi_calc_freq(n, m);
385 if ((tmp_speed <= requested_speed) &&
386 (tmp_speed > highest_speed)) {
387 highest_speed = tmp_speed;
392 writel(baud, &twsi->baudrate);
394 /* Wait for controller for one tick */
396 ndelay(calc_tick(highest_speed));
400 return highest_speed;
403 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
404 int slaveadd, uint *actual_speed)
406 /* Reset controller */
409 *actual_speed = __twsi_i2c_set_bus_speed(twsi, speed);
410 /* Set slave address; even though we don't use it */
411 writel(slaveadd, &twsi->slave_address);
412 writel(0, &twsi->xtnd_slave_addr);
413 /* Assert STOP, but don't care for the result */
415 (void) twsi_stop(twsi, calc_tick(*actual_speed));
417 (void) twsi_stop(twsi, 10000);
422 * Begin I2C transaction with expected start status, at given address.
423 * Expected address status will derive from direction bit (bit 0) in addr.
425 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
428 int status, expected_addr_status;
430 /* Compute the expected address status from the direction bit in
431 * the address byte */
432 if (addr & 1) /* Reading */
433 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
435 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
437 status = twsi_start(twsi, expected_start_status, tick);
438 /* Send out the address if the start went well */
440 status = twsi_send(twsi, addr, expected_addr_status, tick);
441 /* Return 0, or the status of the first failure */
446 * Begin read, nak data byte, end.
448 static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
455 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick);
456 /* Dummy read was accepted: receive byte, but NAK it. */
458 status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick);
459 /* Stop transaction */
460 twsi_stop(twsi, tick);
461 /* Return 0, or the status of the first failure */
466 * Begin write, send address byte(s), begin read, receive data bytes, end.
468 * NOTE: Some devices want a stop right before the second start, while some
469 * will choke if it is there. Since deciding this is not yet supported in
470 * higher level APIs, we need to make a decision here, and for the moment that
471 * will be a repeated start without a preceding stop.
473 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
474 u8 *addr, int alen, uchar *data, int length,
479 int expected_start = MVTWSI_STATUS_START;
482 /* Begin i2c write to send the address bytes */
483 status = i2c_begin(twsi, expected_start, (chip << 1), tick);
484 /* Send address bytes */
485 while ((status == 0) && alen--)
486 status = twsi_send(twsi, *(addr++),
487 MVTWSI_STATUS_DATA_W_ACK, tick);
488 /* Send repeated STARTs after the initial START */
489 expected_start = MVTWSI_STATUS_REPEATED_START;
491 /* Begin i2c read to receive data bytes */
493 status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick);
494 /* Receive actual data bytes; set NAK if we if we have nothing more to
496 while ((status == 0) && length--)
497 status = twsi_recv(twsi, data++,
499 MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick);
500 /* Stop transaction */
501 stop_status = twsi_stop(twsi, tick);
502 /* Return 0, or the status of the first failure */
503 return status != 0 ? status : stop_status;
507 * Begin write, send address byte(s), send data bytes, end.
509 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
510 u8 *addr, int alen, uchar *data, int length,
513 int status, stop_status;
515 /* Begin i2c write to send first the address bytes, then the
517 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
518 /* Send address bytes */
519 while ((status == 0) && (alen-- > 0))
520 status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK,
522 /* Send data bytes */
523 while ((status == 0) && (length-- > 0))
524 status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK,
526 /* Stop transaction */
527 stop_status = twsi_stop(twsi, tick);
528 /* Return 0, or the status of the first failure */
529 return status != 0 ? status : stop_status;
532 #ifndef CONFIG_DM_I2C
533 static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
536 struct mvtwsi_registers *twsi = twsi_get_base(adap);
537 __twsi_i2c_init(twsi, speed, slaveadd, NULL);
540 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
541 uint requested_speed)
543 struct mvtwsi_registers *twsi = twsi_get_base(adap);
544 __twsi_i2c_set_bus_speed(twsi, requested_speed);
548 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
550 struct mvtwsi_registers *twsi = twsi_get_base(adap);
551 return __twsi_i2c_probe_chip(twsi, chip, 10000);
554 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
555 int alen, uchar *data, int length)
557 struct mvtwsi_registers *twsi = twsi_get_base(adap);
560 addr_bytes[0] = (addr >> 0) & 0xFF;
561 addr_bytes[1] = (addr >> 8) & 0xFF;
562 addr_bytes[2] = (addr >> 16) & 0xFF;
563 addr_bytes[3] = (addr >> 24) & 0xFF;
565 return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length,
569 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
570 int alen, uchar *data, int length)
572 struct mvtwsi_registers *twsi = twsi_get_base(adap);
575 addr_bytes[0] = (addr >> 0) & 0xFF;
576 addr_bytes[1] = (addr >> 8) & 0xFF;
577 addr_bytes[2] = (addr >> 16) & 0xFF;
578 addr_bytes[3] = (addr >> 24) & 0xFF;
580 return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length,
584 #ifdef CONFIG_I2C_MVTWSI_BASE0
585 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
586 twsi_i2c_read, twsi_i2c_write,
587 twsi_i2c_set_bus_speed,
588 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
590 #ifdef CONFIG_I2C_MVTWSI_BASE1
591 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
592 twsi_i2c_read, twsi_i2c_write,
593 twsi_i2c_set_bus_speed,
594 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
597 #ifdef CONFIG_I2C_MVTWSI_BASE2
598 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
599 twsi_i2c_read, twsi_i2c_write,
600 twsi_i2c_set_bus_speed,
601 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
604 #ifdef CONFIG_I2C_MVTWSI_BASE3
605 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
606 twsi_i2c_read, twsi_i2c_write,
607 twsi_i2c_set_bus_speed,
608 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
611 #ifdef CONFIG_I2C_MVTWSI_BASE4
612 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
613 twsi_i2c_read, twsi_i2c_write,
614 twsi_i2c_set_bus_speed,
615 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
618 #ifdef CONFIG_I2C_MVTWSI_BASE5
619 U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
620 twsi_i2c_read, twsi_i2c_write,
621 twsi_i2c_set_bus_speed,
622 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
625 #else /* CONFIG_DM_I2C */
627 static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
630 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
631 return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick);
634 static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed)
636 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
638 dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed);
639 dev->tick = calc_tick(dev->speed);
644 static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus)
646 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
648 dev->base = dev_get_addr_ptr(bus);
653 dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
655 dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
656 "u-boot,i2c-slave-addr", 0x0);
657 dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
658 "clock-frequency", 100000);
662 static int mvtwsi_i2c_probe(struct udevice *bus)
664 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
667 __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed);
668 dev->speed = actual_speed;
669 dev->tick = calc_tick(dev->speed);
673 static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
675 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
676 struct i2c_msg *dmsg, *omsg, dummy;
678 memset(&dummy, 0, sizeof(struct i2c_msg));
680 /* We expect either two messages (one with an offset and one with the
681 * actual data) or one message (just data or offset/data combined) */
682 if (nmsgs > 2 || nmsgs == 0) {
683 debug("%s: Only one or two messages are supported.", __func__);
687 omsg = nmsgs == 1 ? &dummy : msg;
688 dmsg = nmsgs == 1 ? msg : msg + 1;
690 if (dmsg->flags & I2C_M_RD)
691 return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
692 omsg->len, dmsg->buf, dmsg->len,
695 return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
696 omsg->len, dmsg->buf, dmsg->len,
700 static const struct dm_i2c_ops mvtwsi_i2c_ops = {
701 .xfer = mvtwsi_i2c_xfer,
702 .probe_chip = mvtwsi_i2c_probe_chip,
703 .set_bus_speed = mvtwsi_i2c_set_bus_speed,
706 static const struct udevice_id mvtwsi_i2c_ids[] = {
707 { .compatible = "marvell,mv64xxx-i2c", },
711 U_BOOT_DRIVER(i2c_mvtwsi) = {
712 .name = "i2c_mvtwsi",
714 .of_match = mvtwsi_i2c_ids,
715 .probe = mvtwsi_i2c_probe,
716 .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata,
717 .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev),
718 .ops = &mvtwsi_i2c_ops,
720 #endif /* CONFIG_DM_I2C */