drivers/i2c/lpc32xx_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * LPC32xx I2C interface driver
   4  *
   5  * (C) Copyright 2014-2015  DENX Software Engineering GmbH
   6  * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
   7  */
   8
   9 #include <common.h>
  10 #include <log.h>
  11 #include <asm/io.h>
  12 #include <i2c.h>
  13 #include <linux/errno.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/i2c.h>
  16 #include <dm.h>
  17 #include <mapmem.h>
  18
  19 /*
  20  * Provide default speed and slave if target did not
  21  */
  22
  23 #if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
  24 #define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
  25 #endif
  26
  27 #if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
  28 #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
  29 #endif
  30
  31 /* TX register fields */
  32 #define LPC32XX_I2C_TX_START            0x00000100
  33 #define LPC32XX_I2C_TX_STOP             0x00000200
  34
  35 /* Control register values */
  36 #define LPC32XX_I2C_SOFT_RESET          0x00000100
  37
  38 /* Status register values */
  39 #define LPC32XX_I2C_STAT_TFF            0x00000400
  40 #define LPC32XX_I2C_STAT_RFE            0x00000200
  41 #define LPC32XX_I2C_STAT_DRMI           0x00000008
  42 #define LPC32XX_I2C_STAT_NAI            0x00000004
  43 #define LPC32XX_I2C_STAT_TDI            0x00000001
  44
  45 #if !CONFIG_IS_ENABLED(DM_I2C)
  46 static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
  47         (struct lpc32xx_i2c_base *)I2C1_BASE,
  48         (struct lpc32xx_i2c_base *)I2C2_BASE,
  49         (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
  50 };
  51 #endif
  52
  53 /* Set I2C bus speed */
  54 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
  55                                         unsigned int speed, unsigned int chip)
  56 {
  57         int half_period;
  58
  59         if (speed == 0)
  60                 return -EINVAL;
  61
  62         /* OTG I2C clock source and CLK registers are different */
  63         if (chip == 2) {
  64                 half_period = (get_periph_clk_rate() / speed) / 2;
  65                 if (half_period > 0xFF)
  66                         return -EINVAL;
  67         } else {
  68                 half_period = (get_hclk_clk_rate() / speed) / 2;
  69                 if (half_period > 0x3FF)
  70                         return -EINVAL;
  71         }
  72
  73         writel(half_period, &base->clk_hi);
  74         writel(half_period, &base->clk_lo);
  75         return 0;
  76 }
  77
  78 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
  79 static void __i2c_init(struct lpc32xx_i2c_base *base,
  80                        int requested_speed, int slaveadd, unsigned int chip)
  81 {
  82         /* soft reset (auto-clears) */
  83         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
  84         /* set HI and LO periods for half of the default speed */
  85         __i2c_set_bus_speed(base, requested_speed, chip);
  86 }
  87
  88 /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
  89 static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
  90 {
  91         int stat;
  92
  93         /* Soft-reset the controller */
  94         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
  95         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
  96                 ;
  97         /* Addre slave for write with start before and stop after */
  98         writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
  99                &base->tx);
 100         /* wait for end of transation */
 101         while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 102                 ;
 103         /* was there no acknowledge? */
 104         return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
 105 }
 106
 107 /*
 108  * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 109  * Begin write, send address byte(s), begin read, receive data bytes, end.
 110  */
 111 static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
 112                       int alen, u8 *data, int length)
 113 {
 114         int stat, wlen;
 115
 116         /* Soft-reset the controller */
 117         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 118         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 119                 ;
 120         /* do we need to write an address at all? */
 121         if (alen) {
 122                 /* Address slave in write mode */
 123                 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 124                 /* write address bytes */
 125                 while (alen--) {
 126                         /* compute address byte + stop for the last one */
 127                         int a = (addr >> (8 * alen)) & 0xff;
 128                         if (!alen)
 129                                 a |= LPC32XX_I2C_TX_STOP;
 130                         /* Send address byte */
 131                         writel(a, &base->tx);
 132                 }
 133                 /* wait for end of transation */
 134                 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 135                         ;
 136                 /* clear end-of-transaction flag */
 137                 writel(1, &base->stat);
 138         }
 139         /* do we have to read data at all? */
 140         if (length) {
 141                 /* Address slave in read mode */
 142                 writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 143                 wlen = length;
 144                 /* get data */
 145                 while (length | wlen) {
 146                         /* read status for TFF and RFE */
 147                         stat = readl(&base->stat);
 148                         /* must we, can we write a trigger byte? */
 149                         if ((wlen > 0)
 150                            & (!(stat & LPC32XX_I2C_STAT_TFF))) {
 151                                 wlen--;
 152                                 /* write trigger byte + stop if last */
 153                                 writel(wlen ? 0 :
 154                                 LPC32XX_I2C_TX_STOP, &base->tx);
 155                         }
 156                         /* must we, can we read a data byte? */
 157                         if ((length > 0)
 158                            & (!(stat & LPC32XX_I2C_STAT_RFE))) {
 159                                 length--;
 160                                 /* read byte */
 161                                 *(data++) = readl(&base->rx);
 162                         }
 163                 }
 164                 /* wait for end of transation */
 165                 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 166                         ;
 167                 /* clear end-of-transaction flag */
 168                 writel(1, &base->stat);
 169         }
 170         /* success */
 171         return 0;
 172 }
 173
 174 /*
 175  * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 176  * Begin write, send address byte(s), send data bytes, end.
 177  */
 178 static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
 179                        int alen, u8 *data, int length)
 180 {
 181         int stat;
 182
 183         /* Soft-reset the controller */
 184         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 185         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 186                 ;
 187         /* do we need to write anything at all? */
 188         if (alen | length)
 189                 /* Address slave in write mode */
 190                 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 191         else
 192                 return 0;
 193         /* write address bytes */
 194         while (alen) {
 195                 /* wait for transmit fifo not full */
 196                 stat = readl(&base->stat);
 197                 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
 198                         alen--;
 199                         int a = (addr >> (8 * alen)) & 0xff;
 200                         if (!(alen | length))
 201                                 a |= LPC32XX_I2C_TX_STOP;
 202                         /* Send address byte */
 203                         writel(a, &base->tx);
 204                 }
 205         }
 206         while (length) {
 207                 /* wait for transmit fifo not full */
 208                 stat = readl(&base->stat);
 209                 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
 210                         /* compute data byte, add stop if length==0 */
 211                         length--;
 212                         int d = *(data++);
 213                         if (!length)
 214                                 d |= LPC32XX_I2C_TX_STOP;
 215                         /* Send data byte */
 216                         writel(d, &base->tx);
 217                 }
 218         }
 219         /* wait for end of transation */
 220         while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 221                 ;
 222         /* clear end-of-transaction flag */
 223         writel(1, &base->stat);
 224         return 0;
 225 }
 226
 227 #if !CONFIG_IS_ENABLED(DM_I2C)
 228 static void lpc32xx_i2c_init(struct i2c_adapter *adap,
 229                              int requested_speed, int slaveadd)
 230 {
 231         __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
 232                    adap->hwadapnr);
 233 }
 234
 235 static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
 236 {
 237         return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
 238 }
 239
 240 static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 241                             int alen, u8 *data, int length)
 242 {
 243         return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
 244                          alen, data, length);
 245 }
 246
 247 static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 248                              int alen, u8 *data, int length)
 249 {
 250         return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
 251                           alen, data, length);
 252 }
 253
 254 static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
 255                                               unsigned int speed)
 256 {
 257         return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
 258                                   adap->hwadapnr);
 259 }
 260
 261 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
 262                          lpc32xx_i2c_read, lpc32xx_i2c_write,
 263                          lpc32xx_i2c_set_bus_speed,
 264                          CONFIG_SYS_I2C_LPC32XX_SPEED,
 265                          CONFIG_SYS_I2C_LPC32XX_SLAVE,
 266                          0)
 267
 268 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
 269                          lpc32xx_i2c_read, lpc32xx_i2c_write,
 270                          lpc32xx_i2c_set_bus_speed,
 271                          CONFIG_SYS_I2C_LPC32XX_SPEED,
 272                          CONFIG_SYS_I2C_LPC32XX_SLAVE,
 273                          1)
 274
 275 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
 276                          lpc32xx_i2c_read, lpc32xx_i2c_write,
 277                          lpc32xx_i2c_set_bus_speed,
 278                          100000,
 279                          0,
 280                          2)
 281 #else /* CONFIG_DM_I2C */
 282 static int lpc32xx_i2c_probe(struct udevice *bus)
 283 {
 284         struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
 285
 286         /*
 287          * FIXME: This is not permitted
 288          *      dev_seq(bus) = dev->index;
 289          */
 290
 291         __i2c_init(dev->base, dev->speed, 0, dev->index);
 292         return 0;
 293 }
 294
 295 static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 296                                   u32 chip_flags)
 297 {
 298         struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
 299         return __i2c_probe_chip(dev->base, chip_addr);
 300 }
 301
 302 static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 303                 int nmsgs)
 304 {
 305         struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
 306         struct i2c_msg *dmsg, *omsg, dummy;
 307         uint i = 0, address = 0;
 308
 309         memset(&dummy, 0, sizeof(struct i2c_msg));
 310
 311         /* We expect either two messages (one with an offset and one with the
 312          * actual data) or one message (just data)
 313          */
 314         if (nmsgs > 2 || nmsgs == 0) {
 315                 debug("%s: Only one or two messages are supported.", __func__);
 316                 return -1;
 317         }
 318
 319         omsg = nmsgs == 1 ? &dummy : msg;
 320         dmsg = nmsgs == 1 ? msg : msg + 1;
 321
 322         /* the address is expected to be a uint, not a array. */
 323         address = omsg->buf[0];
 324         for (i = 1; i < omsg->len; i++)
 325                 address = (address << 8) + omsg->buf[i];
 326
 327         if (dmsg->flags & I2C_M_RD)
 328                 return __i2c_read(dev->base, dmsg->addr, address,
 329                                   omsg->len, dmsg->buf, dmsg->len);
 330         else
 331                 return __i2c_write(dev->base, dmsg->addr, address,
 332                                    omsg->len, dmsg->buf, dmsg->len);
 333 }
 334
 335 static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 336 {
 337         struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
 338         return __i2c_set_bus_speed(dev->base, speed, dev->index);
 339 }
 340
 341 static int lpc32xx_i2c_reset(struct udevice *bus)
 342 {
 343         struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
 344
 345         __i2c_init(dev->base, dev->speed, 0, dev->index);
 346         return 0;
 347 }
 348
 349 static const struct dm_i2c_ops lpc32xx_i2c_ops = {
 350         .xfer          = lpc32xx_i2c_xfer,
 351         .probe_chip    = lpc32xx_i2c_probe_chip,
 352         .deblock       = lpc32xx_i2c_reset,
 353         .set_bus_speed = lpc32xx_i2c_set_bus_speed,
 354 };
 355
 356 U_BOOT_DRIVER(i2c_lpc32xx) = {
 357         .id                   = UCLASS_I2C,
 358         .name                 = "i2c_lpc32xx",
 359         .probe                = lpc32xx_i2c_probe,
 360         .ops                  = &lpc32xx_i2c_ops,
 361 };
 362 #endif /* CONFIG_DM_I2C */