Merge branch '2021-07-06-platform-updates'
[platform/kernel/u-boot.git] / drivers / i2c / lpc32xx_i2c.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * LPC32xx I2C interface driver
4  *
5  * (C) Copyright 2014-2015  DENX Software Engineering GmbH
6  * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
7  */
8
9 #include <common.h>
10 #include <log.h>
11 #include <asm/io.h>
12 #include <i2c.h>
13 #include <linux/errno.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/i2c.h>
16 #include <dm.h>
17 #include <mapmem.h>
18
19 /*
20  * Provide default speed and slave if target did not
21  */
22
23 #if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
24 #define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
25 #endif
26
27 #if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
28 #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
29 #endif
30
31 /* TX register fields */
32 #define LPC32XX_I2C_TX_START            0x00000100
33 #define LPC32XX_I2C_TX_STOP             0x00000200
34
35 /* Control register values */
36 #define LPC32XX_I2C_SOFT_RESET          0x00000100
37
38 /* Status register values */
39 #define LPC32XX_I2C_STAT_TFF            0x00000400
40 #define LPC32XX_I2C_STAT_RFE            0x00000200
41 #define LPC32XX_I2C_STAT_NAI            0x00000004
42 #define LPC32XX_I2C_STAT_TDI            0x00000001
43
44 #if !CONFIG_IS_ENABLED(DM_I2C)
45 static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
46         (struct lpc32xx_i2c_base *)I2C1_BASE,
47         (struct lpc32xx_i2c_base *)I2C2_BASE,
48         (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
49 };
50 #endif
51
52 /* Set I2C bus speed */
53 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
54                                         unsigned int speed, unsigned int chip)
55 {
56         int half_period;
57
58         if (speed == 0)
59                 return -EINVAL;
60
61         /* OTG I2C clock source and CLK registers are different */
62         if (chip == 2) {
63                 half_period = (get_periph_clk_rate() / speed) / 2;
64                 if (half_period > 0xFF)
65                         return -EINVAL;
66         } else {
67                 half_period = (get_hclk_clk_rate() / speed) / 2;
68                 if (half_period > 0x3FF)
69                         return -EINVAL;
70         }
71
72         writel(half_period, &base->clk_hi);
73         writel(half_period, &base->clk_lo);
74         return 0;
75 }
76
77 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
78 static void __i2c_init(struct lpc32xx_i2c_base *base,
79                        int requested_speed, int slaveadd, unsigned int chip)
80 {
81         /* soft reset (auto-clears) */
82         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
83         /* set HI and LO periods for half of the default speed */
84         __i2c_set_bus_speed(base, requested_speed, chip);
85 }
86
87 /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
88 static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
89 {
90         int stat;
91
92         /* Soft-reset the controller */
93         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
94         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
95                 ;
96         /* Addre slave for write with start before and stop after */
97         writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
98                &base->tx);
99         /* wait for end of transation */
100         while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
101                 ;
102         /* was there no acknowledge? */
103         return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
104 }
105
106 /*
107  * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
108  * Begin write, send address byte(s), begin read, receive data bytes, end.
109  */
110 static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
111                       int alen, u8 *data, int length)
112 {
113         int stat, wlen;
114
115         /* Soft-reset the controller */
116         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
117         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
118                 ;
119         /* do we need to write an address at all? */
120         if (alen) {
121                 /* Address slave in write mode */
122                 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
123                 /* write address bytes */
124                 while (alen--) {
125                         /* compute address byte + stop for the last one */
126                         int a = (addr >> (8 * alen)) & 0xff;
127                         if (!alen)
128                                 a |= LPC32XX_I2C_TX_STOP;
129                         /* Send address byte */
130                         writel(a, &base->tx);
131                 }
132                 /* wait for end of transation */
133                 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
134                         ;
135                 /* clear end-of-transaction flag */
136                 writel(1, &base->stat);
137         }
138         /* do we have to read data at all? */
139         if (length) {
140                 /* Address slave in read mode */
141                 writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
142                 wlen = length;
143                 /* get data */
144                 while (length | wlen) {
145                         /* read status for TFF and RFE */
146                         stat = readl(&base->stat);
147                         /* must we, can we write a trigger byte? */
148                         if ((wlen > 0)
149                            & (!(stat & LPC32XX_I2C_STAT_TFF))) {
150                                 wlen--;
151                                 /* write trigger byte + stop if last */
152                                 writel(wlen ? 0 :
153                                 LPC32XX_I2C_TX_STOP, &base->tx);
154                         }
155                         /* must we, can we read a data byte? */
156                         if ((length > 0)
157                            & (!(stat & LPC32XX_I2C_STAT_RFE))) {
158                                 length--;
159                                 /* read byte */
160                                 *(data++) = readl(&base->rx);
161                         }
162                 }
163                 /* wait for end of transation */
164                 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
165                         ;
166                 /* clear end-of-transaction flag */
167                 writel(1, &base->stat);
168         }
169         /* success */
170         return 0;
171 }
172
173 /*
174  * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
175  * Begin write, send address byte(s), send data bytes, end.
176  */
177 static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
178                        int alen, u8 *data, int length)
179 {
180         int stat;
181
182         /* Soft-reset the controller */
183         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
184         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
185                 ;
186         /* do we need to write anything at all? */
187         if (alen | length)
188                 /* Address slave in write mode */
189                 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
190         else
191                 return 0;
192         /* write address bytes */
193         while (alen) {
194                 /* wait for transmit fifo not full */
195                 stat = readl(&base->stat);
196                 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
197                         alen--;
198                         int a = (addr >> (8 * alen)) & 0xff;
199                         if (!(alen | length))
200                                 a |= LPC32XX_I2C_TX_STOP;
201                         /* Send address byte */
202                         writel(a, &base->tx);
203                 }
204         }
205         while (length) {
206                 /* wait for transmit fifo not full */
207                 stat = readl(&base->stat);
208                 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
209                         /* compute data byte, add stop if length==0 */
210                         length--;
211                         int d = *(data++);
212                         if (!length)
213                                 d |= LPC32XX_I2C_TX_STOP;
214                         /* Send data byte */
215                         writel(d, &base->tx);
216                 }
217         }
218         /* wait for end of transation */
219         while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
220                 ;
221         /* clear end-of-transaction flag */
222         writel(1, &base->stat);
223         return 0;
224 }
225
226 #if !CONFIG_IS_ENABLED(DM_I2C)
227 static void lpc32xx_i2c_init(struct i2c_adapter *adap,
228                              int requested_speed, int slaveadd)
229 {
230         __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
231                    adap->hwadapnr);
232 }
233
234 static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
235 {
236         return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
237 }
238
239 static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
240                             int alen, u8 *data, int length)
241 {
242         return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
243                          alen, data, length);
244 }
245
246 static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
247                              int alen, u8 *data, int length)
248 {
249         return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
250                           alen, data, length);
251 }
252
253 static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
254                                               unsigned int speed)
255 {
256         return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
257                                   adap->hwadapnr);
258 }
259
260 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
261                          lpc32xx_i2c_read, lpc32xx_i2c_write,
262                          lpc32xx_i2c_set_bus_speed,
263                          CONFIG_SYS_I2C_LPC32XX_SPEED,
264                          CONFIG_SYS_I2C_LPC32XX_SLAVE,
265                          0)
266
267 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
268                          lpc32xx_i2c_read, lpc32xx_i2c_write,
269                          lpc32xx_i2c_set_bus_speed,
270                          CONFIG_SYS_I2C_LPC32XX_SPEED,
271                          CONFIG_SYS_I2C_LPC32XX_SLAVE,
272                          1)
273
274 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
275                          lpc32xx_i2c_read, lpc32xx_i2c_write,
276                          lpc32xx_i2c_set_bus_speed,
277                          100000,
278                          0,
279                          2)
280 #else /* CONFIG_DM_I2C */
281 static int lpc32xx_i2c_probe(struct udevice *bus)
282 {
283         struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
284
285         dev->base = dev_read_addr_ptr(bus);
286         __i2c_init(dev->base, dev->speed, 0, dev->index);
287         return 0;
288 }
289
290 static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
291                                   u32 chip_flags)
292 {
293         struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
294         return __i2c_probe_chip(dev->base, chip_addr);
295 }
296
297 static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
298                 int nmsgs)
299 {
300         struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
301         struct i2c_msg *dmsg, *omsg, dummy;
302         uint i = 0, address = 0;
303
304         memset(&dummy, 0, sizeof(struct i2c_msg));
305
306         /* We expect either two messages (one with an offset and one with the
307          * actual data) or one message (just data)
308          */
309         if (nmsgs > 2 || nmsgs == 0) {
310                 debug("%s: Only one or two messages are supported.", __func__);
311                 return -1;
312         }
313
314         omsg = nmsgs == 1 ? &dummy : msg;
315         dmsg = nmsgs == 1 ? msg : msg + 1;
316
317         /* the address is expected to be a uint, not a array. */
318         address = omsg->buf[0];
319         for (i = 1; i < omsg->len; i++)
320                 address = (address << 8) + omsg->buf[i];
321
322         if (dmsg->flags & I2C_M_RD)
323                 return __i2c_read(dev->base, dmsg->addr, address,
324                                   omsg->len, dmsg->buf, dmsg->len);
325         else
326                 return __i2c_write(dev->base, dmsg->addr, address,
327                                    omsg->len, dmsg->buf, dmsg->len);
328 }
329
330 static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
331 {
332         struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
333         return __i2c_set_bus_speed(dev->base, speed, dev->index);
334 }
335
336 static int lpc32xx_i2c_reset(struct udevice *bus)
337 {
338         struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
339
340         __i2c_init(dev->base, dev->speed, 0, dev->index);
341         return 0;
342 }
343
344 static const struct dm_i2c_ops lpc32xx_i2c_ops = {
345         .xfer          = lpc32xx_i2c_xfer,
346         .probe_chip    = lpc32xx_i2c_probe_chip,
347         .deblock       = lpc32xx_i2c_reset,
348         .set_bus_speed = lpc32xx_i2c_set_bus_speed,
349 };
350
351 static const struct udevice_id lpc32xx_i2c_ids[] = {
352         { .compatible = "nxp,pnx-i2c" },
353         { }
354 };
355
356 U_BOOT_DRIVER(i2c_lpc32xx) = {
357         .name                 = "i2c_lpc32xx",
358         .id                   = UCLASS_I2C,
359         .of_match             = lpc32xx_i2c_ids,
360         .probe                = lpc32xx_i2c_probe,
361         .ops                  = &lpc32xx_i2c_ops,
362 };
363 #endif /* CONFIG_DM_I2C */