1 // SPDX-License-Identifier: GPL-2.0+
3 * LPC32xx I2C interface driver
5 * (C) Copyright 2014-2015 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
13 #include <linux/errno.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/i2c.h>
20 * Provide default speed and slave if target did not
23 #if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
24 #define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
27 #if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
28 #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
31 /* TX register fields */
32 #define LPC32XX_I2C_TX_START 0x00000100
33 #define LPC32XX_I2C_TX_STOP 0x00000200
35 /* Control register values */
36 #define LPC32XX_I2C_SOFT_RESET 0x00000100
38 /* Status register values */
39 #define LPC32XX_I2C_STAT_TFF 0x00000400
40 #define LPC32XX_I2C_STAT_RFE 0x00000200
41 #define LPC32XX_I2C_STAT_NAI 0x00000004
42 #define LPC32XX_I2C_STAT_TDI 0x00000001
44 #if !CONFIG_IS_ENABLED(DM_I2C)
45 static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
46 (struct lpc32xx_i2c_base *)I2C1_BASE,
47 (struct lpc32xx_i2c_base *)I2C2_BASE,
48 (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
52 /* Set I2C bus speed */
53 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
54 unsigned int speed, unsigned int chip)
61 /* OTG I2C clock source and CLK registers are different */
63 half_period = (get_periph_clk_rate() / speed) / 2;
64 if (half_period > 0xFF)
67 half_period = (get_hclk_clk_rate() / speed) / 2;
68 if (half_period > 0x3FF)
72 writel(half_period, &base->clk_hi);
73 writel(half_period, &base->clk_lo);
77 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
78 static void __i2c_init(struct lpc32xx_i2c_base *base,
79 int requested_speed, int slaveadd, unsigned int chip)
81 /* soft reset (auto-clears) */
82 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
83 /* set HI and LO periods for half of the default speed */
84 __i2c_set_bus_speed(base, requested_speed, chip);
87 /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
88 static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
92 /* Soft-reset the controller */
93 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
94 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
96 /* Addre slave for write with start before and stop after */
97 writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
99 /* wait for end of transation */
100 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
102 /* was there no acknowledge? */
103 return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
107 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
108 * Begin write, send address byte(s), begin read, receive data bytes, end.
110 static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
111 int alen, u8 *data, int length)
115 /* Soft-reset the controller */
116 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
117 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
119 /* do we need to write an address at all? */
121 /* Address slave in write mode */
122 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
123 /* write address bytes */
125 /* compute address byte + stop for the last one */
126 int a = (addr >> (8 * alen)) & 0xff;
128 a |= LPC32XX_I2C_TX_STOP;
129 /* Send address byte */
130 writel(a, &base->tx);
132 /* wait for end of transation */
133 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
135 /* clear end-of-transaction flag */
136 writel(1, &base->stat);
138 /* do we have to read data at all? */
140 /* Address slave in read mode */
141 writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
144 while (length | wlen) {
145 /* read status for TFF and RFE */
146 stat = readl(&base->stat);
147 /* must we, can we write a trigger byte? */
149 & (!(stat & LPC32XX_I2C_STAT_TFF))) {
151 /* write trigger byte + stop if last */
153 LPC32XX_I2C_TX_STOP, &base->tx);
155 /* must we, can we read a data byte? */
157 & (!(stat & LPC32XX_I2C_STAT_RFE))) {
160 *(data++) = readl(&base->rx);
163 /* wait for end of transation */
164 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
166 /* clear end-of-transaction flag */
167 writel(1, &base->stat);
174 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
175 * Begin write, send address byte(s), send data bytes, end.
177 static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
178 int alen, u8 *data, int length)
182 /* Soft-reset the controller */
183 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
184 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
186 /* do we need to write anything at all? */
188 /* Address slave in write mode */
189 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
192 /* write address bytes */
194 /* wait for transmit fifo not full */
195 stat = readl(&base->stat);
196 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
198 int a = (addr >> (8 * alen)) & 0xff;
199 if (!(alen | length))
200 a |= LPC32XX_I2C_TX_STOP;
201 /* Send address byte */
202 writel(a, &base->tx);
206 /* wait for transmit fifo not full */
207 stat = readl(&base->stat);
208 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
209 /* compute data byte, add stop if length==0 */
213 d |= LPC32XX_I2C_TX_STOP;
215 writel(d, &base->tx);
218 /* wait for end of transation */
219 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
221 /* clear end-of-transaction flag */
222 writel(1, &base->stat);
226 #if !CONFIG_IS_ENABLED(DM_I2C)
227 static void lpc32xx_i2c_init(struct i2c_adapter *adap,
228 int requested_speed, int slaveadd)
230 __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
234 static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
236 return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
239 static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
240 int alen, u8 *data, int length)
242 return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
246 static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
247 int alen, u8 *data, int length)
249 return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
253 static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
256 return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
260 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
261 lpc32xx_i2c_read, lpc32xx_i2c_write,
262 lpc32xx_i2c_set_bus_speed,
263 CONFIG_SYS_I2C_LPC32XX_SPEED,
264 CONFIG_SYS_I2C_LPC32XX_SLAVE,
267 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
268 lpc32xx_i2c_read, lpc32xx_i2c_write,
269 lpc32xx_i2c_set_bus_speed,
270 CONFIG_SYS_I2C_LPC32XX_SPEED,
271 CONFIG_SYS_I2C_LPC32XX_SLAVE,
274 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
275 lpc32xx_i2c_read, lpc32xx_i2c_write,
276 lpc32xx_i2c_set_bus_speed,
280 #else /* CONFIG_DM_I2C */
281 static int lpc32xx_i2c_probe(struct udevice *bus)
283 struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
286 * FIXME: This is not permitted
287 * dev_seq(bus) = dev->index;
290 __i2c_init(dev->base, dev->speed, 0, dev->index);
294 static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
297 struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
298 return __i2c_probe_chip(dev->base, chip_addr);
301 static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
304 struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
305 struct i2c_msg *dmsg, *omsg, dummy;
306 uint i = 0, address = 0;
308 memset(&dummy, 0, sizeof(struct i2c_msg));
310 /* We expect either two messages (one with an offset and one with the
311 * actual data) or one message (just data)
313 if (nmsgs > 2 || nmsgs == 0) {
314 debug("%s: Only one or two messages are supported.", __func__);
318 omsg = nmsgs == 1 ? &dummy : msg;
319 dmsg = nmsgs == 1 ? msg : msg + 1;
321 /* the address is expected to be a uint, not a array. */
322 address = omsg->buf[0];
323 for (i = 1; i < omsg->len; i++)
324 address = (address << 8) + omsg->buf[i];
326 if (dmsg->flags & I2C_M_RD)
327 return __i2c_read(dev->base, dmsg->addr, address,
328 omsg->len, dmsg->buf, dmsg->len);
330 return __i2c_write(dev->base, dmsg->addr, address,
331 omsg->len, dmsg->buf, dmsg->len);
334 static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
336 struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
337 return __i2c_set_bus_speed(dev->base, speed, dev->index);
340 static int lpc32xx_i2c_reset(struct udevice *bus)
342 struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
344 __i2c_init(dev->base, dev->speed, 0, dev->index);
348 static const struct dm_i2c_ops lpc32xx_i2c_ops = {
349 .xfer = lpc32xx_i2c_xfer,
350 .probe_chip = lpc32xx_i2c_probe_chip,
351 .deblock = lpc32xx_i2c_reset,
352 .set_bus_speed = lpc32xx_i2c_set_bus_speed,
355 U_BOOT_DRIVER(i2c_lpc32xx) = {
357 .name = "i2c_lpc32xx",
358 .probe = lpc32xx_i2c_probe,
359 .ops = &lpc32xx_i2c_ops,
361 #endif /* CONFIG_DM_I2C */