drivers/i2c/lpc32xx_i2c.c

   1 /*
   2  * LPC32xx I2C interface driver
   3  *
   4  * (C) Copyright 2014-2015  DENX Software Engineering GmbH
   5  * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  *
   9  * NOTE: This driver should be converted to driver model before June 2017.
  10  * Please see doc/driver-model/i2c-howto.txt for instructions.
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <i2c.h>
  16 #include <linux/errno.h>
  17 #include <asm/arch/clk.h>
  18
  19 /*
  20  * Provide default speed and slave if target did not
  21  */
  22
  23 #if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
  24 #define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
  25 #endif
  26
  27 #if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
  28 #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
  29 #endif
  30
  31 /* i2c register set */
  32 struct lpc32xx_i2c_base {
  33         union {
  34                 u32 rx;
  35                 u32 tx;
  36         };
  37         u32 stat;
  38         u32 ctrl;
  39         u32 clk_hi;
  40         u32 clk_lo;
  41         u32 adr;
  42         u32 rxfl;
  43         u32 txfl;
  44         u32 rxb;
  45         u32 txb;
  46         u32 stx;
  47         u32 stxfl;
  48 };
  49
  50 /* TX register fields */
  51 #define LPC32XX_I2C_TX_START            0x00000100
  52 #define LPC32XX_I2C_TX_STOP             0x00000200
  53
  54 /* Control register values */
  55 #define LPC32XX_I2C_SOFT_RESET          0x00000100
  56
  57 /* Status register values */
  58 #define LPC32XX_I2C_STAT_TFF            0x00000400
  59 #define LPC32XX_I2C_STAT_RFE            0x00000200
  60 #define LPC32XX_I2C_STAT_DRMI           0x00000008
  61 #define LPC32XX_I2C_STAT_NAI            0x00000004
  62 #define LPC32XX_I2C_STAT_TDI            0x00000001
  63
  64 static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
  65         (struct lpc32xx_i2c_base *)I2C1_BASE,
  66         (struct lpc32xx_i2c_base *)I2C2_BASE,
  67         (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
  68 };
  69
  70 /* Set I2C bus speed */
  71 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
  72                                         unsigned int speed, unsigned int chip)
  73 {
  74         int half_period;
  75
  76         if (speed == 0)
  77                 return -EINVAL;
  78
  79         /* OTG I2C clock source and CLK registers are different */
  80         if (chip == 2) {
  81                 half_period = (get_periph_clk_rate() / speed) / 2;
  82                 if (half_period > 0xFF)
  83                         return -EINVAL;
  84         } else {
  85                 half_period = (get_hclk_clk_rate() / speed) / 2;
  86                 if (half_period > 0x3FF)
  87                         return -EINVAL;
  88         }
  89
  90         writel(half_period, &base->clk_hi);
  91         writel(half_period, &base->clk_lo);
  92         return 0;
  93 }
  94
  95 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
  96 static void __i2c_init(struct lpc32xx_i2c_base *base,
  97                        int requested_speed, int slaveadd, unsigned int chip)
  98 {
  99         /* soft reset (auto-clears) */
 100         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 101         /* set HI and LO periods for half of the default speed */
 102         __i2c_set_bus_speed(base, requested_speed, chip);
 103 }
 104
 105 /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
 106 static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
 107 {
 108         int stat;
 109
 110         /* Soft-reset the controller */
 111         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 112         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 113                 ;
 114         /* Addre slave for write with start before and stop after */
 115         writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
 116                &base->tx);
 117         /* wait for end of transation */
 118         while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 119                 ;
 120         /* was there no acknowledge? */
 121         return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
 122 }
 123
 124 /*
 125  * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 126  * Begin write, send address byte(s), begin read, receive data bytes, end.
 127  */
 128 static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
 129                       int alen, u8 *data, int length)
 130 {
 131         int stat, wlen;
 132
 133         /* Soft-reset the controller */
 134         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 135         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 136                 ;
 137         /* do we need to write an address at all? */
 138         if (alen) {
 139                 /* Address slave in write mode */
 140                 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 141                 /* write address bytes */
 142                 while (alen--) {
 143                         /* compute address byte + stop for the last one */
 144                         int a = (addr >> (8 * alen)) & 0xff;
 145                         if (!alen)
 146                                 a |= LPC32XX_I2C_TX_STOP;
 147                         /* Send address byte */
 148                         writel(a, &base->tx);
 149                 }
 150                 /* wait for end of transation */
 151                 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 152                         ;
 153                 /* clear end-of-transaction flag */
 154                 writel(1, &base->stat);
 155         }
 156         /* do we have to read data at all? */
 157         if (length) {
 158                 /* Address slave in read mode */
 159                 writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 160                 wlen = length;
 161                 /* get data */
 162                 while (length | wlen) {
 163                         /* read status for TFF and RFE */
 164                         stat = readl(&base->stat);
 165                         /* must we, can we write a trigger byte? */
 166                         if ((wlen > 0)
 167                            & (!(stat & LPC32XX_I2C_STAT_TFF))) {
 168                                 wlen--;
 169                                 /* write trigger byte + stop if last */
 170                                 writel(wlen ? 0 :
 171                                 LPC32XX_I2C_TX_STOP, &base->tx);
 172                         }
 173                         /* must we, can we read a data byte? */
 174                         if ((length > 0)
 175                            & (!(stat & LPC32XX_I2C_STAT_RFE))) {
 176                                 length--;
 177                                 /* read byte */
 178                                 *(data++) = readl(&base->rx);
 179                         }
 180                 }
 181                 /* wait for end of transation */
 182                 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 183                         ;
 184                 /* clear end-of-transaction flag */
 185                 writel(1, &base->stat);
 186         }
 187         /* success */
 188         return 0;
 189 }
 190
 191 /*
 192  * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 193  * Begin write, send address byte(s), send data bytes, end.
 194  */
 195 static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
 196                        int alen, u8 *data, int length)
 197 {
 198         int stat;
 199
 200         /* Soft-reset the controller */
 201         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 202         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 203                 ;
 204         /* do we need to write anything at all? */
 205         if (alen | length)
 206                 /* Address slave in write mode */
 207                 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 208         else
 209                 return 0;
 210         /* write address bytes */
 211         while (alen) {
 212                 /* wait for transmit fifo not full */
 213                 stat = readl(&base->stat);
 214                 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
 215                         alen--;
 216                         int a = (addr >> (8 * alen)) & 0xff;
 217                         if (!(alen | length))
 218                                 a |= LPC32XX_I2C_TX_STOP;
 219                         /* Send address byte */
 220                         writel(a, &base->tx);
 221                 }
 222         }
 223         while (length) {
 224                 /* wait for transmit fifo not full */
 225                 stat = readl(&base->stat);
 226                 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
 227                         /* compute data byte, add stop if length==0 */
 228                         length--;
 229                         int d = *(data++);
 230                         if (!length)
 231                                 d |= LPC32XX_I2C_TX_STOP;
 232                         /* Send data byte */
 233                         writel(d, &base->tx);
 234                 }
 235         }
 236         /* wait for end of transation */
 237         while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 238                 ;
 239         /* clear end-of-transaction flag */
 240         writel(1, &base->stat);
 241         return 0;
 242 }
 243
 244 static void lpc32xx_i2c_init(struct i2c_adapter *adap,
 245                              int requested_speed, int slaveadd)
 246 {
 247         __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
 248                    adap->hwadapnr);
 249 }
 250
 251 static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
 252 {
 253         return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
 254 }
 255
 256 static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 257                             int alen, u8 *data, int length)
 258 {
 259         return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
 260                          alen, data, length);
 261 }
 262
 263 static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 264                              int alen, u8 *data, int length)
 265 {
 266         return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
 267                           alen, data, length);
 268 }
 269
 270 static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
 271                                               unsigned int speed)
 272 {
 273         return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
 274                                   adap->hwadapnr);
 275 }
 276
 277 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
 278                          lpc32xx_i2c_read, lpc32xx_i2c_write,
 279                          lpc32xx_i2c_set_bus_speed,
 280                          CONFIG_SYS_I2C_LPC32XX_SPEED,
 281                          CONFIG_SYS_I2C_LPC32XX_SLAVE,
 282                          0)
 283
 284 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
 285                          lpc32xx_i2c_read, lpc32xx_i2c_write,
 286                          lpc32xx_i2c_set_bus_speed,
 287                          CONFIG_SYS_I2C_LPC32XX_SPEED,
 288                          CONFIG_SYS_I2C_LPC32XX_SLAVE,
 289                          1)
 290
 291 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
 292                          lpc32xx_i2c_read, lpc32xx_i2c_write,
 293                          lpc32xx_i2c_set_bus_speed,
 294                          100000,
 295                          0,
 296                          2)