drivers/i2c/kona_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Broadcom Corporation.
   4  *
   5  * NOTE: This driver should be converted to driver model before June 2017.
   6  * Please see doc/driver-model/i2c-howto.txt for instructions.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <linux/errno.h>
  12 #include <asm/arch/sysmap.h>
  13 #include <asm/kona-common/clk.h>
  14 #include <i2c.h>
  15
  16 /* Hardware register offsets and field defintions */
  17 #define CS_OFFSET                               0x00000020
  18 #define CS_ACK_SHIFT                            3
  19 #define CS_ACK_MASK                             0x00000008
  20 #define CS_ACK_CMD_GEN_START                    0x00000000
  21 #define CS_ACK_CMD_GEN_RESTART                  0x00000001
  22 #define CS_CMD_SHIFT                            1
  23 #define CS_CMD_CMD_NO_ACTION                    0x00000000
  24 #define CS_CMD_CMD_START_RESTART                0x00000001
  25 #define CS_CMD_CMD_STOP                         0x00000002
  26 #define CS_EN_SHIFT                             0
  27 #define CS_EN_CMD_ENABLE_BSC                    0x00000001
  28
  29 #define TIM_OFFSET                              0x00000024
  30 #define TIM_PRESCALE_SHIFT                      6
  31 #define TIM_P_SHIFT                             3
  32 #define TIM_NO_DIV_SHIFT                        2
  33 #define TIM_DIV_SHIFT                           0
  34
  35 #define DAT_OFFSET                              0x00000028
  36
  37 #define TOUT_OFFSET                             0x0000002c
  38
  39 #define TXFCR_OFFSET                            0x0000003c
  40 #define TXFCR_FIFO_FLUSH_MASK                   0x00000080
  41 #define TXFCR_FIFO_EN_MASK                      0x00000040
  42
  43 #define IER_OFFSET                              0x00000044
  44 #define IER_READ_COMPLETE_INT_MASK              0x00000010
  45 #define IER_I2C_INT_EN_MASK                     0x00000008
  46 #define IER_FIFO_INT_EN_MASK                    0x00000002
  47 #define IER_NOACK_EN_MASK                       0x00000001
  48
  49 #define ISR_OFFSET                              0x00000048
  50 #define ISR_RESERVED_MASK                       0xffffff60
  51 #define ISR_CMDBUSY_MASK                        0x00000080
  52 #define ISR_READ_COMPLETE_MASK                  0x00000010
  53 #define ISR_SES_DONE_MASK                       0x00000008
  54 #define ISR_ERR_MASK                            0x00000004
  55 #define ISR_TXFIFOEMPTY_MASK                    0x00000002
  56 #define ISR_NOACK_MASK                          0x00000001
  57
  58 #define CLKEN_OFFSET                            0x0000004c
  59 #define CLKEN_AUTOSENSE_OFF_MASK                0x00000080
  60 #define CLKEN_M_SHIFT                           4
  61 #define CLKEN_N_SHIFT                           1
  62 #define CLKEN_CLKEN_MASK                        0x00000001
  63
  64 #define FIFO_STATUS_OFFSET                      0x00000054
  65 #define FIFO_STATUS_RXFIFO_EMPTY_MASK           0x00000004
  66 #define FIFO_STATUS_TXFIFO_EMPTY_MASK           0x00000010
  67
  68 #define HSTIM_OFFSET                            0x00000058
  69 #define HSTIM_HS_MODE_MASK                      0x00008000
  70 #define HSTIM_HS_HOLD_SHIFT                     10
  71 #define HSTIM_HS_HIGH_PHASE_SHIFT               5
  72 #define HSTIM_HS_SETUP_SHIFT                    0
  73
  74 #define PADCTL_OFFSET                           0x0000005c
  75 #define PADCTL_PAD_OUT_EN_MASK                  0x00000004
  76
  77 #define RXFCR_OFFSET                            0x00000068
  78 #define RXFCR_NACK_EN_SHIFT                     7
  79 #define RXFCR_READ_COUNT_SHIFT                  0
  80 #define RXFIFORDOUT_OFFSET                      0x0000006c
  81
  82 /* Locally used constants */
  83 #define MAX_RX_FIFO_SIZE                64U     /* bytes */
  84 #define MAX_TX_FIFO_SIZE                64U     /* bytes */
  85
  86 #define I2C_TIMEOUT                     100000  /* usecs */
  87
  88 #define WAIT_INT_CHK                    100     /* usecs */
  89 #if I2C_TIMEOUT % WAIT_INT_CHK
  90 #error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
  91 #endif
  92
  93 /* Operations that can be commanded to the controller */
  94 enum bcm_kona_cmd_t {
  95         BCM_CMD_NOACTION = 0,
  96         BCM_CMD_START,
  97         BCM_CMD_RESTART,
  98         BCM_CMD_STOP,
  99 };
 100
 101 enum bus_speed_index {
 102         BCM_SPD_100K = 0,
 103         BCM_SPD_400K,
 104         BCM_SPD_1MHZ,
 105 };
 106
 107 /* Internal divider settings for standard mode, fast mode and fast mode plus */
 108 struct bus_speed_cfg {
 109         uint8_t time_m;         /* Number of cycles for setup time */
 110         uint8_t time_n;         /* Number of cycles for hold time */
 111         uint8_t prescale;       /* Prescale divider */
 112         uint8_t time_p;         /* Timing coefficient */
 113         uint8_t no_div;         /* Disable clock divider */
 114         uint8_t time_div;       /* Post-prescale divider */
 115 };
 116
 117 static const struct bus_speed_cfg std_cfg_table[] = {
 118         [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
 119         [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
 120         [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
 121 };
 122
 123 struct bcm_kona_i2c_dev {
 124         void *base;
 125         uint speed;
 126         const struct bus_speed_cfg *std_cfg;
 127 };
 128
 129 /* Keep these two defines in sync */
 130 #define DEF_SPD 100000
 131 #define DEF_SPD_ENUM BCM_SPD_100K
 132
 133 #define DEF_DEVICE(num) \
 134 {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
 135
 136 static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
 137 #ifdef CONFIG_SYS_I2C_BASE0
 138         DEF_DEVICE(0),
 139 #endif
 140 #ifdef CONFIG_SYS_I2C_BASE1
 141         DEF_DEVICE(1),
 142 #endif
 143 #ifdef CONFIG_SYS_I2C_BASE2
 144         DEF_DEVICE(2),
 145 #endif
 146 #ifdef CONFIG_SYS_I2C_BASE3
 147         DEF_DEVICE(3),
 148 #endif
 149 #ifdef CONFIG_SYS_I2C_BASE4
 150         DEF_DEVICE(4),
 151 #endif
 152 #ifdef CONFIG_SYS_I2C_BASE5
 153         DEF_DEVICE(5),
 154 #endif
 155 };
 156
 157 #define I2C_M_TEN       0x0010  /* ten bit address */
 158 #define I2C_M_RD        0x0001  /* read data */
 159 #define I2C_M_NOSTART   0x4000  /* no restart between msgs */
 160
 161 struct kona_i2c_msg {
 162         uint16_t addr;
 163         uint16_t flags;
 164         uint16_t len;
 165         uint8_t *buf;
 166 };
 167
 168 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
 169                                           enum bcm_kona_cmd_t cmd)
 170 {
 171         debug("%s, %d\n", __func__, cmd);
 172
 173         switch (cmd) {
 174         case BCM_CMD_NOACTION:
 175                 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
 176                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 177                        dev->base + CS_OFFSET);
 178                 break;
 179
 180         case BCM_CMD_START:
 181                 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
 182                        (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
 183                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 184                        dev->base + CS_OFFSET);
 185                 break;
 186
 187         case BCM_CMD_RESTART:
 188                 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
 189                        (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
 190                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 191                        dev->base + CS_OFFSET);
 192                 break;
 193
 194         case BCM_CMD_STOP:
 195                 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
 196                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 197                        dev->base + CS_OFFSET);
 198                 break;
 199
 200         default:
 201                 printf("Unknown command %d\n", cmd);
 202         }
 203 }
 204
 205 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
 206 {
 207         writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
 208                dev->base + CLKEN_OFFSET);
 209 }
 210
 211 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
 212 {
 213         writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
 214                dev->base + CLKEN_OFFSET);
 215 }
 216
 217 /* Wait until at least one of the mask bit(s) are set */
 218 static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
 219                                           unsigned long time_left,
 220                                           uint32_t mask)
 221 {
 222         uint32_t status;
 223
 224         while (time_left) {
 225                 status = readl(dev->base + ISR_OFFSET);
 226
 227                 if ((status & ~ISR_RESERVED_MASK) == 0) {
 228                         debug("Bogus I2C interrupt 0x%x\n", status);
 229                         continue;
 230                 }
 231
 232                 /* Must flush the TX FIFO when NAK detected */
 233                 if (status & ISR_NOACK_MASK)
 234                         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
 235                                dev->base + TXFCR_OFFSET);
 236
 237                 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
 238
 239                 if (status & mask) {
 240                         /* We are done since one of the mask bits are set */
 241                         return time_left;
 242                 }
 243                 udelay(WAIT_INT_CHK);
 244                 time_left -= WAIT_INT_CHK;
 245         }
 246         return 0;
 247 }
 248
 249 /* Send command to I2C bus */
 250 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
 251                                  enum bcm_kona_cmd_t cmd)
 252 {
 253         int rc = 0;
 254         unsigned long time_left = I2C_TIMEOUT;
 255
 256         /* Send the command */
 257         bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
 258
 259         /* Wait for transaction to finish or timeout */
 260         time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
 261
 262         if (!time_left) {
 263                 printf("controller timed out\n");
 264                 rc = -ETIMEDOUT;
 265         }
 266
 267         /* Clear command */
 268         bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
 269
 270         return rc;
 271 }
 272
 273 /* Read a single RX FIFO worth of data from the i2c bus */
 274 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
 275                                          uint8_t *buf, unsigned int len,
 276                                          unsigned int last_byte_nak)
 277 {
 278         unsigned long time_left = I2C_TIMEOUT;
 279
 280         /* Start the RX FIFO */
 281         writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
 282                (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
 283
 284         /* Wait for FIFO read to complete */
 285         time_left =
 286             wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
 287
 288         if (!time_left) {
 289                 printf("RX FIFO time out\n");
 290                 return -EREMOTEIO;
 291         }
 292
 293         /* Read data from FIFO */
 294         for (; len > 0; len--, buf++)
 295                 *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
 296
 297         return 0;
 298 }
 299
 300 /* Read any amount of data using the RX FIFO from the i2c bus */
 301 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
 302                                   struct kona_i2c_msg *msg)
 303 {
 304         unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
 305         unsigned int last_byte_nak = 0;
 306         unsigned int bytes_read = 0;
 307         int rc;
 308
 309         uint8_t *tmp_buf = msg->buf;
 310
 311         while (bytes_read < msg->len) {
 312                 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
 313                         last_byte_nak = 1;      /* NAK last byte of transfer */
 314                         bytes_to_read = msg->len - bytes_read;
 315                 }
 316
 317                 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
 318                                                    last_byte_nak);
 319                 if (rc < 0)
 320                         return -EREMOTEIO;
 321
 322                 bytes_read += bytes_to_read;
 323                 tmp_buf += bytes_to_read;
 324         }
 325
 326         return 0;
 327 }
 328
 329 /* Write a single byte of data to the i2c bus */
 330 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
 331                                    unsigned int nak_expected)
 332 {
 333         unsigned long time_left = I2C_TIMEOUT;
 334         unsigned int nak_received;
 335
 336         /* Clear pending session done interrupt */
 337         writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
 338
 339         /* Send one byte of data */
 340         writel(data, dev->base + DAT_OFFSET);
 341
 342         time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
 343
 344         if (!time_left) {
 345                 debug("controller timed out\n");
 346                 return -ETIMEDOUT;
 347         }
 348
 349         nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
 350
 351         if (nak_received ^ nak_expected) {
 352                 debug("unexpected NAK/ACK\n");
 353                 return -EREMOTEIO;
 354         }
 355
 356         return 0;
 357 }
 358
 359 /* Write a single TX FIFO worth of data to the i2c bus */
 360 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
 361                                           uint8_t *buf, unsigned int len)
 362 {
 363         int k;
 364         unsigned long time_left = I2C_TIMEOUT;
 365         unsigned int fifo_status;
 366
 367         /* Write data into FIFO */
 368         for (k = 0; k < len; k++)
 369                 writel(buf[k], (dev->base + DAT_OFFSET));
 370
 371         /* Wait for FIFO to empty */
 372         do {
 373                 time_left =
 374                     wait_for_int_timeout(dev, time_left,
 375                                          (IER_FIFO_INT_EN_MASK |
 376                                           IER_NOACK_EN_MASK));
 377                 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
 378         } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
 379
 380         /* Check if there was a NAK */
 381         if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
 382                 printf("unexpected NAK\n");
 383                 return -EREMOTEIO;
 384         }
 385
 386         /* Check if a timeout occurred */
 387         if (!time_left) {
 388                 printf("completion timed out\n");
 389                 return -EREMOTEIO;
 390         }
 391
 392         return 0;
 393 }
 394
 395 /* Write any amount of data using TX FIFO to the i2c bus */
 396 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
 397                                    struct kona_i2c_msg *msg)
 398 {
 399         unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
 400         unsigned int bytes_written = 0;
 401         int rc;
 402
 403         uint8_t *tmp_buf = msg->buf;
 404
 405         while (bytes_written < msg->len) {
 406                 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
 407                         bytes_to_write = msg->len - bytes_written;
 408
 409                 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
 410                                                     bytes_to_write);
 411                 if (rc < 0)
 412                         return -EREMOTEIO;
 413
 414                 bytes_written += bytes_to_write;
 415                 tmp_buf += bytes_to_write;
 416         }
 417
 418         return 0;
 419 }
 420
 421 /* Send i2c address */
 422 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
 423                                 struct kona_i2c_msg *msg)
 424 {
 425         unsigned char addr;
 426
 427         if (msg->flags & I2C_M_TEN) {
 428                 /* First byte is 11110XX0 where XX is upper 2 bits */
 429                 addr = 0xf0 | ((msg->addr & 0x300) >> 7);
 430                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 431                         return -EREMOTEIO;
 432
 433                 /* Second byte is the remaining 8 bits */
 434                 addr = msg->addr & 0xff;
 435                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 436                         return -EREMOTEIO;
 437
 438                 if (msg->flags & I2C_M_RD) {
 439                         /* For read, send restart command */
 440                         if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
 441                                 return -EREMOTEIO;
 442
 443                         /* Then re-send the first byte with the read bit set */
 444                         addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
 445                         if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 446                                 return -EREMOTEIO;
 447                 }
 448         } else {
 449                 addr = msg->addr << 1;
 450
 451                 if (msg->flags & I2C_M_RD)
 452                         addr |= 1;
 453
 454                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 455                         return -EREMOTEIO;
 456         }
 457
 458         return 0;
 459 }
 460
 461 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
 462 {
 463         writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
 464                dev->base + CLKEN_OFFSET);
 465 }
 466
 467 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
 468 {
 469         writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
 470                dev->base + HSTIM_OFFSET);
 471
 472         writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
 473                (dev->std_cfg->time_p << TIM_P_SHIFT) |
 474                (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
 475                (dev->std_cfg->time_div << TIM_DIV_SHIFT),
 476                dev->base + TIM_OFFSET);
 477
 478         writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
 479                (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
 480                CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
 481 }
 482
 483 /* Master transfer function */
 484 static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
 485                              struct kona_i2c_msg msgs[], int num)
 486 {
 487         struct kona_i2c_msg *pmsg;
 488         int rc = 0;
 489         int i;
 490
 491         /* Enable pad output */
 492         writel(0, dev->base + PADCTL_OFFSET);
 493
 494         /* Enable internal clocks */
 495         bcm_kona_i2c_enable_clock(dev);
 496
 497         /* Send start command */
 498         rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
 499         if (rc < 0) {
 500                 printf("Start command failed rc = %d\n", rc);
 501                 goto xfer_disable_pad;
 502         }
 503
 504         /* Loop through all messages */
 505         for (i = 0; i < num; i++) {
 506                 pmsg = &msgs[i];
 507
 508                 /* Send restart for subsequent messages */
 509                 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
 510                         rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
 511                         if (rc < 0) {
 512                                 printf("restart cmd failed rc = %d\n", rc);
 513                                 goto xfer_send_stop;
 514                         }
 515                 }
 516
 517                 /* Send slave address */
 518                 if (!(pmsg->flags & I2C_M_NOSTART)) {
 519                         rc = bcm_kona_i2c_do_addr(dev, pmsg);
 520                         if (rc < 0) {
 521                                 debug("NAK from addr %2.2x msg#%d rc = %d\n",
 522                                       pmsg->addr, i, rc);
 523                                 goto xfer_send_stop;
 524                         }
 525                 }
 526
 527                 /* Perform data transfer */
 528                 if (pmsg->flags & I2C_M_RD) {
 529                         rc = bcm_kona_i2c_read_fifo(dev, pmsg);
 530                         if (rc < 0) {
 531                                 printf("read failure\n");
 532                                 goto xfer_send_stop;
 533                         }
 534                 } else {
 535                         rc = bcm_kona_i2c_write_fifo(dev, pmsg);
 536                         if (rc < 0) {
 537                                 printf("write failure");
 538                                 goto xfer_send_stop;
 539                         }
 540                 }
 541         }
 542
 543         rc = num;
 544
 545 xfer_send_stop:
 546         /* Send a STOP command */
 547         bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
 548
 549 xfer_disable_pad:
 550         /* Disable pad output */
 551         writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
 552
 553         /* Stop internal clock */
 554         bcm_kona_i2c_disable_clock(dev);
 555
 556         return rc;
 557 }
 558
 559 static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
 560                                           uint speed)
 561 {
 562         switch (speed) {
 563         case 100000:
 564                 dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
 565                 break;
 566         case 400000:
 567                 dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
 568                 break;
 569         case 1000000:
 570                 dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
 571                 break;
 572         default:
 573                 printf("%d hz bus speed not supported\n", speed);
 574                 return -EINVAL;
 575         }
 576         dev->speed = speed;
 577         return 0;
 578 }
 579
 580 static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
 581 {
 582         /* Parse bus speed */
 583         bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
 584
 585         /* Enable internal clocks */
 586         bcm_kona_i2c_enable_clock(dev);
 587
 588         /* Configure internal dividers */
 589         bcm_kona_i2c_config_timing(dev);
 590
 591         /* Disable timeout */
 592         writel(0, dev->base + TOUT_OFFSET);
 593
 594         /* Enable autosense */
 595         bcm_kona_i2c_enable_autosense(dev);
 596
 597         /* Enable TX FIFO */
 598         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
 599                dev->base + TXFCR_OFFSET);
 600
 601         /* Mask all interrupts */
 602         writel(0, dev->base + IER_OFFSET);
 603
 604         /* Clear all pending interrupts */
 605         writel(ISR_CMDBUSY_MASK |
 606                ISR_READ_COMPLETE_MASK |
 607                ISR_SES_DONE_MASK |
 608                ISR_ERR_MASK |
 609                ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
 610
 611         /* Enable the controller but leave it idle */
 612         bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
 613
 614         /* Disable pad output */
 615         writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
 616 }
 617
 618 /*
 619  * uboot layer
 620  */
 621 struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
 622 {
 623         return &g_i2c_devs[adap->hwadapnr];
 624 }
 625
 626 static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 627 {
 628         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 629
 630         if (clk_bsc_enable(dev->base))
 631                 return;
 632
 633         bcm_kona_i2c_init(dev);
 634 }
 635
 636 static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 637                          int alen, uchar *buffer, int len)
 638 {
 639         /* msg[0] writes the addr, msg[1] reads the data */
 640         struct kona_i2c_msg msg[2];
 641         unsigned char msgbuf0[64];
 642         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 643
 644         msg[0].addr = chip;
 645         msg[0].flags = 0;
 646         msg[0].len = 1;
 647         msg[0].buf = msgbuf0;   /* msgbuf0 contains incrementing reg addr */
 648
 649         msg[1].addr = chip;
 650         msg[1].flags = I2C_M_RD;
 651         /* msg[1].buf dest ptr increments each read */
 652
 653         msgbuf0[0] = (unsigned char)addr;
 654         msg[1].buf = buffer;
 655         msg[1].len = len;
 656         if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
 657                 /* Sending 2 i2c messages */
 658                 kona_i2c_init(adap, adap->speed, adap->slaveaddr);
 659                 debug("I2C read: I/O error\n");
 660                 return -EIO;
 661         }
 662         return 0;
 663 }
 664
 665 static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 666                           int alen, uchar *buffer, int len)
 667 {
 668         struct kona_i2c_msg msg[1];
 669         unsigned char msgbuf0[64];
 670         unsigned int i;
 671         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 672
 673         msg[0].addr = chip;
 674         msg[0].flags = 0;
 675         msg[0].len = 2;         /* addr byte plus data */
 676         msg[0].buf = msgbuf0;
 677
 678         for (i = 0; i < len; i++) {
 679                 msgbuf0[0] = addr++;
 680                 msgbuf0[1] = buffer[i];
 681                 if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
 682                         kona_i2c_init(adap, adap->speed, adap->slaveaddr);
 683                         debug("I2C write: I/O error\n");
 684                         return -EIO;
 685                 }
 686         }
 687         return 0;
 688 }
 689
 690 static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
 691 {
 692         uchar tmp;
 693
 694         /*
 695          * read addr 0x0 of the given chip.
 696          */
 697         return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
 698 }
 699
 700 static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 701 {
 702         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 703         return bcm_kona_i2c_assign_bus_speed(dev, speed);
 704 }
 705
 706 /*
 707  * Register kona i2c adapters. Keep the order below so
 708  * that the bus number matches the adapter number.
 709  */
 710 #define DEF_ADAPTER(num) \
 711 U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
 712                          kona_i2c_read, kona_i2c_write, \
 713                          kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
 714
 715 #ifdef CONFIG_SYS_I2C_BASE0
 716         DEF_ADAPTER(0)
 717 #endif
 718 #ifdef CONFIG_SYS_I2C_BASE1
 719         DEF_ADAPTER(1)
 720 #endif
 721 #ifdef CONFIG_SYS_I2C_BASE2
 722         DEF_ADAPTER(2)
 723 #endif
 724 #ifdef CONFIG_SYS_I2C_BASE3
 725         DEF_ADAPTER(3)
 726 #endif
 727 #ifdef CONFIG_SYS_I2C_BASE4
 728         DEF_ADAPTER(4)
 729 #endif
 730 #ifdef CONFIG_SYS_I2C_BASE5
 731         DEF_ADAPTER(5)
 732 #endif