1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Broadcom
7 #include <asm/global_data.h>
14 #include "iproc_i2c.h"
16 DECLARE_GLOBAL_DATA_PTR;
18 struct iproc_i2c_regs {
25 u32 blnks[6]; /* Not to be used */
37 struct iproc_i2c_regs __iomem *base; /* register base */
42 /* Function to read a value from specified register. */
43 static unsigned int iproc_i2c_reg_read(u32 *reg_addr)
47 val = readl((void *)(reg_addr));
48 return cpu_to_le32(val);
51 /* Function to write a value ('val') in to a specified register. */
52 static int iproc_i2c_reg_write(u32 *reg_addr, unsigned int val)
54 val = cpu_to_le32(val);
55 writel(val, (void *)(reg_addr));
60 static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata)
62 struct iproc_i2c_regs *base = bus_prvdata->base;
65 debug("\n----------------------------------------------\n");
66 debug("%s: Dumping SMBus registers...\n", __func__);
68 regval = iproc_i2c_reg_read(&base->cfg_reg);
69 debug("CCB_SMB_CFG_REG=0x%08X\n", regval);
71 regval = iproc_i2c_reg_read(&base->timg_cfg);
72 debug("CCB_SMB_TIMGCFG_REG=0x%08X\n", regval);
74 regval = iproc_i2c_reg_read(&base->addr_reg);
75 debug("CCB_SMB_ADDR_REG=0x%08X\n", regval);
77 regval = iproc_i2c_reg_read(&base->mstr_fifo_ctrl);
78 debug("CCB_SMB_MSTRFIFOCTL_REG=0x%08X\n", regval);
80 regval = iproc_i2c_reg_read(&base->slv_fifo_ctrl);
81 debug("CCB_SMB_SLVFIFOCTL_REG=0x%08X\n", regval);
83 regval = iproc_i2c_reg_read(&base->bitbng_ctrl);
84 debug("CCB_SMB_BITBANGCTL_REG=0x%08X\n", regval);
86 regval = iproc_i2c_reg_read(&base->mstr_cmd);
87 debug("CCB_SMB_MSTRCMD_REG=0x%08X\n", regval);
89 regval = iproc_i2c_reg_read(&base->slv_cmd);
90 debug("CCB_SMB_SLVCMD_REG=0x%08X\n", regval);
92 regval = iproc_i2c_reg_read(&base->evt_en);
93 debug("CCB_SMB_EVTEN_REG=0x%08X\n", regval);
95 regval = iproc_i2c_reg_read(&base->evt_sts);
96 debug("CCB_SMB_EVTSTS_REG=0x%08X\n", regval);
98 regval = iproc_i2c_reg_read(&base->mstr_datawr);
99 debug("CCB_SMB_MSTRDATAWR_REG=0x%08X\n", regval);
101 regval = iproc_i2c_reg_read(&base->mstr_datard);
102 debug("CCB_SMB_MSTRDATARD_REG=0x%08X\n", regval);
104 regval = iproc_i2c_reg_read(&base->slv_datawr);
105 debug("CCB_SMB_SLVDATAWR_REG=0x%08X\n", regval);
107 regval = iproc_i2c_reg_read(&base->slv_datard);
108 debug("CCB_SMB_SLVDATARD_REG=0x%08X\n", regval);
110 debug("----------------------------------------------\n\n");
114 static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata)
121 * Function to ensure that the previous transaction was completed before
122 * initiating a new transaction. It can also be used in polling mode to
123 * check status of completion of a command
125 static int iproc_i2c_startbusy_wait(struct iproc_i2c *bus_prvdata)
127 struct iproc_i2c_regs *base = bus_prvdata->base;
130 regval = iproc_i2c_reg_read(&base->mstr_cmd);
132 /* Check if an operation is in progress. During probe it won't be.
133 * But when shutdown/remove was called we want to make sure that
134 * the transaction in progress completed
136 if (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
142 regval = iproc_i2c_reg_read(&base->mstr_cmd);
144 /* If start-busy bit cleared, exit the loop */
145 } while ((regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) &&
146 (i < IPROC_SMB_MAX_RETRIES));
148 if (i >= IPROC_SMB_MAX_RETRIES) {
149 pr_err("%s: START_BUSY bit didn't clear, exiting\n",
158 * This function set clock frequency for SMBus block. As per hardware
159 * engineering, the clock frequency can be changed dynamically.
161 static int iproc_i2c_set_clk_freq(struct iproc_i2c *bus_prvdata)
163 struct iproc_i2c_regs *base = bus_prvdata->base;
166 regval = iproc_i2c_reg_read(&base->timg_cfg);
168 switch (bus_prvdata->bus_speed) {
169 case I2C_SPEED_STANDARD_RATE:
170 regval &= ~CCB_SMB_TIMGCFG_MODE400_MASK;
173 case I2C_SPEED_FAST_RATE:
174 regval |= CCB_SMB_TIMGCFG_MODE400_MASK;
181 iproc_i2c_reg_write(&base->timg_cfg, regval);
185 static int iproc_i2c_init(struct udevice *bus)
187 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
188 struct iproc_i2c_regs *base = bus_prvdata->base;
191 debug("\nEntering %s\n", __func__);
193 /* Put controller in reset */
194 regval = iproc_i2c_reg_read(&base->cfg_reg);
195 regval |= CCB_SMB_CFG_RST_MASK;
196 regval &= ~CCB_SMB_CFG_SMBEN_MASK;
197 iproc_i2c_reg_write(&base->cfg_reg, regval);
199 /* Wait 100 usec as per spec */
202 /* bring controller out of reset */
203 regval &= ~CCB_SMB_CFG_RST_MASK;
204 iproc_i2c_reg_write(&base->cfg_reg, regval);
206 /* Flush Tx, Rx FIFOs. Note we are setting the Rx FIFO threshold to 0.
207 * May be OK since we are setting RX_EVENT and RX_FIFO_FULL interrupts
209 regval = CCB_SMB_MSTRRXFIFOFLSH_MASK | CCB_SMB_MSTRTXFIFOFLSH_MASK;
210 iproc_i2c_reg_write(&base->mstr_fifo_ctrl, regval);
212 /* Enable SMbus block. Note, we are setting MASTER_RETRY_COUNT to zero
213 * since there will be only one master
215 regval = iproc_i2c_reg_read(&base->cfg_reg);
216 regval |= CCB_SMB_CFG_SMBEN_MASK;
217 iproc_i2c_reg_write(&base->cfg_reg, regval);
219 /* Set default clock frequency */
220 iproc_i2c_set_clk_freq(bus_prvdata);
223 iproc_i2c_reg_write(&base->evt_en, 0);
225 /* Clear intrs (W1TC) */
226 regval = iproc_i2c_reg_read(&base->evt_sts);
227 iproc_i2c_reg_write(&base->evt_sts, regval);
229 bus_prvdata->i2c_init_done = 1;
231 iproc_dump_i2c_regs(bus_prvdata);
232 debug("%s: Init successful\n", __func__);
238 * This function copies data to SMBus's Tx FIFO. Valid for write transactions
241 * base_addr: Mapped address of this SMBus instance
242 * dev_addr: SMBus (I2C) device address. We are assuming 7-bit addresses
244 * info: Data to copy in to Tx FIFO. For read commands, the size should be
245 * set to zero by the caller
248 static void iproc_i2c_write_trans_data(struct iproc_i2c *bus_prvdata,
249 unsigned short dev_addr,
250 struct iproc_xact_info *info)
252 struct iproc_i2c_regs *base = bus_prvdata->base;
255 unsigned int num_data_bytes = 0;
257 debug("%s: dev_addr=0x%X cmd_valid=%d cmd=0x%02x size=%u proto=%d buf[] %x\n",
258 __func__, dev_addr, info->cmd_valid,
259 info->command, info->size, info->smb_proto, info->data[0]);
261 /* Write SMBus device address first */
262 /* Note, we are assuming 7-bit addresses for now. For 10-bit addresses,
263 * we may have one more write to send the upper 3 bits of 10-bit addr
265 iproc_i2c_reg_write(&base->mstr_datawr, dev_addr);
267 /* If the protocol needs command code, copy it */
269 iproc_i2c_reg_write(&base->mstr_datawr, info->command);
271 /* Depending on the SMBus protocol, we need to write additional
272 * transaction data in to Tx FIFO. Refer to section 5.5 of SMBus
273 * spec for sequence for a transaction
275 switch (info->smb_proto) {
276 case SMBUS_PROT_RECV_BYTE:
277 /* No additional data to be written */
281 case SMBUS_PROT_SEND_BYTE:
282 num_data_bytes = info->size;
285 case SMBUS_PROT_RD_BYTE:
286 case SMBUS_PROT_RD_WORD:
287 case SMBUS_PROT_BLK_RD:
288 /* Write slave address with R/W~ set (bit #0) */
289 iproc_i2c_reg_write(&base->mstr_datawr,
294 case SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL:
295 iproc_i2c_reg_write(&base->mstr_datawr,
297 CCB_SMB_MSTRWRSTS_MASK);
301 case SMBUS_PROT_WR_BYTE:
302 case SMBUS_PROT_WR_WORD:
303 /* No additional bytes to be written.
304 * Data portion is written in the
307 num_data_bytes = info->size;
310 case SMBUS_PROT_BLK_WR:
311 /* 3rd byte is byte count */
312 iproc_i2c_reg_write(&base->mstr_datawr, info->size);
313 num_data_bytes = info->size;
320 /* Copy actual data from caller, next. In general, for reads,
323 for (i = 0; num_data_bytes; --num_data_bytes, i++) {
324 /* For the last byte, set MASTER_WR_STATUS bit */
325 regval = (num_data_bytes == 1) ?
326 info->data[i] | CCB_SMB_MSTRWRSTS_MASK :
329 iproc_i2c_reg_write(&base->mstr_datawr, regval);
333 static int iproc_i2c_data_send(struct iproc_i2c *bus_prvdata,
335 struct iproc_xact_info *info)
337 struct iproc_i2c_regs *base = bus_prvdata->base;
341 /* Make sure the previous transaction completed */
342 rc = iproc_i2c_startbusy_wait(bus_prvdata);
345 pr_err("%s: Send: bus is busy, exiting\n", __func__);
349 /* Write transaction bytes to Tx FIFO */
350 iproc_i2c_write_trans_data(bus_prvdata, addr, info);
352 /* Program master command register (0x30) with protocol type and set
353 * start_busy_command bit to initiate the write transaction
355 regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
356 CCB_SMB_MSTRSTARTBUSYCMD_MASK;
358 iproc_i2c_reg_write(&base->mstr_cmd, regval);
360 /* Check for Master status */
361 regval = iproc_i2c_reg_read(&base->mstr_cmd);
362 while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
366 regval = iproc_i2c_reg_read(&base->mstr_cmd);
369 /* If start_busy bit cleared, check if there are any errors */
370 if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) {
371 /* start_busy bit cleared, check master_status field now */
372 regval &= CCB_SMB_MSTRSTS_MASK;
373 regval >>= CCB_SMB_MSTRSTS_SHIFT;
375 if (regval != MSTR_STS_XACT_SUCCESS) {
376 /* Error We can flush Tx FIFO here */
377 pr_err("%s: ERROR: Error in transaction %u, exiting\n",
386 static int iproc_i2c_data_recv(struct iproc_i2c *bus_prvdata,
388 struct iproc_xact_info *info,
389 unsigned int *num_bytes_read)
391 struct iproc_i2c_regs *base = bus_prvdata->base;
395 /* Make sure the previous transaction completed */
396 rc = iproc_i2c_startbusy_wait(bus_prvdata);
399 pr_err("%s: Receive: Bus is busy, exiting\n", __func__);
403 /* Program all transaction bytes into master Tx FIFO */
404 iproc_i2c_write_trans_data(bus_prvdata, addr, info);
406 /* Program master command register (0x30) with protocol type and set
407 * start_busy_command bit to initiate the write transaction
409 regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
410 CCB_SMB_MSTRSTARTBUSYCMD_MASK | info->size;
412 iproc_i2c_reg_write(&base->mstr_cmd, regval);
414 /* Check for Master status */
415 regval = iproc_i2c_reg_read(&base->mstr_cmd);
416 while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
420 regval = iproc_i2c_reg_read(&base->mstr_cmd);
423 /* If start_busy bit cleared, check if there are any errors */
424 if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) {
425 /* start_busy bit cleared, check master_status field now */
426 regval &= CCB_SMB_MSTRSTS_MASK;
427 regval >>= CCB_SMB_MSTRSTS_SHIFT;
429 if (regval != MSTR_STS_XACT_SUCCESS) {
430 /* We can flush Tx FIFO here */
431 pr_err("%s: Error in transaction %d, exiting\n",
437 /* Read received byte(s), after TX out address etc */
438 regval = iproc_i2c_reg_read(&base->mstr_datard);
440 /* For block read, protocol (hw) returns byte count,
443 if (info->smb_proto == SMBUS_PROT_BLK_RD) {
446 *num_bytes_read = regval & CCB_SMB_MSTRRDDATA_MASK;
448 /* Limit to reading a max of 32 bytes only; just a safeguard.
449 * If # bytes read is a number > 32, check transaction set up,
450 * and contact hw engg. Assumption: PEC is disabled
453 (i < *num_bytes_read) && (i < I2C_SMBUS_BLOCK_MAX);
455 /* Read Rx FIFO for data bytes */
456 regval = iproc_i2c_reg_read(&base->mstr_datard);
457 info->data[i] = regval & CCB_SMB_MSTRRDDATA_MASK;
461 *info->data = regval & CCB_SMB_MSTRRDDATA_MASK;
468 static int i2c_write_byte(struct iproc_i2c *bus_prvdata,
469 u8 devaddr, u8 regoffset, u8 value)
472 struct iproc_xact_info info;
477 info.command = (unsigned char)regoffset;
481 info.smb_proto = SMBUS_PROT_WR_BYTE;
482 /* Refer to i2c_smbus_write_byte params passed. */
483 rc = iproc_i2c_data_send(bus_prvdata, devaddr, &info);
486 pr_err("%s: %s error accessing device 0x%X\n",
487 __func__, "Write", devaddr);
494 int i2c_write(struct udevice *bus,
495 uchar chip, uint regaddr, int alen, uchar *buffer, int len)
497 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
502 pr_err("I2C write: address out of range\n");
507 pr_err("I2C write: Need offset addr and value\n");
511 /* buffer contains offset addr followed by value to be written */
516 for (i = 0; i < data_len; i++) {
517 if (i2c_write_byte(bus_prvdata, chip, regaddr + i, data[i])) {
518 pr_err("I2C write (%d): I/O error\n", i);
527 static int i2c_read_byte(struct iproc_i2c *bus_prvdata,
528 u8 devaddr, u8 regoffset, u8 *value)
531 struct iproc_xact_info info;
532 unsigned int num_bytes_read = 0;
537 info.command = (unsigned char)regoffset;
541 info.smb_proto = SMBUS_PROT_RD_BYTE;
542 /* Refer to i2c_smbus_read_byte for params passed. */
543 rc = iproc_i2c_data_recv(bus_prvdata, devaddr, &info, &num_bytes_read);
546 pr_err("%s: %s error accessing device 0x%X\n",
547 __func__, "Read", devaddr);
554 int i2c_read(struct udevice *bus,
555 uchar chip, uint addr, int alen, uchar *buffer, int len)
557 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
561 pr_err("I2C read: address out of range\n");
565 for (i = 0; i < len; i++) {
566 if (i2c_read_byte(bus_prvdata, chip, addr + i, &buffer[i])) {
567 pr_err("I2C read: I/O error\n");
576 static int iproc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
580 debug("%s: %d messages\n", __func__, nmsgs);
582 for (; nmsgs > 0; nmsgs--, msg++) {
583 if (msg->flags & I2C_M_RD)
584 ret = i2c_read(bus, msg->addr, 0, 0,
587 ret = i2c_write(bus, msg->addr, 0, 0,
594 static int iproc_i2c_probe_chip(struct udevice *bus, uint chip_addr,
597 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
598 struct iproc_i2c_regs *base = bus_prvdata->base;
601 debug("\n%s: Entering chip probe\n", __func__);
603 /* Init internal regs, disable intrs (and then clear intrs), set fifo
606 if (!bus_prvdata->i2c_init_done)
609 regval = (chip_addr << 1);
610 iproc_i2c_reg_write(&base->mstr_datawr, regval);
611 regval = ((SMBUS_PROT_QUICK_CMD << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
612 (1 << CCB_SMB_MSTRSTARTBUSYCMD_SHIFT));
613 iproc_i2c_reg_write(&base->mstr_cmd, regval);
617 regval = iproc_i2c_reg_read(&base->mstr_cmd);
618 regval &= CCB_SMB_MSTRSTARTBUSYCMD_MASK;
621 regval = iproc_i2c_reg_read(&base->mstr_cmd);
623 if ((regval & CCB_SMB_MSTRSTS_MASK) != 0)
626 iproc_dump_i2c_regs(bus_prvdata);
627 debug("%s: chip probe successful\n", __func__);
632 static int iproc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
634 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
636 bus_prvdata->bus_speed = speed;
637 return iproc_i2c_set_clk_freq(bus_prvdata);
641 * i2c_get_bus_speed - get i2c bus speed
643 * This function returns the speed of operation in Hz
645 int iproc_i2c_get_bus_speed(struct udevice *bus)
647 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
648 struct iproc_i2c_regs *base = bus_prvdata->base;
652 regval = iproc_i2c_reg_read(&base->timg_cfg);
653 regval = (regval & CCB_SMB_TIMGCFG_MODE400_MASK) >>
654 CCB_SMB_TIMGCFG_MODE400_SHIFT;
658 ret = I2C_SPEED_STANDARD_RATE;
661 ret = I2C_SPEED_FAST_RATE;
671 static int iproc_i2c_probe(struct udevice *bus)
673 return iproc_i2c_init(bus);
676 static int iproc_i2c_of_to_plat(struct udevice *bus)
678 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
679 int node = dev_of_offset(bus);
680 const void *blob = gd->fdt_blob;
682 bus_prvdata->base = map_physmem(dev_read_addr(bus),
686 bus_prvdata->bus_speed =
687 fdtdec_get_int(blob, node, "bus-frequency",
688 I2C_SPEED_STANDARD_RATE);
693 static const struct dm_i2c_ops iproc_i2c_ops = {
694 .xfer = iproc_i2c_xfer,
695 .probe_chip = iproc_i2c_probe_chip,
696 .set_bus_speed = iproc_i2c_set_bus_speed,
697 .get_bus_speed = iproc_i2c_get_bus_speed,
700 static const struct udevice_id iproc_i2c_ids[] = {
701 { .compatible = "brcm,iproc-i2c" },
705 U_BOOT_DRIVER(iproc_i2c) = {
708 .of_match = iproc_i2c_ids,
709 .of_to_plat = iproc_i2c_of_to_plat,
710 .probe = iproc_i2c_probe,
711 .priv_auto = sizeof(struct iproc_i2c),
712 .ops = &iproc_i2c_ops,
713 .flags = DM_FLAG_PRE_RELOC,