3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <gdsys_fpga.h>
12 DECLARE_GLOBAL_DATA_PTR;
15 I2CINT_ERROR_EV = 1 << 13,
16 I2CINT_TRANSMIT_EV = 1 << 14,
17 I2CINT_RECEIVE_EV = 1 << 15,
21 I2CMB_WRITE = 1 << 10,
22 I2CMB_2BYTE = 1 << 11,
23 I2CMB_HOLD_BUS = 1 << 13,
24 I2CMB_NATIVE = 2 << 14,
27 static int wait_for_int(bool read)
32 FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
33 while (!(val & (I2CINT_ERROR_EV
34 | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
37 printf("I2C timeout\n");
40 FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
43 return (val & I2CINT_ERROR_EV) ? 1 : 0;
46 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
51 FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV
52 | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
53 FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
59 val |= buffer[1] << 8;
60 FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val);
63 FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox,
65 | (read ? 0 : I2CMB_WRITE)
67 | ((len > 1) ? I2CMB_2BYTE : 0)
68 | (is_last ? 0 : I2CMB_HOLD_BUS));
70 if (wait_for_int(read))
74 FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val);
75 buffer[0] = val & 0xff;
83 static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus)
85 int shift = (alen-1) * 8;
88 int transfer = MIN(alen, 2);
90 bool is_last = alen <= transfer;
92 buf[0] = addr >> shift;
94 buf[1] = addr >> (shift - 8);
96 if (ihs_i2c_transfer(chip, buf, transfer, false,
97 hold_bus ? false : is_last))
107 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr,
108 int alen, uchar *buffer, int len, bool read)
113 if (ihs_i2c_address(chip, addr, alen, !read))
117 int transfer = MIN(len, 2);
119 if (ihs_i2c_transfer(chip, buffer, transfer, read,
132 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
134 #ifdef CONFIG_SYS_I2C_INIT_BOARD
136 * Call board specific i2c bus reset routine before accessing the
137 * environment, which might be in a chip on that bus. For details
138 * about this problem see doc/I2C_Edge_Conditions.
144 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
148 if (ihs_i2c_transfer(chip, buffer, 0, true, true))
154 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
155 int alen, uchar *buffer, int len)
157 return ihs_i2c_access(adap, chip, addr, alen, buffer, len, true);
160 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
161 int alen, uchar *buffer, int len)
163 return ihs_i2c_access(adap, chip, addr, alen, buffer, len, false);
166 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
169 if (speed != adap->speed)
175 * Register IHS i2c adapters
177 #ifdef CONFIG_SYS_I2C_IHS_CH0
178 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
179 ihs_i2c_read, ihs_i2c_write,
180 ihs_i2c_set_bus_speed,
181 CONFIG_SYS_I2C_IHS_SPEED_0,
182 CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
184 #ifdef CONFIG_SYS_I2C_IHS_CH1
185 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
186 ihs_i2c_read, ihs_i2c_write,
187 ihs_i2c_set_bus_speed,
188 CONFIG_SYS_I2C_IHS_SPEED_1,
189 CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
191 #ifdef CONFIG_SYS_I2C_IHS_CH2
192 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
193 ihs_i2c_read, ihs_i2c_write,
194 ihs_i2c_set_bus_speed,
195 CONFIG_SYS_I2C_IHS_SPEED_2,
196 CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
198 #ifdef CONFIG_SYS_I2C_IHS_CH3
199 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
200 ihs_i2c_read, ihs_i2c_write,
201 ihs_i2c_set_bus_speed,
202 CONFIG_SYS_I2C_IHS_SPEED_3,
203 CONFIG_SYS_I2C_IHS_SLAVE_3, 3)