drivers/i2c/ihs_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #ifdef CONFIG_DM_I2C
  10 #include <dm.h>
  11 #include <regmap.h>
  12 #else
  13 #include <gdsys_fpga.h>
  14 #endif
  15 #include <log.h>
  16 #include <asm/global_data.h>
  17 #include <asm/unaligned.h>
  18 #include <linux/bitops.h>
  19 #include <linux/delay.h>
  20
  21 #ifdef CONFIG_DM_I2C
  22 struct ihs_i2c_priv {
  23         uint speed;
  24         struct regmap *map;
  25 };
  26
  27 struct ihs_i2c_regs {
  28         u16 interrupt_status;
  29         u16 interrupt_enable_control;
  30         u16 write_mailbox_ext;
  31         u16 write_mailbox;
  32         u16 read_mailbox_ext;
  33         u16 read_mailbox;
  34 };
  35
  36 #define ihs_i2c_set(map, member, val) \
  37         regmap_set(map, struct ihs_i2c_regs, member, val)
  38
  39 #define ihs_i2c_get(map, member, valp) \
  40         regmap_get(map, struct ihs_i2c_regs, member, valp)
  41
  42 #else /* !CONFIG_DM_I2C */
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 #ifdef CONFIG_SYS_I2C_IHS_DUAL
  46
  47 #define I2C_SET_REG(fld, val) \
  48         do { \
  49                 if (I2C_ADAP_HWNR & 0x10) \
  50                         FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
  51                 else \
  52                         FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
  53         } while (0)
  54 #else
  55 #define I2C_SET_REG(fld, val) \
  56                 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
  57 #endif
  58
  59 #ifdef CONFIG_SYS_I2C_IHS_DUAL
  60 #define I2C_GET_REG(fld, val) \
  61         do {                                    \
  62                 if (I2C_ADAP_HWNR & 0x10) \
  63                         FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
  64                 else \
  65                         FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
  66         } while (0)
  67 #else
  68 #define I2C_GET_REG(fld, val) \
  69                 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
  70 #endif
  71 #endif /* CONFIG_DM_I2C */
  72
  73 enum {
  74         I2CINT_ERROR_EV = BIT(13),
  75         I2CINT_TRANSMIT_EV = BIT(14),
  76         I2CINT_RECEIVE_EV = BIT(15),
  77 };
  78
  79 enum {
  80         I2CMB_READ = 0 << 10,
  81         I2CMB_WRITE = 1 << 10,
  82         I2CMB_1BYTE = 0 << 11,
  83         I2CMB_2BYTE = 1 << 11,
  84         I2CMB_DONT_HOLD_BUS = 0 << 13,
  85         I2CMB_HOLD_BUS = 1 << 13,
  86         I2CMB_NATIVE = 2 << 14,
  87 };
  88
  89 enum {
  90         I2COP_WRITE = 0,
  91         I2COP_READ = 1,
  92 };
  93
  94 #ifdef CONFIG_DM_I2C
  95 static int wait_for_int(struct udevice *dev, int read)
  96 #else
  97 static int wait_for_int(bool read)
  98 #endif
  99 {
 100         u16 val;
 101         uint ctr = 0;
 102 #ifdef CONFIG_DM_I2C
 103         struct ihs_i2c_priv *priv = dev_get_priv(dev);
 104 #endif
 105
 106 #ifdef CONFIG_DM_I2C
 107         ihs_i2c_get(priv->map, interrupt_status, &val);
 108 #else
 109         I2C_GET_REG(interrupt_status, &val);
 110 #endif
 111         /* Wait until error or receive/transmit interrupt was raised */
 112         while (!(val & (I2CINT_ERROR_EV
 113                | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
 114                 udelay(10);
 115                 if (ctr++ > 5000) {
 116                         debug("%s: timed out\n", __func__);
 117                         return -ETIMEDOUT;
 118                 }
 119 #ifdef CONFIG_DM_I2C
 120                 ihs_i2c_get(priv->map, interrupt_status, &val);
 121 #else
 122                 I2C_GET_REG(interrupt_status, &val);
 123 #endif
 124         }
 125
 126         return (val & I2CINT_ERROR_EV) ? -EIO : 0;
 127 }
 128
 129 #ifdef CONFIG_DM_I2C
 130 static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
 131                             uchar *buffer, int len, int read, bool is_last)
 132 #else
 133 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
 134                             bool is_last)
 135 #endif
 136 {
 137         u16 val;
 138         u16 data;
 139         int res;
 140 #ifdef CONFIG_DM_I2C
 141         struct ihs_i2c_priv *priv = dev_get_priv(dev);
 142 #endif
 143
 144         /* Clear interrupt status */
 145         data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
 146 #ifdef CONFIG_DM_I2C
 147         ihs_i2c_set(priv->map, interrupt_status, data);
 148         ihs_i2c_get(priv->map, interrupt_status, &val);
 149 #else
 150         I2C_SET_REG(interrupt_status, data);
 151         I2C_GET_REG(interrupt_status, &val);
 152 #endif
 153
 154         /* If we want to write and have data, write the bytes to the mailbox */
 155         if (!read && len) {
 156                 val = buffer[0];
 157
 158                 if (len > 1)
 159                         val |= buffer[1] << 8;
 160 #ifdef CONFIG_DM_I2C
 161                 ihs_i2c_set(priv->map, write_mailbox_ext, val);
 162 #else
 163                 I2C_SET_REG(write_mailbox_ext, val);
 164 #endif
 165         }
 166
 167         data = I2CMB_NATIVE
 168                | (read ? 0 : I2CMB_WRITE)
 169                | (chip << 1)
 170                | ((len > 1) ? I2CMB_2BYTE : 0)
 171                | (is_last ? 0 : I2CMB_HOLD_BUS);
 172
 173 #ifdef CONFIG_DM_I2C
 174         ihs_i2c_set(priv->map, write_mailbox, data);
 175 #else
 176         I2C_SET_REG(write_mailbox, data);
 177 #endif
 178
 179 #ifdef CONFIG_DM_I2C
 180         res = wait_for_int(dev, read);
 181 #else
 182         res = wait_for_int(read);
 183 #endif
 184         if (res) {
 185                 if (res == -ETIMEDOUT)
 186                         debug("%s: time out while waiting for event\n", __func__);
 187
 188                 return res;
 189         }
 190
 191         /* If we want to read, get the bytes from the mailbox */
 192         if (read) {
 193 #ifdef CONFIG_DM_I2C
 194                 ihs_i2c_get(priv->map, read_mailbox_ext, &val);
 195 #else
 196                 I2C_GET_REG(read_mailbox_ext, &val);
 197 #endif
 198                 buffer[0] = val & 0xff;
 199                 if (len > 1)
 200                         buffer[1] = val >> 8;
 201         }
 202
 203         return 0;
 204 }
 205
 206 #ifdef CONFIG_DM_I2C
 207 static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
 208 #else
 209 static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
 210                                int read)
 211 #endif
 212 {
 213         int res;
 214
 215         while (len) {
 216                 int transfer = min(len, 2);
 217                 bool is_last = len <= transfer;
 218
 219 #ifdef CONFIG_DM_I2C
 220                 res = ihs_i2c_transfer(dev, chip, data, transfer, read,
 221                                        hold_bus ? false : is_last);
 222 #else
 223                 res = ihs_i2c_transfer(chip, data, transfer, read,
 224                                        hold_bus ? false : is_last);
 225 #endif
 226                 if (res)
 227                         return res;
 228
 229                 data += transfer;
 230                 len -= transfer;
 231         }
 232
 233         return 0;
 234 }
 235
 236 #ifdef CONFIG_DM_I2C
 237 static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
 238                            bool hold_bus)
 239 #else
 240 static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
 241 #endif
 242 {
 243 #ifdef CONFIG_DM_I2C
 244         return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
 245 #else
 246         return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
 247 #endif
 248 }
 249
 250 #ifdef CONFIG_DM_I2C
 251 static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
 252                           int alen, uchar *buffer, int len, int read)
 253 #else
 254 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
 255                           int alen, uchar *buffer, int len, int read)
 256 #endif
 257 {
 258         int res;
 259
 260         /* Don't hold the bus if length of data to send/receive is zero */
 261         if (len <= 0)
 262                 return -EINVAL;
 263
 264 #ifdef CONFIG_DM_I2C
 265         res = ihs_i2c_address(dev, chip, addr, alen, len);
 266 #else
 267         res = ihs_i2c_address(chip, addr, alen, len);
 268 #endif
 269         if (res)
 270                 return res;
 271
 272 #ifdef CONFIG_DM_I2C
 273         return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
 274 #else
 275         return ihs_i2c_send_buffer(chip, buffer, len, false, read);
 276 #endif
 277 }
 278
 279 #ifdef CONFIG_DM_I2C
 280
 281 int ihs_i2c_probe(struct udevice *bus)
 282 {
 283         struct ihs_i2c_priv *priv = dev_get_priv(bus);
 284
 285         regmap_init_mem(dev_ofnode(bus), &priv->map);
 286
 287         return 0;
 288 }
 289
 290 static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
 291 {
 292         struct ihs_i2c_priv *priv = dev_get_priv(bus);
 293
 294         if (speed != priv->speed && priv->speed != 0)
 295                 return -EINVAL;
 296
 297         priv->speed = speed;
 298
 299         return 0;
 300 }
 301
 302 static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 303 {
 304         struct i2c_msg *dmsg, *omsg, dummy;
 305
 306         memset(&dummy, 0, sizeof(struct i2c_msg));
 307
 308         /* We expect either two messages (one with an offset and one with the
 309          * actucal data) or one message (just data)
 310          */
 311         if (nmsgs > 2 || nmsgs == 0) {
 312                 debug("%s: Only one or two messages are supported\n", __func__);
 313                 return -ENOTSUPP;
 314         }
 315
 316         omsg = nmsgs == 1 ? &dummy : msg;
 317         dmsg = nmsgs == 1 ? msg : msg + 1;
 318
 319         if (dmsg->flags & I2C_M_RD)
 320                 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
 321                                       omsg->len, dmsg->buf, dmsg->len,
 322                                       I2COP_READ);
 323         else
 324                 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
 325                                       omsg->len, dmsg->buf, dmsg->len,
 326                                       I2COP_WRITE);
 327 }
 328
 329 static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 330                               u32 chip_flags)
 331 {
 332         uchar buffer[2];
 333         int res;
 334
 335         res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true);
 336         if (res)
 337                 return res;
 338
 339         return 0;
 340 }
 341
 342 static const struct dm_i2c_ops ihs_i2c_ops = {
 343         .xfer           = ihs_i2c_xfer,
 344         .probe_chip     = ihs_i2c_probe_chip,
 345         .set_bus_speed  = ihs_i2c_set_bus_speed,
 346 };
 347
 348 static const struct udevice_id ihs_i2c_ids[] = {
 349         { .compatible = "gdsys,ihs_i2cmaster", },
 350         { /* sentinel */ }
 351 };
 352
 353 U_BOOT_DRIVER(i2c_ihs) = {
 354         .name = "i2c_ihs",
 355         .id = UCLASS_I2C,
 356         .of_match = ihs_i2c_ids,
 357         .probe = ihs_i2c_probe,
 358         .priv_auto      = sizeof(struct ihs_i2c_priv),
 359         .ops = &ihs_i2c_ops,
 360 };
 361
 362 #else /* CONFIG_DM_I2C */
 363
 364 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 365 {
 366 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 367         /*
 368          * Call board specific i2c bus reset routine before accessing the
 369          * environment, which might be in a chip on that bus. For details
 370          * about this problem see doc/I2C_Edge_Conditions.
 371          */
 372         i2c_init_board();
 373 #endif
 374 }
 375
 376 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
 377 {
 378         uchar buffer[2];
 379         int res;
 380
 381         res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
 382         if (res)
 383                 return res;
 384
 385         return 0;
 386 }
 387
 388 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 389                         int alen, uchar *buffer, int len)
 390 {
 391         u8 addr_bytes[4];
 392
 393         put_unaligned_le32(addr, addr_bytes);
 394
 395         return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
 396                               I2COP_READ);
 397 }
 398
 399 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 400                          int alen, uchar *buffer, int len)
 401 {
 402         u8 addr_bytes[4];
 403
 404         put_unaligned_le32(addr, addr_bytes);
 405
 406         return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
 407                               I2COP_WRITE);
 408 }
 409
 410 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
 411                                           unsigned int speed)
 412 {
 413         if (speed != adap->speed)
 414                 return -EINVAL;
 415         return speed;
 416 }
 417
 418 /*
 419  * Register IHS i2c adapters
 420  */
 421 #ifdef CONFIG_SYS_I2C_IHS_CH0
 422 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
 423                          ihs_i2c_read, ihs_i2c_write,
 424                          ihs_i2c_set_bus_speed,
 425                          CONFIG_SYS_I2C_IHS_SPEED_0,
 426                          CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
 427 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 428 U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
 429                          ihs_i2c_read, ihs_i2c_write,
 430                          ihs_i2c_set_bus_speed,
 431                          CONFIG_SYS_I2C_IHS_SPEED_0_1,
 432                          CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
 433 #endif
 434 #endif
 435 #ifdef CONFIG_SYS_I2C_IHS_CH1
 436 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
 437                          ihs_i2c_read, ihs_i2c_write,
 438                          ihs_i2c_set_bus_speed,
 439                          CONFIG_SYS_I2C_IHS_SPEED_1,
 440                          CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
 441 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 442 U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
 443                          ihs_i2c_read, ihs_i2c_write,
 444                          ihs_i2c_set_bus_speed,
 445                          CONFIG_SYS_I2C_IHS_SPEED_1_1,
 446                          CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
 447 #endif
 448 #endif
 449 #ifdef CONFIG_SYS_I2C_IHS_CH2
 450 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
 451                          ihs_i2c_read, ihs_i2c_write,
 452                          ihs_i2c_set_bus_speed,
 453                          CONFIG_SYS_I2C_IHS_SPEED_2,
 454                          CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
 455 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 456 U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
 457                          ihs_i2c_read, ihs_i2c_write,
 458                          ihs_i2c_set_bus_speed,
 459                          CONFIG_SYS_I2C_IHS_SPEED_2_1,
 460                          CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
 461 #endif
 462 #endif
 463 #ifdef CONFIG_SYS_I2C_IHS_CH3
 464 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
 465                          ihs_i2c_read, ihs_i2c_write,
 466                          ihs_i2c_set_bus_speed,
 467                          CONFIG_SYS_I2C_IHS_SPEED_3,
 468                          CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
 469 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 470 U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
 471                          ihs_i2c_read, ihs_i2c_write,
 472                          ihs_i2c_set_bus_speed,
 473                          CONFIG_SYS_I2C_IHS_SPEED_3_1,
 474                          CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
 475 #endif
 476 #endif
 477 #endif /* CONFIG_DM_I2C */