1 // SPDX-License-Identifier: GPL-2.0+
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
13 #include <gdsys_fpga.h>
16 #include <asm/unaligned.h>
17 #include <linux/delay.h>
27 u16 interrupt_enable_control;
28 u16 write_mailbox_ext;
34 #define ihs_i2c_set(map, member, val) \
35 regmap_set(map, struct ihs_i2c_regs, member, val)
37 #define ihs_i2c_get(map, member, valp) \
38 regmap_get(map, struct ihs_i2c_regs, member, valp)
40 #else /* !CONFIG_DM_I2C */
41 DECLARE_GLOBAL_DATA_PTR;
43 #ifdef CONFIG_SYS_I2C_IHS_DUAL
45 #define I2C_SET_REG(fld, val) \
47 if (I2C_ADAP_HWNR & 0x10) \
48 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
50 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
53 #define I2C_SET_REG(fld, val) \
54 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
57 #ifdef CONFIG_SYS_I2C_IHS_DUAL
58 #define I2C_GET_REG(fld, val) \
60 if (I2C_ADAP_HWNR & 0x10) \
61 FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
63 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
66 #define I2C_GET_REG(fld, val) \
67 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
69 #endif /* CONFIG_DM_I2C */
72 I2CINT_ERROR_EV = BIT(13),
73 I2CINT_TRANSMIT_EV = BIT(14),
74 I2CINT_RECEIVE_EV = BIT(15),
79 I2CMB_WRITE = 1 << 10,
80 I2CMB_1BYTE = 0 << 11,
81 I2CMB_2BYTE = 1 << 11,
82 I2CMB_DONT_HOLD_BUS = 0 << 13,
83 I2CMB_HOLD_BUS = 1 << 13,
84 I2CMB_NATIVE = 2 << 14,
93 static int wait_for_int(struct udevice *dev, int read)
95 static int wait_for_int(bool read)
101 struct ihs_i2c_priv *priv = dev_get_priv(dev);
105 ihs_i2c_get(priv->map, interrupt_status, &val);
107 I2C_GET_REG(interrupt_status, &val);
109 /* Wait until error or receive/transmit interrupt was raised */
110 while (!(val & (I2CINT_ERROR_EV
111 | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
114 debug("%s: timed out\n", __func__);
118 ihs_i2c_get(priv->map, interrupt_status, &val);
120 I2C_GET_REG(interrupt_status, &val);
124 return (val & I2CINT_ERROR_EV) ? -EIO : 0;
128 static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
129 uchar *buffer, int len, int read, bool is_last)
131 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
139 struct ihs_i2c_priv *priv = dev_get_priv(dev);
142 /* Clear interrupt status */
143 data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
145 ihs_i2c_set(priv->map, interrupt_status, data);
146 ihs_i2c_get(priv->map, interrupt_status, &val);
148 I2C_SET_REG(interrupt_status, data);
149 I2C_GET_REG(interrupt_status, &val);
152 /* If we want to write and have data, write the bytes to the mailbox */
157 val |= buffer[1] << 8;
159 ihs_i2c_set(priv->map, write_mailbox_ext, val);
161 I2C_SET_REG(write_mailbox_ext, val);
166 | (read ? 0 : I2CMB_WRITE)
168 | ((len > 1) ? I2CMB_2BYTE : 0)
169 | (is_last ? 0 : I2CMB_HOLD_BUS);
172 ihs_i2c_set(priv->map, write_mailbox, data);
174 I2C_SET_REG(write_mailbox, data);
178 res = wait_for_int(dev, read);
180 res = wait_for_int(read);
183 if (res == -ETIMEDOUT)
184 debug("%s: time out while waiting for event\n", __func__);
189 /* If we want to read, get the bytes from the mailbox */
192 ihs_i2c_get(priv->map, read_mailbox_ext, &val);
194 I2C_GET_REG(read_mailbox_ext, &val);
196 buffer[0] = val & 0xff;
198 buffer[1] = val >> 8;
205 static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
207 static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
214 int transfer = min(len, 2);
215 bool is_last = len <= transfer;
218 res = ihs_i2c_transfer(dev, chip, data, transfer, read,
219 hold_bus ? false : is_last);
221 res = ihs_i2c_transfer(chip, data, transfer, read,
222 hold_bus ? false : is_last);
235 static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
238 static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
242 return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
244 return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
249 static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
250 int alen, uchar *buffer, int len, int read)
252 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
253 int alen, uchar *buffer, int len, int read)
258 /* Don't hold the bus if length of data to send/receive is zero */
263 res = ihs_i2c_address(dev, chip, addr, alen, len);
265 res = ihs_i2c_address(chip, addr, alen, len);
271 return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
273 return ihs_i2c_send_buffer(chip, buffer, len, false, read);
279 int ihs_i2c_probe(struct udevice *bus)
281 struct ihs_i2c_priv *priv = dev_get_priv(bus);
283 regmap_init_mem(dev_ofnode(bus), &priv->map);
288 static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
290 struct ihs_i2c_priv *priv = dev_get_priv(bus);
292 if (speed != priv->speed && priv->speed != 0)
300 static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
302 struct i2c_msg *dmsg, *omsg, dummy;
304 memset(&dummy, 0, sizeof(struct i2c_msg));
306 /* We expect either two messages (one with an offset and one with the
307 * actucal data) or one message (just data)
309 if (nmsgs > 2 || nmsgs == 0) {
310 debug("%s: Only one or two messages are supported\n", __func__);
314 omsg = nmsgs == 1 ? &dummy : msg;
315 dmsg = nmsgs == 1 ? msg : msg + 1;
317 if (dmsg->flags & I2C_M_RD)
318 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
319 omsg->len, dmsg->buf, dmsg->len,
322 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
323 omsg->len, dmsg->buf, dmsg->len,
327 static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
333 res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true);
340 static const struct dm_i2c_ops ihs_i2c_ops = {
341 .xfer = ihs_i2c_xfer,
342 .probe_chip = ihs_i2c_probe_chip,
343 .set_bus_speed = ihs_i2c_set_bus_speed,
346 static const struct udevice_id ihs_i2c_ids[] = {
347 { .compatible = "gdsys,ihs_i2cmaster", },
351 U_BOOT_DRIVER(i2c_ihs) = {
354 .of_match = ihs_i2c_ids,
355 .probe = ihs_i2c_probe,
356 .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
360 #else /* CONFIG_DM_I2C */
362 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
364 #ifdef CONFIG_SYS_I2C_INIT_BOARD
366 * Call board specific i2c bus reset routine before accessing the
367 * environment, which might be in a chip on that bus. For details
368 * about this problem see doc/I2C_Edge_Conditions.
374 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
379 res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
386 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
387 int alen, uchar *buffer, int len)
391 put_unaligned_le32(addr, addr_bytes);
393 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
397 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
398 int alen, uchar *buffer, int len)
402 put_unaligned_le32(addr, addr_bytes);
404 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
408 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
411 if (speed != adap->speed)
417 * Register IHS i2c adapters
419 #ifdef CONFIG_SYS_I2C_IHS_CH0
420 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
421 ihs_i2c_read, ihs_i2c_write,
422 ihs_i2c_set_bus_speed,
423 CONFIG_SYS_I2C_IHS_SPEED_0,
424 CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
425 #ifdef CONFIG_SYS_I2C_IHS_DUAL
426 U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
427 ihs_i2c_read, ihs_i2c_write,
428 ihs_i2c_set_bus_speed,
429 CONFIG_SYS_I2C_IHS_SPEED_0_1,
430 CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
433 #ifdef CONFIG_SYS_I2C_IHS_CH1
434 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
435 ihs_i2c_read, ihs_i2c_write,
436 ihs_i2c_set_bus_speed,
437 CONFIG_SYS_I2C_IHS_SPEED_1,
438 CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
439 #ifdef CONFIG_SYS_I2C_IHS_DUAL
440 U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
441 ihs_i2c_read, ihs_i2c_write,
442 ihs_i2c_set_bus_speed,
443 CONFIG_SYS_I2C_IHS_SPEED_1_1,
444 CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
447 #ifdef CONFIG_SYS_I2C_IHS_CH2
448 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
449 ihs_i2c_read, ihs_i2c_write,
450 ihs_i2c_set_bus_speed,
451 CONFIG_SYS_I2C_IHS_SPEED_2,
452 CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
453 #ifdef CONFIG_SYS_I2C_IHS_DUAL
454 U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
455 ihs_i2c_read, ihs_i2c_write,
456 ihs_i2c_set_bus_speed,
457 CONFIG_SYS_I2C_IHS_SPEED_2_1,
458 CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
461 #ifdef CONFIG_SYS_I2C_IHS_CH3
462 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
463 ihs_i2c_read, ihs_i2c_write,
464 ihs_i2c_set_bus_speed,
465 CONFIG_SYS_I2C_IHS_SPEED_3,
466 CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
467 #ifdef CONFIG_SYS_I2C_IHS_DUAL
468 U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
469 ihs_i2c_read, ihs_i2c_write,
470 ihs_i2c_set_bus_speed,
471 CONFIG_SYS_I2C_IHS_SPEED_3_1,
472 CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
475 #endif /* CONFIG_DM_I2C */