1 // SPDX-License-Identifier: GPL-2.0+
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 #include "../misc/gdsys_soc.h"
14 #include <gdsys_fpga.h>
16 #include <asm/unaligned.h>
25 REG_INTERRUPT_STATUS = 0x00,
26 REG_INTERRUPT_ENABLE_CONTROL = 0x02,
27 REG_WRITE_MAILBOX_EXT = 0x04,
28 REG_WRITE_MAILBOX = 0x06,
29 REG_READ_MAILBOX_EXT = 0x08,
30 REG_READ_MAILBOX = 0x0A,
33 #else /* !CONFIG_DM_I2C */
34 DECLARE_GLOBAL_DATA_PTR;
36 #ifdef CONFIG_SYS_I2C_IHS_DUAL
38 #define I2C_SET_REG(fld, val) \
40 if (I2C_ADAP_HWNR & 0x10) \
41 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
43 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
46 #define I2C_SET_REG(fld, val) \
47 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
50 #ifdef CONFIG_SYS_I2C_IHS_DUAL
51 #define I2C_GET_REG(fld, val) \
53 if (I2C_ADAP_HWNR & 0x10) \
54 FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
56 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
59 #define I2C_GET_REG(fld, val) \
60 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
62 #endif /* CONFIG_DM_I2C */
65 I2CINT_ERROR_EV = BIT(13),
66 I2CINT_TRANSMIT_EV = BIT(14),
67 I2CINT_RECEIVE_EV = BIT(15),
72 I2CMB_WRITE = 1 << 10,
73 I2CMB_1BYTE = 0 << 11,
74 I2CMB_2BYTE = 1 << 11,
75 I2CMB_DONT_HOLD_BUS = 0 << 13,
76 I2CMB_HOLD_BUS = 1 << 13,
77 I2CMB_NATIVE = 2 << 14,
86 static int wait_for_int(struct udevice *dev, int read)
88 static int wait_for_int(bool read)
94 struct ihs_i2c_priv *priv = dev_get_priv(dev);
97 gdsys_soc_get_fpga(dev, &fpga);
101 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
104 I2C_GET_REG(interrupt_status, &val);
106 /* Wait until error or receive/transmit interrupt was raised */
107 while (!(val & (I2CINT_ERROR_EV
108 | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
113 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
116 I2C_GET_REG(interrupt_status, &val);
120 return (val & I2CINT_ERROR_EV) ? 1 : 0;
124 static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
125 uchar *buffer, int len, int read, bool is_last)
127 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
134 struct ihs_i2c_priv *priv = dev_get_priv(dev);
135 struct udevice *fpga;
137 gdsys_soc_get_fpga(dev, &fpga);
140 /* Clear interrupt status */
141 data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
143 fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data,
145 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
148 I2C_SET_REG(interrupt_status, data);
149 I2C_GET_REG(interrupt_status, &val);
152 /* If we want to write and have data, write the bytes to the mailbox */
157 val |= buffer[1] << 8;
159 fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val,
162 I2C_SET_REG(write_mailbox_ext, val);
167 | (read ? 0 : I2CMB_WRITE)
169 | ((len > 1) ? I2CMB_2BYTE : 0)
170 | (is_last ? 0 : I2CMB_HOLD_BUS);
173 fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data,
176 I2C_SET_REG(write_mailbox, data);
180 if (wait_for_int(dev, read))
182 if (wait_for_int(read))
186 /* If we want to read, get the bytes from the mailbox */
189 fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val,
192 I2C_GET_REG(read_mailbox_ext, &val);
194 buffer[0] = val & 0xff;
196 buffer[1] = val >> 8;
203 static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
205 static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
210 int transfer = min(len, 2);
211 bool is_last = len <= transfer;
214 if (ihs_i2c_transfer(dev, chip, data, transfer, read,
215 hold_bus ? false : is_last))
218 if (ihs_i2c_transfer(chip, data, transfer, read,
219 hold_bus ? false : is_last))
231 static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
234 static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
238 return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
240 return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
245 static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
246 int alen, uchar *buffer, int len, int read)
248 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
249 int alen, uchar *buffer, int len, int read)
252 /* Don't hold the bus if length of data to send/receive is zero */
254 if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len))
257 if (len <= 0 || ihs_i2c_address(chip, addr, alen, len))
262 return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
264 return ihs_i2c_send_buffer(chip, buffer, len, false, read);
270 int ihs_i2c_probe(struct udevice *bus)
272 struct ihs_i2c_priv *priv = dev_get_priv(bus);
275 addr = dev_read_u32_default(bus, "reg", -1);
282 static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
284 struct ihs_i2c_priv *priv = dev_get_priv(bus);
286 if (speed != priv->speed && priv->speed != 0)
294 static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
296 struct i2c_msg *dmsg, *omsg, dummy;
298 memset(&dummy, 0, sizeof(struct i2c_msg));
300 /* We expect either two messages (one with an offset and one with the
301 * actucal data) or one message (just data)
303 if (nmsgs > 2 || nmsgs == 0) {
304 debug("%s: Only one or two messages are supported.", __func__);
308 omsg = nmsgs == 1 ? &dummy : msg;
309 dmsg = nmsgs == 1 ? msg : msg + 1;
311 if (dmsg->flags & I2C_M_RD)
312 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
313 omsg->len, dmsg->buf, dmsg->len,
316 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
317 omsg->len, dmsg->buf, dmsg->len,
321 static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
326 if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true))
332 static const struct dm_i2c_ops ihs_i2c_ops = {
333 .xfer = ihs_i2c_xfer,
334 .probe_chip = ihs_i2c_probe_chip,
335 .set_bus_speed = ihs_i2c_set_bus_speed,
338 static const struct udevice_id ihs_i2c_ids[] = {
339 { .compatible = "gdsys,ihs_i2cmaster", },
343 U_BOOT_DRIVER(i2c_ihs) = {
346 .of_match = ihs_i2c_ids,
347 .probe = ihs_i2c_probe,
348 .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
352 #else /* CONFIG_DM_I2C */
354 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
356 #ifdef CONFIG_SYS_I2C_INIT_BOARD
358 * Call board specific i2c bus reset routine before accessing the
359 * environment, which might be in a chip on that bus. For details
360 * about this problem see doc/I2C_Edge_Conditions.
366 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
370 if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true))
376 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
377 int alen, uchar *buffer, int len)
381 put_unaligned_le32(addr, addr_bytes);
383 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
387 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
388 int alen, uchar *buffer, int len)
392 put_unaligned_le32(addr, addr_bytes);
394 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
398 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
401 if (speed != adap->speed)
407 * Register IHS i2c adapters
409 #ifdef CONFIG_SYS_I2C_IHS_CH0
410 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
411 ihs_i2c_read, ihs_i2c_write,
412 ihs_i2c_set_bus_speed,
413 CONFIG_SYS_I2C_IHS_SPEED_0,
414 CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
415 #ifdef CONFIG_SYS_I2C_IHS_DUAL
416 U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
417 ihs_i2c_read, ihs_i2c_write,
418 ihs_i2c_set_bus_speed,
419 CONFIG_SYS_I2C_IHS_SPEED_0_1,
420 CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
423 #ifdef CONFIG_SYS_I2C_IHS_CH1
424 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
425 ihs_i2c_read, ihs_i2c_write,
426 ihs_i2c_set_bus_speed,
427 CONFIG_SYS_I2C_IHS_SPEED_1,
428 CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
429 #ifdef CONFIG_SYS_I2C_IHS_DUAL
430 U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
431 ihs_i2c_read, ihs_i2c_write,
432 ihs_i2c_set_bus_speed,
433 CONFIG_SYS_I2C_IHS_SPEED_1_1,
434 CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
437 #ifdef CONFIG_SYS_I2C_IHS_CH2
438 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
439 ihs_i2c_read, ihs_i2c_write,
440 ihs_i2c_set_bus_speed,
441 CONFIG_SYS_I2C_IHS_SPEED_2,
442 CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
443 #ifdef CONFIG_SYS_I2C_IHS_DUAL
444 U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
445 ihs_i2c_read, ihs_i2c_write,
446 ihs_i2c_set_bus_speed,
447 CONFIG_SYS_I2C_IHS_SPEED_2_1,
448 CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
451 #ifdef CONFIG_SYS_I2C_IHS_CH3
452 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
453 ihs_i2c_read, ihs_i2c_write,
454 ihs_i2c_set_bus_speed,
455 CONFIG_SYS_I2C_IHS_SPEED_3,
456 CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
457 #ifdef CONFIG_SYS_I2C_IHS_DUAL
458 U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
459 ihs_i2c_read, ihs_i2c_write,
460 ihs_i2c_set_bus_speed,
461 CONFIG_SYS_I2C_IHS_SPEED_3_1,
462 CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
465 #endif /* CONFIG_DM_I2C */