1 // SPDX-License-Identifier: GPL-2.0+
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
9 #if CONFIG_IS_ENABLED(DM_I2C)
13 #include <gdsys_fpga.h>
16 #include <asm/global_data.h>
17 #include <asm/unaligned.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
21 #if CONFIG_IS_ENABLED(DM_I2C)
29 u16 interrupt_enable_control;
30 u16 write_mailbox_ext;
36 #define ihs_i2c_set(map, member, val) \
37 regmap_set(map, struct ihs_i2c_regs, member, val)
39 #define ihs_i2c_get(map, member, valp) \
40 regmap_get(map, struct ihs_i2c_regs, member, valp)
42 #else /* !CONFIG_DM_I2C */
43 DECLARE_GLOBAL_DATA_PTR;
45 #ifdef CONFIG_SYS_I2C_IHS_DUAL
47 #define I2C_SET_REG(fld, val) \
49 if (I2C_ADAP_HWNR & 0x10) \
50 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
52 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
55 #define I2C_SET_REG(fld, val) \
56 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
59 #ifdef CONFIG_SYS_I2C_IHS_DUAL
60 #define I2C_GET_REG(fld, val) \
62 if (I2C_ADAP_HWNR & 0x10) \
63 FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
65 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
68 #define I2C_GET_REG(fld, val) \
69 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
71 #endif /* CONFIG_DM_I2C */
74 I2CINT_ERROR_EV = BIT(13),
75 I2CINT_TRANSMIT_EV = BIT(14),
76 I2CINT_RECEIVE_EV = BIT(15),
81 I2CMB_WRITE = 1 << 10,
82 I2CMB_1BYTE = 0 << 11,
83 I2CMB_2BYTE = 1 << 11,
84 I2CMB_DONT_HOLD_BUS = 0 << 13,
85 I2CMB_HOLD_BUS = 1 << 13,
86 I2CMB_NATIVE = 2 << 14,
94 #if CONFIG_IS_ENABLED(DM_I2C)
95 static int wait_for_int(struct udevice *dev, int read)
97 static int wait_for_int(bool read)
102 #if CONFIG_IS_ENABLED(DM_I2C)
103 struct ihs_i2c_priv *priv = dev_get_priv(dev);
106 #if CONFIG_IS_ENABLED(DM_I2C)
107 ihs_i2c_get(priv->map, interrupt_status, &val);
109 I2C_GET_REG(interrupt_status, &val);
111 /* Wait until error or receive/transmit interrupt was raised */
112 while (!(val & (I2CINT_ERROR_EV
113 | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
116 debug("%s: timed out\n", __func__);
119 #if CONFIG_IS_ENABLED(DM_I2C)
120 ihs_i2c_get(priv->map, interrupt_status, &val);
122 I2C_GET_REG(interrupt_status, &val);
126 return (val & I2CINT_ERROR_EV) ? -EIO : 0;
129 #if CONFIG_IS_ENABLED(DM_I2C)
130 static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
131 uchar *buffer, int len, int read, bool is_last)
133 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
140 #if CONFIG_IS_ENABLED(DM_I2C)
141 struct ihs_i2c_priv *priv = dev_get_priv(dev);
144 /* Clear interrupt status */
145 data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
146 #if CONFIG_IS_ENABLED(DM_I2C)
147 ihs_i2c_set(priv->map, interrupt_status, data);
148 ihs_i2c_get(priv->map, interrupt_status, &val);
150 I2C_SET_REG(interrupt_status, data);
151 I2C_GET_REG(interrupt_status, &val);
154 /* If we want to write and have data, write the bytes to the mailbox */
159 val |= buffer[1] << 8;
160 #if CONFIG_IS_ENABLED(DM_I2C)
161 ihs_i2c_set(priv->map, write_mailbox_ext, val);
163 I2C_SET_REG(write_mailbox_ext, val);
168 | (read ? 0 : I2CMB_WRITE)
170 | ((len > 1) ? I2CMB_2BYTE : 0)
171 | (is_last ? 0 : I2CMB_HOLD_BUS);
173 #if CONFIG_IS_ENABLED(DM_I2C)
174 ihs_i2c_set(priv->map, write_mailbox, data);
176 I2C_SET_REG(write_mailbox, data);
179 #if CONFIG_IS_ENABLED(DM_I2C)
180 res = wait_for_int(dev, read);
182 res = wait_for_int(read);
185 if (res == -ETIMEDOUT)
186 debug("%s: time out while waiting for event\n", __func__);
191 /* If we want to read, get the bytes from the mailbox */
193 #if CONFIG_IS_ENABLED(DM_I2C)
194 ihs_i2c_get(priv->map, read_mailbox_ext, &val);
196 I2C_GET_REG(read_mailbox_ext, &val);
198 buffer[0] = val & 0xff;
200 buffer[1] = val >> 8;
206 #if CONFIG_IS_ENABLED(DM_I2C)
207 static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
209 static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
216 int transfer = min(len, 2);
217 bool is_last = len <= transfer;
219 #if CONFIG_IS_ENABLED(DM_I2C)
220 res = ihs_i2c_transfer(dev, chip, data, transfer, read,
221 hold_bus ? false : is_last);
223 res = ihs_i2c_transfer(chip, data, transfer, read,
224 hold_bus ? false : is_last);
236 #if CONFIG_IS_ENABLED(DM_I2C)
237 static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
240 static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
243 #if CONFIG_IS_ENABLED(DM_I2C)
244 return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
246 return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
250 #if CONFIG_IS_ENABLED(DM_I2C)
251 static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
252 int alen, uchar *buffer, int len, int read)
254 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
255 int alen, uchar *buffer, int len, int read)
260 /* Don't hold the bus if length of data to send/receive is zero */
264 #if CONFIG_IS_ENABLED(DM_I2C)
265 res = ihs_i2c_address(dev, chip, addr, alen, len);
267 res = ihs_i2c_address(chip, addr, alen, len);
272 #if CONFIG_IS_ENABLED(DM_I2C)
273 return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
275 return ihs_i2c_send_buffer(chip, buffer, len, false, read);
279 #if CONFIG_IS_ENABLED(DM_I2C)
281 int ihs_i2c_probe(struct udevice *bus)
283 struct ihs_i2c_priv *priv = dev_get_priv(bus);
285 regmap_init_mem(dev_ofnode(bus), &priv->map);
290 static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
292 struct ihs_i2c_priv *priv = dev_get_priv(bus);
294 if (speed != priv->speed && priv->speed != 0)
302 static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
304 struct i2c_msg *dmsg, *omsg, dummy;
306 memset(&dummy, 0, sizeof(struct i2c_msg));
308 /* We expect either two messages (one with an offset and one with the
309 * actucal data) or one message (just data)
311 if (nmsgs > 2 || nmsgs == 0) {
312 debug("%s: Only one or two messages are supported\n", __func__);
316 omsg = nmsgs == 1 ? &dummy : msg;
317 dmsg = nmsgs == 1 ? msg : msg + 1;
319 if (dmsg->flags & I2C_M_RD)
320 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
321 omsg->len, dmsg->buf, dmsg->len,
324 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
325 omsg->len, dmsg->buf, dmsg->len,
329 static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
335 res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true);
342 static const struct dm_i2c_ops ihs_i2c_ops = {
343 .xfer = ihs_i2c_xfer,
344 .probe_chip = ihs_i2c_probe_chip,
345 .set_bus_speed = ihs_i2c_set_bus_speed,
348 static const struct udevice_id ihs_i2c_ids[] = {
349 { .compatible = "gdsys,ihs_i2cmaster", },
353 U_BOOT_DRIVER(i2c_ihs) = {
356 .of_match = ihs_i2c_ids,
357 .probe = ihs_i2c_probe,
358 .priv_auto = sizeof(struct ihs_i2c_priv),
362 #else /* CONFIG_DM_I2C */
364 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
366 #ifdef CONFIG_SYS_I2C_INIT_BOARD
368 * Call board specific i2c bus reset routine before accessing the
369 * environment, which might be in a chip on that bus. For details
370 * about this problem see doc/I2C_Edge_Conditions.
376 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
381 res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
388 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
389 int alen, uchar *buffer, int len)
393 put_unaligned_le32(addr, addr_bytes);
395 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
399 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
400 int alen, uchar *buffer, int len)
404 put_unaligned_le32(addr, addr_bytes);
406 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
410 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
413 if (speed != adap->speed)
419 * Register IHS i2c adapters
421 #ifdef CONFIG_SYS_I2C_IHS_CH0
422 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
423 ihs_i2c_read, ihs_i2c_write,
424 ihs_i2c_set_bus_speed,
425 CONFIG_SYS_I2C_IHS_SPEED_0,
426 CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
427 #ifdef CONFIG_SYS_I2C_IHS_DUAL
428 U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
429 ihs_i2c_read, ihs_i2c_write,
430 ihs_i2c_set_bus_speed,
431 CONFIG_SYS_I2C_IHS_SPEED_0_1,
432 CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
435 #ifdef CONFIG_SYS_I2C_IHS_CH1
436 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
437 ihs_i2c_read, ihs_i2c_write,
438 ihs_i2c_set_bus_speed,
439 CONFIG_SYS_I2C_IHS_SPEED_1,
440 CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
441 #ifdef CONFIG_SYS_I2C_IHS_DUAL
442 U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
443 ihs_i2c_read, ihs_i2c_write,
444 ihs_i2c_set_bus_speed,
445 CONFIG_SYS_I2C_IHS_SPEED_1_1,
446 CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
449 #ifdef CONFIG_SYS_I2C_IHS_CH2
450 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
451 ihs_i2c_read, ihs_i2c_write,
452 ihs_i2c_set_bus_speed,
453 CONFIG_SYS_I2C_IHS_SPEED_2,
454 CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
455 #ifdef CONFIG_SYS_I2C_IHS_DUAL
456 U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
457 ihs_i2c_read, ihs_i2c_write,
458 ihs_i2c_set_bus_speed,
459 CONFIG_SYS_I2C_IHS_SPEED_2_1,
460 CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
463 #ifdef CONFIG_SYS_I2C_IHS_CH3
464 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
465 ihs_i2c_read, ihs_i2c_write,
466 ihs_i2c_set_bus_speed,
467 CONFIG_SYS_I2C_IHS_SPEED_3,
468 CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
469 #ifdef CONFIG_SYS_I2C_IHS_DUAL
470 U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
471 ihs_i2c_read, ihs_i2c_write,
472 ihs_i2c_set_bus_speed,
473 CONFIG_SYS_I2C_IHS_SPEED_3_1,
474 CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
477 #endif /* CONFIG_DM_I2C */