2 * Copyright (C) 2014 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/types.h>
11 #include <asm/errno.h>
12 #include <dm/device.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 struct uniphier_fi2c_regs {
20 u32 cr; /* control register */
21 #define I2C_CR_MST (1 << 3) /* master mode */
22 #define I2C_CR_STA (1 << 2) /* start condition */
23 #define I2C_CR_STO (1 << 1) /* stop condition */
24 #define I2C_CR_NACK (1 << 0) /* not ACK */
25 u32 dttx; /* send FIFO (write-only) */
26 #define dtrx dttx /* receive FIFO (read-only) */
27 #define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */
28 #define I2C_DTTX_RD (1 << 0) /* read */
29 u32 __reserved; /* no register at offset 0x08 */
30 u32 slad; /* slave address */
31 u32 cyc; /* clock cycle control */
32 u32 lctl; /* clock low period control */
33 u32 ssut; /* restart/stop setup time control */
34 u32 dsut; /* data setup time control */
35 u32 intr; /* interrupt status */
36 u32 ie; /* interrupt enable */
37 u32 ic; /* interrupt clear */
38 #define I2C_INT_TE (1 << 9) /* TX FIFO empty */
39 #define I2C_INT_RB (1 << 4) /* received specified bytes */
40 #define I2C_INT_NA (1 << 2) /* no answer */
41 #define I2C_INT_AL (1 << 1) /* arbitration lost */
42 u32 sr; /* status register */
43 #define I2C_SR_DB (1 << 12) /* device busy */
44 #define I2C_SR_BB (1 << 8) /* bus busy */
45 #define I2C_SR_RFF (1 << 3) /* Rx FIFO full */
46 #define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */
47 #define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */
48 #define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */
49 u32 __reserved2; /* no register at offset 0x30 */
50 u32 rst; /* reset control */
51 #define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */
52 #define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */
53 #define I2C_RST_RST (1 << 0) /* forcible bus reset */
54 u32 bm; /* bus monitor */
55 u32 noise; /* noise filter control */
56 u32 tbc; /* Tx byte count setting */
57 u32 rbc; /* Rx byte count setting */
58 u32 tbcm; /* Tx byte count monitor */
59 u32 rbcm; /* Rx byte count monitor */
60 u32 brst; /* bus reset */
61 #define I2C_BRST_FOEN (1 << 1) /* normal operation */
62 #define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */
65 #define FIOCLK 50000000
67 struct uniphier_fi2c_dev {
68 struct uniphier_fi2c_regs __iomem *regs; /* register base */
69 unsigned long fioclk; /* internal operation clock */
70 unsigned long timeout; /* time out (us) */
73 static int poll_status(u32 __iomem *reg, u32 flag)
75 int wait = 1000000; /* 1 sec is long enough */
77 while (readl(reg) & flag) {
86 static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
90 /* bus forcible reset */
91 writel(I2C_RST_RST, ®s->rst);
92 ret = poll_status(®s->rst, I2C_RST_RST);
94 debug("error: fail to reset I2C controller\n");
99 static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
103 ret = poll_status(®s->sr, I2C_SR_DB);
105 debug("error: device busy too long. reset...\n");
106 ret = reset_bus(regs);
112 static int uniphier_fi2c_probe(struct udevice *dev)
116 struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
119 addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
122 priv->regs = map_sysmem(addr, size);
127 priv->fioclk = FIOCLK;
129 /* bus forcible reset */
130 ret = reset_bus(priv->regs);
134 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
139 static int uniphier_fi2c_remove(struct udevice *dev)
141 struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
143 unmap_sysmem(priv->regs);
148 static int uniphier_fi2c_child_pre_probe(struct udevice *dev)
150 struct dm_i2c_chip *i2c_chip = dev_get_parentdata(dev);
152 if (dev->of_offset == -1)
154 return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset,
158 static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags,
162 unsigned long wait = dev->timeout;
163 int ret = -EREMOTEIO;
167 irq = readl(&dev->regs->intr);
168 } while (!(irq & flags) && wait--);
171 debug("error: time out\n");
175 if (irq & I2C_INT_AL) {
176 debug("error: arbitration lost\n");
181 if (irq & I2C_INT_NA) {
182 debug("error: no answer\n");
189 static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret)
193 debug("stop condition\n");
194 writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);
196 ret = poll_status(&dev->regs->sr, I2C_SR_DB);
198 debug("error: device busy after operation\n");
200 return old_ret ? old_ret : ret;
203 static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr,
204 uint len, const u8 *buf, bool *stop)
207 const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
208 struct uniphier_fi2c_regs __iomem *regs = dev->regs;
210 debug("%s: addr = %x, len = %d\n", __func__, addr, len);
212 writel(I2C_DTTX_CMD | addr << 1, ®s->dttx);
214 writel(irq_flags, ®s->ie);
215 writel(irq_flags, ®s->ic);
217 debug("start condition\n");
218 writel(I2C_CR_MST | I2C_CR_STA, ®s->cr);
220 ret = wait_for_irq(dev, irq_flags, stop);
225 debug("sending %x\n", *buf);
226 writel(*buf++, ®s->dttx);
228 writel(irq_flags, ®s->ic);
230 ret = wait_for_irq(dev, irq_flags, stop);
236 writel(irq_flags, ®s->ic);
239 ret = issue_stop(dev, ret);
244 static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr,
245 uint len, u8 *buf, bool *stop)
248 const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
249 struct uniphier_fi2c_regs __iomem *regs = dev->regs;
251 debug("%s: addr = %x, len = %d\n", __func__, addr, len);
254 * In case 'len == 0', only the slave address should be sent
255 * for probing, which is covered by the transmit function.
258 return uniphier_fi2c_transmit(dev, addr, len, buf, stop);
260 writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, ®s->dttx);
262 writel(0, ®s->rbc);
263 writel(irq_flags, ®s->ie);
264 writel(irq_flags, ®s->ic);
266 debug("start condition\n");
267 writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
271 ret = wait_for_irq(dev, irq_flags, stop);
275 *buf++ = readl(®s->dtrx);
276 debug("received %x\n", *(buf - 1));
279 writel(I2C_CR_MST | I2C_CR_NACK, ®s->cr);
281 writel(irq_flags, ®s->ic);
285 writel(irq_flags, ®s->ic);
288 ret = issue_stop(dev, ret);
293 static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
297 struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
300 ret = check_device_busy(dev->regs);
304 for (; nmsgs > 0; nmsgs--, msg++) {
305 /* If next message is read, skip the stop condition */
306 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
308 if (msg->flags & I2C_M_RD)
309 ret = uniphier_fi2c_receive(dev, msg->addr, msg->len,
312 ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len,
322 static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
325 unsigned int clk_count;
326 struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
327 struct uniphier_fi2c_regs __iomem *regs = dev->regs;
329 /* max supported frequency is 400 kHz */
333 ret = check_device_busy(dev->regs);
337 /* make sure the bus is idle when changing the frequency */
338 writel(I2C_BRST_RSCLO, ®s->brst);
340 clk_count = dev->fioclk / speed;
342 writel(clk_count, ®s->cyc);
343 writel(clk_count / 2, ®s->lctl);
344 writel(clk_count / 2, ®s->ssut);
345 writel(clk_count / 16, ®s->dsut);
347 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, ®s->brst);
350 * Theoretically, each byte can be transferred in
351 * 1000000 * 9 / speed usec.
352 * This time out value is long enough.
354 dev->timeout = 100000000L / speed;
359 static const struct dm_i2c_ops uniphier_fi2c_ops = {
360 .xfer = uniphier_fi2c_xfer,
361 .set_bus_speed = uniphier_fi2c_set_bus_speed,
364 static const struct udevice_id uniphier_fi2c_of_match[] = {
365 { .compatible = "panasonic,uniphier-fi2c" },
369 U_BOOT_DRIVER(uniphier_fi2c) = {
370 .name = "uniphier-fi2c",
372 .of_match = uniphier_fi2c_of_match,
373 .probe = uniphier_fi2c_probe,
374 .remove = uniphier_fi2c_remove,
375 .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
376 .child_pre_probe = uniphier_fi2c_child_pre_probe,
377 .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev),
378 .ops = &uniphier_fi2c_ops,