drivers/i2c/i2c-microchip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Microchip I2C controller driver
   4  *
   5  * Copyright (C) 2021 Microchip Technology Inc.
   6  * Padmarao Begari <padmarao.begari@microchip.com>
   7  */
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <i2c.h>
  12 #include <asm/io.h>
  13 #include <dm/device_compat.h>
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17
  18 #define MICROCHIP_I2C_TIMEOUT   (1000 * 60)
  19
  20 #define MPFS_I2C_CTRL   (0x00)
  21 #define CTRL_CR0                (0x00)
  22 #define CTRL_CR1                (0x01)
  23 #define CTRL_AA                 BIT(2)
  24 #define CTRL_SI                 BIT(3)
  25 #define CTRL_STO                BIT(4)
  26 #define CTRL_STA                BIT(5)
  27 #define CTRL_ENS1               BIT(6)
  28 #define CTRL_CR2                (0x07)
  29 #define MPFS_I2C_STATUS                                                 (0x04)
  30 #define STATUS_BUS_ERROR                                                (0x00)
  31 #define STATUS_M_START_SENT                                             (0x08)
  32 #define STATUS_M_REPEATED_START_SENT                    (0x10)
  33 #define STATUS_M_SLAW_ACK                                               (0x18)
  34 #define STATUS_M_SLAW_NACK                                              (0x20)
  35 #define STATUS_M_TX_DATA_ACK                                    (0x28)
  36 #define STATUS_M_TX_DATA_NACK                                   (0x30)
  37 #define STATUS_M_ARB_LOST                                               (0x38)
  38 #define STATUS_M_SLAR_ACK                                               (0x40)
  39 #define STATUS_M_SLAR_NACK                                              (0x48)
  40 #define STATUS_M_RX_DATA_ACKED                                  (0x50)
  41 #define STATUS_M_RX_DATA_NACKED                                 (0x58)
  42 #define STATUS_S_SLAW_ACKED                                             (0x60)
  43 #define STATUS_S_ARB_LOST_SLAW_ACKED                    (0x68)
  44 #define STATUS_S_GENERAL_CALL_ACKED                             (0x70)
  45 #define STATUS_S_ARB_LOST_GENERAL_CALL_ACKED    (0x78)
  46 #define STATUS_S_RX_DATA_ACKED                                  (0x80)
  47 #define STATUS_S_RX_DATA_NACKED                                 (0x88)
  48 #define STATUS_S_GENERAL_CALL_RX_DATA_ACKED             (0x90)
  49 #define STATUS_S_GENERAL_CALL_RX_DATA_NACKED    (0x98)
  50 #define STATUS_S_RX_STOP                                                (0xA0)
  51 #define STATUS_S_SLAR_ACKED                                             (0xA8)
  52 #define STATUS_S_ARB_LOST_SLAR_ACKED                    (0xB0)
  53 #define STATUS_S_TX_DATA_ACK                                    (0xb8)
  54 #define STATUS_S_TX_DATA_NACK                                   (0xC0)
  55 #define STATUS_LAST_DATA_ACK                                    (0xC8)
  56 #define STATUS_M_SMB_MASTER_RESET                               (0xD0)
  57 #define STATUS_S_SCL_LOW_TIMEOUT                                (0xD8)
  58 #define STATUS_NO_STATE_INFO                                    (0xF8)
  59 #define MPFS_I2C_DATA                   (0x08)
  60 #define MPFS_I2C_SLAVE0_ADDR    (0x0c)
  61 #define MPFS_I2C_SMBUS                  (0x10)
  62 #define MPFS_I2C_FREQ                   (0x14)
  63 #define MPFS_I2C_GLITCHREG              (0x18)
  64 #define MPFS_I2C_SLAVE1_ADDR    (0x1c)
  65
  66 #define PCLK_DIV_256    ((0 << CTRL_CR0) | (0 << CTRL_CR1) | (0 << CTRL_CR2))
  67 #define PCLK_DIV_224    ((1 << CTRL_CR0) | (0 << CTRL_CR1) | (0 << CTRL_CR2))
  68 #define PCLK_DIV_192    ((0 << CTRL_CR0) | (1 << CTRL_CR1) | (0 << CTRL_CR2))
  69 #define PCLK_DIV_160    ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (0 << CTRL_CR2))
  70 #define PCLK_DIV_960    ((0 << CTRL_CR0) | (0 << CTRL_CR1) | (1 << CTRL_CR2))
  71 #define PCLK_DIV_120    ((1 << CTRL_CR0) | (0 << CTRL_CR1) | (1 << CTRL_CR2))
  72 #define PCLK_DIV_60             ((0 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
  73 #define BCLK_DIV_8              ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
  74 #define CLK_MASK                ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
  75
  76 /*
  77  * mpfs_i2c_bus - I2C bus context
  78  * @base: pointer to register struct
  79  * @msg_len: number of bytes transferred in msg
  80  * @msg_err: error code for completed message
  81  * @i2c_clk: clock reference for i2c input clock
  82  * @clk_rate: current i2c bus clock rate
  83  * @buf: ptr to msg buffer for easier use.
  84  * @addr: i2c address.
  85  * @isr_status: cached copy of local ISR status.
  86  */
  87 struct mpfs_i2c_bus {
  88         void __iomem *base;
  89         size_t msg_len;
  90         int msg_err;
  91         struct clk i2c_clk;
  92         u32 clk_rate;
  93         u8 *buf;
  94         u8 addr;
  95         u32 isr_status;
  96 };
  97
  98 static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
  99 {
 100         return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
 101 }
 102
 103 static void mpfs_i2c_int_clear(struct mpfs_i2c_bus *bus)
 104 {
 105         u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
 106
 107         ctrl &= ~CTRL_SI;
 108         writel(ctrl, bus->base + MPFS_I2C_CTRL);
 109 }
 110
 111 static void mpfs_i2c_core_disable(struct mpfs_i2c_bus *bus)
 112 {
 113         u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
 114
 115         ctrl &= ~CTRL_ENS1;
 116         writel(ctrl, bus->base + MPFS_I2C_CTRL);
 117 }
 118
 119 static void mpfs_i2c_core_enable(struct mpfs_i2c_bus *bus)
 120 {
 121         u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
 122
 123         ctrl |= CTRL_ENS1;
 124         writel(ctrl, bus->base + MPFS_I2C_CTRL);
 125 }
 126
 127 static void mpfs_i2c_reset(struct mpfs_i2c_bus *bus)
 128 {
 129         mpfs_i2c_core_disable(bus);
 130         mpfs_i2c_core_enable(bus);
 131 }
 132
 133 static inline void mpfs_i2c_stop(struct mpfs_i2c_bus *bus)
 134 {
 135         u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
 136
 137         ctrl |= CTRL_STO;
 138         writel(ctrl, bus->base + MPFS_I2C_CTRL);
 139 }
 140
 141 static inline int mpfs_generate_divisor(u32 rate, u8 *code)
 142 {
 143         int ret = 0;
 144
 145         if (rate >= 960)
 146                 *code = PCLK_DIV_960;
 147         else if (rate >= 256)
 148                 *code = PCLK_DIV_256;
 149         else if (rate >= 224)
 150                 *code = PCLK_DIV_224;
 151         else if (rate >= 192)
 152                 *code = PCLK_DIV_192;
 153         else if (rate >= 160)
 154                 *code = PCLK_DIV_160;
 155         else if (rate >= 120)
 156                 *code = PCLK_DIV_120;
 157         else if (rate >= 60)
 158                 *code = PCLK_DIV_60;
 159         else if (rate >= 8)
 160                 *code = BCLK_DIV_8;
 161         else
 162                 ret = -EINVAL;
 163
 164         return ret;
 165 }
 166
 167 static int mpfs_i2c_init(struct mpfs_i2c_bus *bus, struct udevice *dev)
 168 {
 169         u32 clk_rate, divisor;
 170         u8 clkval, ctrl;
 171         int ret;
 172
 173         ret = clk_get_by_index(dev, 0, &bus->i2c_clk);
 174         if (ret)
 175                 return -EINVAL;
 176
 177         ret = clk_enable(&bus->i2c_clk);
 178         if (ret)
 179                 return ret;
 180
 181         clk_rate = clk_get_rate(&bus->i2c_clk);
 182         if (!clk_rate)
 183                 return -EINVAL;
 184
 185         clk_free(&bus->i2c_clk);
 186
 187         divisor = clk_rate / bus->clk_rate;
 188
 189         ctrl = readl(bus->base + MPFS_I2C_CTRL);
 190
 191         ctrl &= ~CLK_MASK;
 192
 193         ret = mpfs_generate_divisor(divisor, &clkval);
 194         if (ret)
 195                 return -EINVAL;
 196
 197         ctrl |= clkval;
 198
 199         writel(ctrl, bus->base + MPFS_I2C_CTRL);
 200
 201         ctrl = readl(bus->base + MPFS_I2C_CTRL);
 202
 203         /* Reset I2C core */
 204         mpfs_i2c_reset(bus);
 205
 206         return 0;
 207 }
 208
 209 static void mpfs_i2c_transfer(struct mpfs_i2c_bus *bus, u32 data)
 210 {
 211         if (bus->msg_len > 0)
 212                 writel(data, bus->base + MPFS_I2C_DATA);
 213 }
 214
 215 static void mpfs_i2c_empty_rx(struct mpfs_i2c_bus *bus)
 216 {
 217         u8 ctrl;
 218         u8 data_read;
 219
 220         if (bus->msg_len > 0) {
 221                 data_read = readl(bus->base + MPFS_I2C_DATA);
 222                 *bus->buf++ = data_read;
 223                 bus->msg_len--;
 224         }
 225
 226         if (bus->msg_len == 0) {
 227                 ctrl = readl(bus->base + MPFS_I2C_CTRL);
 228                 ctrl &= ~CTRL_AA;
 229                 writel(ctrl, bus->base + MPFS_I2C_CTRL);
 230         }
 231 }
 232
 233 static int mpfs_i2c_fill_tx(struct mpfs_i2c_bus *bus)
 234 {
 235         mpfs_i2c_transfer(bus, *bus->buf++);
 236         bus->msg_len--;
 237
 238         return 0;
 239 }
 240
 241 static int mpfs_i2c_service_handler(struct mpfs_i2c_bus *bus)
 242 {
 243         bool finish = false;
 244         u32 status;
 245         u8 ctrl;
 246
 247         status = bus->isr_status;
 248
 249         switch (status) {
 250         case STATUS_M_START_SENT:
 251         case STATUS_M_REPEATED_START_SENT:
 252                 ctrl = readl(bus->base + MPFS_I2C_CTRL);
 253                 ctrl &= ~CTRL_STA;
 254                 writel(bus->addr, bus->base + MPFS_I2C_DATA);
 255                 writel(ctrl, bus->base + MPFS_I2C_CTRL);
 256                 break;
 257         case STATUS_M_SLAW_ACK:
 258         case STATUS_M_TX_DATA_ACK:
 259                 if (bus->msg_len > 0) {
 260                         mpfs_i2c_fill_tx(bus);
 261                 } else {
 262                         /* On the last byte to be transmitted, send STOP */
 263                         mpfs_i2c_stop(bus);
 264                         finish = true;
 265                 }
 266                 break;
 267         case STATUS_M_SLAR_ACK:
 268                 ctrl = readl(bus->base + MPFS_I2C_CTRL);
 269                 ctrl |= CTRL_AA;
 270                 writel(ctrl, bus->base + MPFS_I2C_CTRL);
 271                 if (bus->msg_len == 0) {
 272                         /* On the last byte to be transmitted, send STOP */
 273                         mpfs_i2c_stop(bus);
 274                         finish = true;
 275                 }
 276                 break;
 277         case STATUS_M_RX_DATA_ACKED:
 278                 mpfs_i2c_empty_rx(bus);
 279                 if (bus->msg_len == 0) {
 280                         /* On the last byte to be transmitted, send STOP */
 281                         mpfs_i2c_stop(bus);
 282                         finish = true;
 283                 }
 284                 break;
 285         case STATUS_M_TX_DATA_NACK:
 286         case STATUS_M_RX_DATA_NACKED:
 287         case STATUS_M_SLAR_NACK:
 288         case STATUS_M_SLAW_NACK:
 289                 bus->msg_err = -ENXIO;
 290                 mpfs_i2c_stop(bus);
 291                 finish = true;
 292                 break;
 293
 294         case STATUS_M_ARB_LOST:
 295                 /* Handle Lost Arbitration */
 296                 bus->msg_err = -EAGAIN;
 297                 finish = true;
 298                 break;
 299         default:
 300                 break;
 301         }
 302
 303         if (finish) {
 304                 ctrl = readl(bus->base + MPFS_I2C_CTRL);
 305                 ctrl &= ~CTRL_AA;
 306                 writel(ctrl, bus->base + MPFS_I2C_CTRL);
 307                 return 0;
 308         }
 309
 310         return 1;
 311 }
 312
 313 static int mpfs_i2c_service(struct mpfs_i2c_bus *bus)
 314 {
 315         int ret = 0;
 316         int si_bit;
 317
 318         si_bit = readl(bus->base + MPFS_I2C_CTRL);
 319         if (si_bit & CTRL_SI) {
 320                 bus->isr_status = readl(bus->base + MPFS_I2C_STATUS);
 321                 ret = mpfs_i2c_service_handler(bus);
 322         }
 323         /* Clear the si flag */
 324         mpfs_i2c_int_clear(bus);
 325         si_bit = readl(bus->base + MPFS_I2C_CTRL);
 326
 327         return ret;
 328 }
 329
 330 static int mpfs_i2c_check_service_change(struct mpfs_i2c_bus *bus)
 331 {
 332         u8 ctrl;
 333         u32 count = 0;
 334
 335         while (1) {
 336                 ctrl = readl(bus->base + MPFS_I2C_CTRL);
 337                 if (ctrl & CTRL_SI)
 338                         break;
 339                 udelay(1);
 340                 count += 1;
 341                 if (count == MICROCHIP_I2C_TIMEOUT)
 342                         return -ETIMEDOUT;
 343         }
 344         return 0;
 345 }
 346
 347 static int mpfs_i2c_poll_device(struct mpfs_i2c_bus *bus)
 348 {
 349         int ret;
 350
 351         while (1) {
 352                 ret = mpfs_i2c_check_service_change(bus);
 353                 if (ret)
 354                         return ret;
 355
 356                 ret = mpfs_i2c_service(bus);
 357                 if (!ret)
 358                         /* all messages have been transferred */
 359                         return ret;
 360         }
 361 }
 362
 363 static int mpfs_i2c_xfer_msg(struct mpfs_i2c_bus *bus, struct i2c_msg *msg)
 364 {
 365         u8 ctrl;
 366         int ret;
 367
 368         if (!msg->len || !msg->buf)
 369                 return -EINVAL;
 370
 371         bus->addr = i2c_8bit_addr_from_msg(msg);
 372         bus->msg_len = msg->len;
 373         bus->buf = msg->buf;
 374         bus->msg_err = 0;
 375
 376         mpfs_i2c_core_enable(bus);
 377
 378         ctrl = readl(bus->base + MPFS_I2C_CTRL);
 379
 380         ctrl |= CTRL_STA;
 381
 382         writel(ctrl, bus->base + MPFS_I2C_CTRL);
 383
 384         ret = mpfs_i2c_poll_device(bus);
 385         if (ret)
 386                 return ret;
 387
 388         return bus->msg_err;
 389 }
 390
 391 static int mpfs_i2c_xfer(struct udevice *dev, struct i2c_msg *msgs, int num_msgs)
 392 {
 393         struct mpfs_i2c_bus *bus = dev_get_priv(dev);
 394         int idx, ret;
 395
 396         if (!msgs || !num_msgs)
 397                 return -EINVAL;
 398
 399         for (idx = 0; idx < num_msgs; idx++) {
 400                 ret = mpfs_i2c_xfer_msg(bus, msgs++);
 401                 if (ret)
 402                         return ret;
 403         }
 404
 405         return ret;
 406 }
 407
 408 static int mpfs_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
 409 {
 410         struct mpfs_i2c_bus *bus = dev_get_priv(dev);
 411         int ret;
 412         u8 ctrl, reg = 0;
 413
 414         /*
 415          * Send the chip address and verify that the
 416          * address was <ACK>ed.
 417          */
 418         bus->addr = addr << 1 | I2C_M_RD;
 419         bus->buf = &reg;
 420         bus->msg_len = 0;
 421         bus->msg_err = 0;
 422
 423         mpfs_i2c_core_enable(bus);
 424
 425         ctrl = readl(bus->base + MPFS_I2C_CTRL);
 426
 427         ctrl |= CTRL_STA;
 428
 429         writel(ctrl, bus->base + MPFS_I2C_CTRL);
 430
 431         ret = mpfs_i2c_poll_device(bus);
 432         if (ret)
 433                 return ret;
 434
 435         return bus->msg_err;
 436 }
 437
 438 static int mpfs_i2c_probe(struct udevice *dev)
 439 {
 440         int ret;
 441         u32 val;
 442         struct mpfs_i2c_bus *bus = dev_get_priv(dev);
 443
 444         bus->base = dev_read_addr_ptr(dev);
 445         if (!bus->base)
 446                 return -EINVAL;
 447
 448         val = dev_read_u32(dev, "clock-frequency", &bus->clk_rate);
 449         if (val) {
 450                 printf("Default to 100kHz\n");
 451                 /* default clock rate */
 452                 bus->clk_rate = 100000;
 453         }
 454
 455         if (bus->clk_rate > 400000 || bus->clk_rate <= 0) {
 456                 printf("Invalid clock-frequency %d\n", bus->clk_rate);
 457                 return -EINVAL;
 458         }
 459
 460         ret = mpfs_i2c_init(bus, dev);
 461
 462         return ret;
 463 }
 464
 465 static const struct dm_i2c_ops mpfs_i2c_ops = {
 466         .xfer = mpfs_i2c_xfer,
 467         .probe_chip = mpfs_i2c_probe_chip,
 468 };
 469
 470 static const struct udevice_id mpfs_i2c_ids[] = {
 471         {.compatible = "microchip,mpfs-i2c"},
 472         {}
 473 };
 474
 475 U_BOOT_DRIVER(mpfs_i2c) = {
 476         .name = "mpfs_i2c",
 477         .id = UCLASS_I2C,
 478         .of_match = mpfs_i2c_ids,
 479         .ops = &mpfs_i2c_ops,
 480         .probe = mpfs_i2c_probe,
 481         .priv_auto = sizeof(struct mpfs_i2c_bus),
 482 };