drivers/i2c/i2c-cdns.c

   1 /*
   2  * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
   3  * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   4  *
   5  * This file is based on: drivers/i2c/zynq_i2c.c,
   6  * with added driver-model support and code cleanup.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <linux/types.h>
  14 #include <linux/io.h>
  15 #include <linux/errno.h>
  16 #include <dm/root.h>
  17 #include <i2c.h>
  18 #include <fdtdec.h>
  19 #include <mapmem.h>
  20 #include <wait_bit.h>
  21
  22 /* i2c register set */
  23 struct cdns_i2c_regs {
  24         u32 control;
  25         u32 status;
  26         u32 address;
  27         u32 data;
  28         u32 interrupt_status;
  29         u32 transfer_size;
  30         u32 slave_mon_pause;
  31         u32 time_out;
  32         u32 interrupt_mask;
  33         u32 interrupt_enable;
  34         u32 interrupt_disable;
  35 };
  36
  37 /* Control register fields */
  38 #define CDNS_I2C_CONTROL_RW             0x00000001
  39 #define CDNS_I2C_CONTROL_MS             0x00000002
  40 #define CDNS_I2C_CONTROL_NEA            0x00000004
  41 #define CDNS_I2C_CONTROL_ACKEN          0x00000008
  42 #define CDNS_I2C_CONTROL_HOLD           0x00000010
  43 #define CDNS_I2C_CONTROL_SLVMON         0x00000020
  44 #define CDNS_I2C_CONTROL_CLR_FIFO       0x00000040
  45 #define CDNS_I2C_CONTROL_DIV_B_SHIFT    8
  46 #define CDNS_I2C_CONTROL_DIV_B_MASK     0x00003F00
  47 #define CDNS_I2C_CONTROL_DIV_A_SHIFT    14
  48 #define CDNS_I2C_CONTROL_DIV_A_MASK     0x0000C000
  49
  50 /* Status register values */
  51 #define CDNS_I2C_STATUS_RXDV    0x00000020
  52 #define CDNS_I2C_STATUS_TXDV    0x00000040
  53 #define CDNS_I2C_STATUS_RXOVF   0x00000080
  54 #define CDNS_I2C_STATUS_BA      0x00000100
  55
  56 /* Interrupt register fields */
  57 #define CDNS_I2C_INTERRUPT_COMP         0x00000001
  58 #define CDNS_I2C_INTERRUPT_DATA         0x00000002
  59 #define CDNS_I2C_INTERRUPT_NACK         0x00000004
  60 #define CDNS_I2C_INTERRUPT_TO           0x00000008
  61 #define CDNS_I2C_INTERRUPT_SLVRDY       0x00000010
  62 #define CDNS_I2C_INTERRUPT_RXOVF        0x00000020
  63 #define CDNS_I2C_INTERRUPT_TXOVF        0x00000040
  64 #define CDNS_I2C_INTERRUPT_RXUNF        0x00000080
  65 #define CDNS_I2C_INTERRUPT_ARBLOST      0x00000200
  66
  67 #define CDNS_I2C_FIFO_DEPTH             16
  68 #define CDNS_I2C_TRANSFER_SIZE_MAX      255 /* Controller transfer limit */
  69 #define CDNS_I2C_TRANSFER_SIZE          (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
  70
  71 #define CDNS_I2C_BROKEN_HOLD_BIT        BIT(0)
  72
  73 #ifdef DEBUG
  74 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
  75 {
  76         int int_status;
  77         int status;
  78         int_status = readl(&cdns_i2c->interrupt_status);
  79
  80         status = readl(&cdns_i2c->status);
  81         if (int_status || status) {
  82                 debug("Status: ");
  83                 if (int_status & CDNS_I2C_INTERRUPT_COMP)
  84                         debug("COMP ");
  85                 if (int_status & CDNS_I2C_INTERRUPT_DATA)
  86                         debug("DATA ");
  87                 if (int_status & CDNS_I2C_INTERRUPT_NACK)
  88                         debug("NACK ");
  89                 if (int_status & CDNS_I2C_INTERRUPT_TO)
  90                         debug("TO ");
  91                 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
  92                         debug("SLVRDY ");
  93                 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
  94                         debug("RXOVF ");
  95                 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
  96                         debug("TXOVF ");
  97                 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
  98                         debug("RXUNF ");
  99                 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
 100                         debug("ARBLOST ");
 101                 if (status & CDNS_I2C_STATUS_RXDV)
 102                         debug("RXDV ");
 103                 if (status & CDNS_I2C_STATUS_TXDV)
 104                         debug("TXDV ");
 105                 if (status & CDNS_I2C_STATUS_RXOVF)
 106                         debug("RXOVF ");
 107                 if (status & CDNS_I2C_STATUS_BA)
 108                         debug("BA ");
 109                 debug("TS%d ", readl(&cdns_i2c->transfer_size));
 110                 debug("\n");
 111         }
 112 }
 113 #endif
 114
 115 struct i2c_cdns_bus {
 116         int id;
 117         unsigned int input_freq;
 118         struct cdns_i2c_regs __iomem *regs;     /* register base */
 119
 120         int hold_flag;
 121         u32 quirks;
 122 };
 123
 124 struct cdns_i2c_platform_data {
 125         u32 quirks;
 126 };
 127
 128 /* Wait for an interrupt */
 129 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 130 {
 131         int timeout, int_status;
 132
 133         for (timeout = 0; timeout < 100; timeout++) {
 134                 int_status = readl(&cdns_i2c->interrupt_status);
 135                 if (int_status & mask)
 136                         break;
 137                 udelay(100);
 138         }
 139
 140         /* Clear interrupt status flags */
 141         writel(int_status & mask, &cdns_i2c->interrupt_status);
 142
 143         return int_status & mask;
 144 }
 145
 146 #define CDNS_I2C_DIVA_MAX       4
 147 #define CDNS_I2C_DIVB_MAX       64
 148
 149 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
 150                 unsigned int *a, unsigned int *b)
 151 {
 152         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
 153         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
 154         unsigned int last_error, current_error;
 155
 156         /* calculate (divisor_a+1) x (divisor_b+1) */
 157         temp = input_clk / (22 * fscl);
 158
 159         /*
 160          * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
 161          * the fscl input is out of range. Return error.
 162          */
 163         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
 164                 return -EINVAL;
 165
 166         last_error = -1;
 167         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
 168                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
 169
 170                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
 171                         continue;
 172                 div_b--;
 173
 174                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
 175
 176                 if (actual_fscl > fscl)
 177                         continue;
 178
 179                 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
 180                                                         (fscl - actual_fscl));
 181
 182                 if (last_error > current_error) {
 183                         calc_div_a = div_a;
 184                         calc_div_b = div_b;
 185                         best_fscl = actual_fscl;
 186                         last_error = current_error;
 187                 }
 188         }
 189
 190         *a = calc_div_a;
 191         *b = calc_div_b;
 192         *f = best_fscl;
 193
 194         return 0;
 195 }
 196
 197 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 198 {
 199         struct i2c_cdns_bus *bus = dev_get_priv(dev);
 200         u32 div_a = 0, div_b = 0;
 201         unsigned long speed_p = speed;
 202         int ret = 0;
 203
 204         if (speed > 400000) {
 205                 debug("%s, failed to set clock speed to %u\n", __func__,
 206                       speed);
 207                 return -EINVAL;
 208         }
 209
 210         ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
 211         if (ret)
 212                 return ret;
 213
 214         debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
 215               __func__, div_a, div_b, bus->input_freq, speed, speed_p);
 216
 217         writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
 218                (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
 219
 220         /* Enable master mode, ack, and 7-bit addressing */
 221         setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
 222                 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
 223
 224         return 0;
 225 }
 226
 227 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 228                                u32 len)
 229 {
 230         u8 *cur_data = data;
 231         struct cdns_i2c_regs *regs = i2c_bus->regs;
 232
 233         /* Set the controller in Master transmit mode and clear FIFO */
 234         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
 235         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
 236
 237         /* Check message size against FIFO depth, and set hold bus bit
 238          * if it is greater than FIFO depth
 239          */
 240         if (len > CDNS_I2C_FIFO_DEPTH)
 241                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 242
 243         /* Clear the interrupts in status register */
 244         writel(0xFF, &regs->interrupt_status);
 245
 246         writel(addr, &regs->address);
 247
 248         while (len--) {
 249                 writel(*(cur_data++), &regs->data);
 250                 if (readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
 251                         if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
 252                                 /* Release the bus */
 253                                 clrbits_le32(&regs->control,
 254                                              CDNS_I2C_CONTROL_HOLD);
 255                                 return -ETIMEDOUT;
 256                         }
 257                 }
 258         }
 259
 260         /* All done... release the bus */
 261         if (!i2c_bus->hold_flag)
 262                 clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 263
 264         /* Wait for the address and data to be sent */
 265         if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
 266                 return -ETIMEDOUT;
 267         return 0;
 268 }
 269
 270 static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
 271 {
 272         return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
 273 }
 274
 275 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 276                               u32 recv_count)
 277 {
 278         u8 *cur_data = data;
 279         struct cdns_i2c_regs *regs = i2c_bus->regs;
 280         int curr_recv_count;
 281         int updatetx, hold_quirk;
 282
 283         /* Check the hardware can handle the requested bytes */
 284         if ((recv_count < 0))
 285                 return -EINVAL;
 286
 287         curr_recv_count = recv_count;
 288
 289         /* Check for the message size against the FIFO depth */
 290         if (recv_count > CDNS_I2C_FIFO_DEPTH)
 291                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 292
 293         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
 294                 CDNS_I2C_CONTROL_RW);
 295
 296         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 297                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 298                 writel(curr_recv_count, &regs->transfer_size);
 299         } else {
 300                 writel(recv_count, &regs->transfer_size);
 301         }
 302
 303         /* Start reading data */
 304         writel(addr, &regs->address);
 305
 306         updatetx = recv_count > curr_recv_count;
 307
 308         hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
 309
 310         while (recv_count) {
 311                 while (readl(&regs->status) & CDNS_I2C_STATUS_RXDV) {
 312                         if (recv_count < CDNS_I2C_FIFO_DEPTH &&
 313                             !i2c_bus->hold_flag) {
 314                                 clrbits_le32(&regs->control,
 315                                              CDNS_I2C_CONTROL_HOLD);
 316                         }
 317                         *(cur_data)++ = readl(&regs->data);
 318                         recv_count--;
 319                         curr_recv_count--;
 320
 321                         if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
 322                                 break;
 323                 }
 324
 325                 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
 326                         /* wait while fifo is full */
 327                         while (readl(&regs->transfer_size) !=
 328                                      (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
 329                                 ;
 330                         /*
 331                          * Check number of bytes to be received against maximum
 332                          * transfer size and update register accordingly.
 333                          */
 334                         if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
 335                             CDNS_I2C_TRANSFER_SIZE) {
 336                                 writel(CDNS_I2C_TRANSFER_SIZE,
 337                                        &regs->transfer_size);
 338                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
 339                                         CDNS_I2C_FIFO_DEPTH;
 340                         } else {
 341                                 writel(recv_count - CDNS_I2C_FIFO_DEPTH,
 342                                        &regs->transfer_size);
 343                                 curr_recv_count = recv_count;
 344                         }
 345                 } else if (recv_count && !hold_quirk && !curr_recv_count) {
 346                         writel(addr, &regs->address);
 347                         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 348                                 writel(CDNS_I2C_TRANSFER_SIZE,
 349                                        &regs->transfer_size);
 350                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 351                         } else {
 352                                 writel(recv_count, &regs->transfer_size);
 353                                 curr_recv_count = recv_count;
 354                         }
 355                 }
 356         }
 357
 358         /* Wait for the address and data to be sent */
 359         if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
 360                 return -ETIMEDOUT;
 361
 362         return 0;
 363 }
 364
 365 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 366                          int nmsgs)
 367 {
 368         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 369         int ret, count;
 370         bool hold_quirk;
 371
 372         hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
 373
 374         if (nmsgs > 1) {
 375                 /*
 376                  * This controller does not give completion interrupt after a
 377                  * master receive message if HOLD bit is set (repeated start),
 378                  * resulting in SW timeout. Hence, if a receive message is
 379                  * followed by any other message, an error is returned
 380                  * indicating that this sequence is not supported.
 381                  */
 382                 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
 383                         if (msg[count].flags & I2C_M_RD) {
 384                                 printf("Can't do repeated start after a receive message\n");
 385                                 return -EOPNOTSUPP;
 386                         }
 387                 }
 388
 389                 i2c_bus->hold_flag = 1;
 390                 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
 391         } else {
 392                 i2c_bus->hold_flag = 0;
 393         }
 394
 395         debug("i2c_xfer: %d messages\n", nmsgs);
 396         for (; nmsgs > 0; nmsgs--, msg++) {
 397                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 398                 if (msg->flags & I2C_M_RD) {
 399                         ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
 400                                                  msg->len);
 401                 } else {
 402                         ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
 403                                                   msg->len);
 404                 }
 405                 if (ret) {
 406                         debug("i2c_write: error sending\n");
 407                         return -EREMOTEIO;
 408                 }
 409         }
 410
 411         return 0;
 412 }
 413
 414 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 415 {
 416         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 417         struct cdns_i2c_platform_data *pdata =
 418                 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
 419
 420         i2c_bus->regs = (struct cdns_i2c_regs *)devfdt_get_addr(dev);
 421         if (!i2c_bus->regs)
 422                 return -ENOMEM;
 423
 424         if (pdata)
 425                 i2c_bus->quirks = pdata->quirks;
 426
 427         i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
 428
 429         return 0;
 430 }
 431
 432 static const struct dm_i2c_ops cdns_i2c_ops = {
 433         .xfer = cdns_i2c_xfer,
 434         .set_bus_speed = cdns_i2c_set_bus_speed,
 435 };
 436
 437 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
 438         .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
 439 };
 440
 441 static const struct udevice_id cdns_i2c_of_match[] = {
 442         { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
 443         { .compatible = "cdns,i2c-r1p14" },
 444         { /* end of table */ }
 445 };
 446
 447 U_BOOT_DRIVER(cdns_i2c) = {
 448         .name = "i2c-cdns",
 449         .id = UCLASS_I2C,
 450         .of_match = cdns_i2c_of_match,
 451         .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
 452         .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
 453         .ops = &cdns_i2c_ops,
 454 };