1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
4 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
6 * This file is based on: drivers/i2c/zynq_i2c.c,
7 * with added driver-model support and code cleanup.
13 #include <linux/delay.h>
14 #include <linux/types.h>
16 #include <linux/errno.h>
24 /* i2c register set */
25 struct cdns_i2c_regs {
36 u32 interrupt_disable;
39 /* Control register fields */
40 #define CDNS_I2C_CONTROL_RW 0x00000001
41 #define CDNS_I2C_CONTROL_MS 0x00000002
42 #define CDNS_I2C_CONTROL_NEA 0x00000004
43 #define CDNS_I2C_CONTROL_ACKEN 0x00000008
44 #define CDNS_I2C_CONTROL_HOLD 0x00000010
45 #define CDNS_I2C_CONTROL_SLVMON 0x00000020
46 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
47 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
48 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
49 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
50 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
52 /* Status register values */
53 #define CDNS_I2C_STATUS_RXDV 0x00000020
54 #define CDNS_I2C_STATUS_TXDV 0x00000040
55 #define CDNS_I2C_STATUS_RXOVF 0x00000080
56 #define CDNS_I2C_STATUS_BA 0x00000100
58 /* Interrupt register fields */
59 #define CDNS_I2C_INTERRUPT_COMP 0x00000001
60 #define CDNS_I2C_INTERRUPT_DATA 0x00000002
61 #define CDNS_I2C_INTERRUPT_NACK 0x00000004
62 #define CDNS_I2C_INTERRUPT_TO 0x00000008
63 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
64 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
65 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
66 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
67 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
69 #define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \
70 CDNS_I2C_INTERRUPT_DATA | \
71 CDNS_I2C_INTERRUPT_NACK | \
72 CDNS_I2C_INTERRUPT_TO | \
73 CDNS_I2C_INTERRUPT_SLVRDY | \
74 CDNS_I2C_INTERRUPT_RXOVF | \
75 CDNS_I2C_INTERRUPT_TXOVF | \
76 CDNS_I2C_INTERRUPT_RXUNF | \
77 CDNS_I2C_INTERRUPT_ARBLOST)
79 #define CDNS_I2C_FIFO_DEPTH 16
80 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
81 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
83 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
85 #define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
88 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
92 int_status = readl(&cdns_i2c->interrupt_status);
94 status = readl(&cdns_i2c->status);
95 if (int_status || status) {
97 if (int_status & CDNS_I2C_INTERRUPT_COMP)
99 if (int_status & CDNS_I2C_INTERRUPT_DATA)
101 if (int_status & CDNS_I2C_INTERRUPT_NACK)
103 if (int_status & CDNS_I2C_INTERRUPT_TO)
105 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
107 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
109 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
111 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
113 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
115 if (status & CDNS_I2C_STATUS_RXDV)
117 if (status & CDNS_I2C_STATUS_TXDV)
119 if (status & CDNS_I2C_STATUS_RXOVF)
121 if (status & CDNS_I2C_STATUS_BA)
123 debug("TS%d ", readl(&cdns_i2c->transfer_size));
129 struct i2c_cdns_bus {
131 unsigned int input_freq;
132 struct cdns_i2c_regs __iomem *regs; /* register base */
138 struct cdns_i2c_platform_data {
142 /* Wait for an interrupt */
143 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
145 int timeout, int_status;
147 for (timeout = 0; timeout < 100; timeout++) {
148 int_status = readl(&cdns_i2c->interrupt_status);
149 if (int_status & mask)
154 /* Clear interrupt status flags */
155 writel(int_status & mask, &cdns_i2c->interrupt_status);
157 return int_status & mask;
160 #define CDNS_I2C_DIVA_MAX 4
161 #define CDNS_I2C_DIVB_MAX 64
163 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
164 unsigned int *a, unsigned int *b)
166 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
167 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
168 unsigned int last_error, current_error;
170 /* calculate (divisor_a+1) x (divisor_b+1) */
171 temp = input_clk / (22 * fscl);
174 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
175 * the fscl input is out of range. Return error.
177 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
181 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
182 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
184 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
188 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
190 if (actual_fscl > fscl)
193 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
194 (fscl - actual_fscl));
196 if (last_error > current_error) {
199 best_fscl = actual_fscl;
200 last_error = current_error;
211 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
213 struct i2c_cdns_bus *bus = dev_get_priv(dev);
214 u32 div_a = 0, div_b = 0;
215 unsigned long speed_p = speed;
218 if (speed > I2C_SPEED_FAST_RATE) {
219 debug("%s, failed to set clock speed to %u\n", __func__,
224 ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
228 debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
229 __func__, div_a, div_b, bus->input_freq, speed, speed_p);
231 writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
232 (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
234 /* Enable master mode, ack, and 7-bit addressing */
235 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
236 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
241 static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
243 return (readl(®s->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
246 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
250 struct cdns_i2c_regs *regs = i2c_bus->regs;
253 /* Set the controller in Master transmit mode and clear FIFO */
254 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
255 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
257 /* Check message size against FIFO depth, and set hold bus bit
258 * if it is greater than FIFO depth
260 if (len > CDNS_I2C_FIFO_DEPTH)
261 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
263 /* Clear the interrupts in status register */
264 writel(CDNS_I2C_INTERRUPTS_MASK, ®s->interrupt_status);
266 writel(addr, ®s->address);
268 while (len-- && !is_arbitration_lost(regs)) {
269 writel(*(cur_data++), ®s->data);
270 if (len && readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
271 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
272 CDNS_I2C_INTERRUPT_ARBLOST);
273 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
275 if (ret & CDNS_I2C_INTERRUPT_COMP)
277 /* Release the bus */
278 clrbits_le32(®s->control,
279 CDNS_I2C_CONTROL_HOLD);
284 if (len && is_arbitration_lost(regs))
287 /* All done... release the bus */
288 if (!i2c_bus->hold_flag)
289 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
291 /* Wait for the address and data to be sent */
292 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
293 CDNS_I2C_INTERRUPT_ARBLOST);
294 if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
295 CDNS_I2C_INTERRUPT_COMP)))
297 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
303 static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
305 return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
308 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
312 struct cdns_i2c_regs *regs = i2c_bus->regs;
314 int updatetx, hold_quirk;
317 curr_recv_count = recv_count;
319 /* Check for the message size against the FIFO depth */
320 if (recv_count > CDNS_I2C_FIFO_DEPTH)
321 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
323 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
324 CDNS_I2C_CONTROL_RW);
326 if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
327 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
328 writel(curr_recv_count, ®s->transfer_size);
330 writel(recv_count, ®s->transfer_size);
333 /* Start reading data */
334 writel(addr, ®s->address);
336 updatetx = recv_count > curr_recv_count;
338 hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
340 while (recv_count && !is_arbitration_lost(regs)) {
341 while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
342 if (recv_count < CDNS_I2C_FIFO_DEPTH &&
343 !i2c_bus->hold_flag) {
344 clrbits_le32(®s->control,
345 CDNS_I2C_CONTROL_HOLD);
347 *(cur_data)++ = readl(®s->data);
351 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
355 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
356 /* wait while fifo is full */
357 while (readl(®s->transfer_size) !=
358 (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
361 * Check number of bytes to be received against maximum
362 * transfer size and update register accordingly.
364 if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
365 CDNS_I2C_TRANSFER_SIZE) {
366 writel(CDNS_I2C_TRANSFER_SIZE,
367 ®s->transfer_size);
368 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
371 writel(recv_count - CDNS_I2C_FIFO_DEPTH,
372 ®s->transfer_size);
373 curr_recv_count = recv_count;
375 } else if (recv_count && !hold_quirk && !curr_recv_count) {
376 writel(addr, ®s->address);
377 if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
378 writel(CDNS_I2C_TRANSFER_SIZE,
379 ®s->transfer_size);
380 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
382 writel(recv_count, ®s->transfer_size);
383 curr_recv_count = recv_count;
388 /* Wait for the address and data to be sent */
389 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
390 CDNS_I2C_INTERRUPT_ARBLOST);
391 if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
392 CDNS_I2C_INTERRUPT_COMP)))
394 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
400 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
403 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
407 struct i2c_msg *message = msg;
408 int num_msgs = nmsgs;
410 hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
414 * This controller does not give completion interrupt after a
415 * master receive message if HOLD bit is set (repeated start),
416 * resulting in SW timeout. Hence, if a receive message is
417 * followed by any other message, an error is returned
418 * indicating that this sequence is not supported.
420 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
421 if (msg[count].flags & I2C_M_RD) {
422 printf("Can't do repeated start after a receive message\n");
427 i2c_bus->hold_flag = 1;
428 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
430 i2c_bus->hold_flag = 0;
433 debug("i2c_xfer: %d messages\n", nmsgs);
434 for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
435 nmsgs > 0; nmsgs--, msg++) {
436 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
437 if (msg->flags & I2C_M_RD) {
438 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
441 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
444 if (ret == -EAGAIN) {
448 printf("%s,arbitration lost, retrying:%d\n", __func__,
454 debug("i2c_write: error sending\n");
462 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
464 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
465 struct cdns_i2c_platform_data *pdata =
466 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
470 i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
475 i2c_bus->quirks = pdata->quirks;
477 ret = clk_get_by_index(dev, 0, &clk);
481 i2c_bus->input_freq = clk_get_rate(&clk);
486 static const struct dm_i2c_ops cdns_i2c_ops = {
487 .xfer = cdns_i2c_xfer,
488 .set_bus_speed = cdns_i2c_set_bus_speed,
491 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
492 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
495 static const struct udevice_id cdns_i2c_of_match[] = {
496 { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
497 { .compatible = "cdns,i2c-r1p14" },
498 { /* end of table */ }
501 U_BOOT_DRIVER(cdns_i2c) = {
504 .of_match = cdns_i2c_of_match,
505 .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
506 .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
507 .ops = &cdns_i2c_ops,