1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
4 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
6 * This file is based on: drivers/i2c/zynq_i2c.c,
7 * with added driver-model support and code cleanup.
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 #include <linux/types.h>
17 #include <linux/errno.h>
25 /* i2c register set */
26 struct cdns_i2c_regs {
37 u32 interrupt_disable;
40 /* Control register fields */
41 #define CDNS_I2C_CONTROL_RW 0x00000001
42 #define CDNS_I2C_CONTROL_MS 0x00000002
43 #define CDNS_I2C_CONTROL_NEA 0x00000004
44 #define CDNS_I2C_CONTROL_ACKEN 0x00000008
45 #define CDNS_I2C_CONTROL_HOLD 0x00000010
46 #define CDNS_I2C_CONTROL_SLVMON 0x00000020
47 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
48 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
49 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
50 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
51 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
53 /* Status register values */
54 #define CDNS_I2C_STATUS_RXDV 0x00000020
55 #define CDNS_I2C_STATUS_TXDV 0x00000040
56 #define CDNS_I2C_STATUS_RXOVF 0x00000080
57 #define CDNS_I2C_STATUS_BA 0x00000100
59 /* Interrupt register fields */
60 #define CDNS_I2C_INTERRUPT_COMP 0x00000001
61 #define CDNS_I2C_INTERRUPT_DATA 0x00000002
62 #define CDNS_I2C_INTERRUPT_NACK 0x00000004
63 #define CDNS_I2C_INTERRUPT_TO 0x00000008
64 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
65 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
66 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
67 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
68 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
70 #define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \
71 CDNS_I2C_INTERRUPT_DATA | \
72 CDNS_I2C_INTERRUPT_NACK | \
73 CDNS_I2C_INTERRUPT_TO | \
74 CDNS_I2C_INTERRUPT_SLVRDY | \
75 CDNS_I2C_INTERRUPT_RXOVF | \
76 CDNS_I2C_INTERRUPT_TXOVF | \
77 CDNS_I2C_INTERRUPT_RXUNF | \
78 CDNS_I2C_INTERRUPT_ARBLOST)
80 #define CDNS_I2C_FIFO_DEPTH 16
81 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
82 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
84 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
86 #define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
89 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
93 int_status = readl(&cdns_i2c->interrupt_status);
95 status = readl(&cdns_i2c->status);
96 if (int_status || status) {
98 if (int_status & CDNS_I2C_INTERRUPT_COMP)
100 if (int_status & CDNS_I2C_INTERRUPT_DATA)
102 if (int_status & CDNS_I2C_INTERRUPT_NACK)
104 if (int_status & CDNS_I2C_INTERRUPT_TO)
106 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
108 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
110 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
112 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
114 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
116 if (status & CDNS_I2C_STATUS_RXDV)
118 if (status & CDNS_I2C_STATUS_TXDV)
120 if (status & CDNS_I2C_STATUS_RXOVF)
122 if (status & CDNS_I2C_STATUS_BA)
124 debug("TS%d ", readl(&cdns_i2c->transfer_size));
130 struct i2c_cdns_bus {
132 unsigned int input_freq;
133 struct cdns_i2c_regs __iomem *regs; /* register base */
139 struct cdns_i2c_platform_data {
143 /* Wait for an interrupt */
144 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
146 int timeout, int_status;
148 for (timeout = 0; timeout < 100; timeout++) {
149 int_status = readl(&cdns_i2c->interrupt_status);
150 if (int_status & mask)
155 /* Clear interrupt status flags */
156 writel(int_status & mask, &cdns_i2c->interrupt_status);
158 return int_status & mask;
161 #define CDNS_I2C_DIVA_MAX 4
162 #define CDNS_I2C_DIVB_MAX 64
164 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
165 unsigned int *a, unsigned int *b)
167 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
168 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
169 unsigned int last_error, current_error;
171 /* calculate (divisor_a+1) x (divisor_b+1) */
172 temp = input_clk / (22 * fscl);
175 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
176 * the fscl input is out of range. Return error.
178 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
182 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
183 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
185 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
189 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
191 if (actual_fscl > fscl)
194 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
195 (fscl - actual_fscl));
197 if (last_error > current_error) {
200 best_fscl = actual_fscl;
201 last_error = current_error;
212 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
214 struct i2c_cdns_bus *bus = dev_get_priv(dev);
215 u32 div_a = 0, div_b = 0;
216 unsigned long speed_p = speed;
219 if (speed > I2C_SPEED_FAST_RATE) {
220 debug("%s, failed to set clock speed to %u\n", __func__,
225 ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
229 debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
230 __func__, div_a, div_b, bus->input_freq, speed, speed_p);
232 writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
233 (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
235 /* Enable master mode, ack, and 7-bit addressing */
236 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
237 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
242 static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
244 return (readl(®s->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
247 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
251 struct cdns_i2c_regs *regs = i2c_bus->regs;
254 /* Set the controller in Master transmit mode and clear FIFO */
255 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
256 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
258 /* Check message size against FIFO depth, and set hold bus bit
259 * if it is greater than FIFO depth
261 if (len > CDNS_I2C_FIFO_DEPTH)
262 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
264 /* Clear the interrupts in status register */
265 writel(CDNS_I2C_INTERRUPTS_MASK, ®s->interrupt_status);
267 writel(addr, ®s->address);
269 while (len-- && !is_arbitration_lost(regs)) {
270 writel(*(cur_data++), ®s->data);
271 if (len && readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
272 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
273 CDNS_I2C_INTERRUPT_ARBLOST);
274 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
276 if (ret & CDNS_I2C_INTERRUPT_COMP)
278 /* Release the bus */
279 clrbits_le32(®s->control,
280 CDNS_I2C_CONTROL_HOLD);
285 if (len && is_arbitration_lost(regs))
288 /* All done... release the bus */
289 if (!i2c_bus->hold_flag)
290 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
292 /* Wait for the address and data to be sent */
293 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
294 CDNS_I2C_INTERRUPT_ARBLOST);
295 if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
296 CDNS_I2C_INTERRUPT_COMP)))
298 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
304 static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
306 return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
309 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
313 struct cdns_i2c_regs *regs = i2c_bus->regs;
315 int updatetx, hold_quirk;
318 curr_recv_count = recv_count;
320 /* Check for the message size against the FIFO depth */
321 if (recv_count > CDNS_I2C_FIFO_DEPTH)
322 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
324 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
325 CDNS_I2C_CONTROL_RW);
327 if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
328 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
329 writel(curr_recv_count, ®s->transfer_size);
331 writel(recv_count, ®s->transfer_size);
334 /* Start reading data */
335 writel(addr, ®s->address);
337 updatetx = recv_count > curr_recv_count;
339 hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
341 while (recv_count && !is_arbitration_lost(regs)) {
342 while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
343 if (recv_count < CDNS_I2C_FIFO_DEPTH &&
344 !i2c_bus->hold_flag) {
345 clrbits_le32(®s->control,
346 CDNS_I2C_CONTROL_HOLD);
348 *(cur_data)++ = readl(®s->data);
352 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
356 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
357 /* wait while fifo is full */
358 while (readl(®s->transfer_size) !=
359 (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
362 * Check number of bytes to be received against maximum
363 * transfer size and update register accordingly.
365 if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
366 CDNS_I2C_TRANSFER_SIZE) {
367 writel(CDNS_I2C_TRANSFER_SIZE,
368 ®s->transfer_size);
369 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
372 writel(recv_count - CDNS_I2C_FIFO_DEPTH,
373 ®s->transfer_size);
374 curr_recv_count = recv_count;
376 } else if (recv_count && !hold_quirk && !curr_recv_count) {
377 writel(addr, ®s->address);
378 if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
379 writel(CDNS_I2C_TRANSFER_SIZE,
380 ®s->transfer_size);
381 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
383 writel(recv_count, ®s->transfer_size);
384 curr_recv_count = recv_count;
389 /* Wait for the address and data to be sent */
390 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
391 CDNS_I2C_INTERRUPT_ARBLOST);
392 if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
393 CDNS_I2C_INTERRUPT_COMP)))
395 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
401 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
404 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
408 struct i2c_msg *message = msg;
409 int num_msgs = nmsgs;
411 hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
415 * This controller does not give completion interrupt after a
416 * master receive message if HOLD bit is set (repeated start),
417 * resulting in SW timeout. Hence, if a receive message is
418 * followed by any other message, an error is returned
419 * indicating that this sequence is not supported.
421 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
422 if (msg[count].flags & I2C_M_RD) {
423 printf("Can't do repeated start after a receive message\n");
428 i2c_bus->hold_flag = 1;
429 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
431 i2c_bus->hold_flag = 0;
434 debug("i2c_xfer: %d messages\n", nmsgs);
435 for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
436 nmsgs > 0; nmsgs--, msg++) {
437 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
438 if (msg->flags & I2C_M_RD) {
439 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
442 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
445 if (ret == -EAGAIN) {
449 printf("%s,arbitration lost, retrying:%d\n", __func__,
455 debug("i2c_write: error sending\n");
463 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
465 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
466 struct cdns_i2c_platform_data *pdata =
467 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
471 i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
476 i2c_bus->quirks = pdata->quirks;
478 ret = clk_get_by_index(dev, 0, &clk);
482 i2c_bus->input_freq = clk_get_rate(&clk);
487 static const struct dm_i2c_ops cdns_i2c_ops = {
488 .xfer = cdns_i2c_xfer,
489 .set_bus_speed = cdns_i2c_set_bus_speed,
492 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
493 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
496 static const struct udevice_id cdns_i2c_of_match[] = {
497 { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
498 { .compatible = "cdns,i2c-r1p14" },
499 { /* end of table */ }
502 U_BOOT_DRIVER(cdns_i2c) = {
505 .of_match = cdns_i2c_of_match,
506 .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
507 .priv_auto = sizeof(struct i2c_cdns_bus),
508 .ops = &cdns_i2c_ops,