drivers/i2c/i2c-cdns.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
   4  * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   5  *
   6  * This file is based on: drivers/i2c/zynq_i2c.c,
   7  * with added driver-model support and code cleanup.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <linux/errno.h>
  15 #include <dm/root.h>
  16 #include <i2c.h>
  17 #include <fdtdec.h>
  18 #include <mapmem.h>
  19 #include <wait_bit.h>
  20 #include <clk.h>
  21
  22 /* i2c register set */
  23 struct cdns_i2c_regs {
  24         u32 control;
  25         u32 status;
  26         u32 address;
  27         u32 data;
  28         u32 interrupt_status;
  29         u32 transfer_size;
  30         u32 slave_mon_pause;
  31         u32 time_out;
  32         u32 interrupt_mask;
  33         u32 interrupt_enable;
  34         u32 interrupt_disable;
  35 };
  36
  37 /* Control register fields */
  38 #define CDNS_I2C_CONTROL_RW             0x00000001
  39 #define CDNS_I2C_CONTROL_MS             0x00000002
  40 #define CDNS_I2C_CONTROL_NEA            0x00000004
  41 #define CDNS_I2C_CONTROL_ACKEN          0x00000008
  42 #define CDNS_I2C_CONTROL_HOLD           0x00000010
  43 #define CDNS_I2C_CONTROL_SLVMON         0x00000020
  44 #define CDNS_I2C_CONTROL_CLR_FIFO       0x00000040
  45 #define CDNS_I2C_CONTROL_DIV_B_SHIFT    8
  46 #define CDNS_I2C_CONTROL_DIV_B_MASK     0x00003F00
  47 #define CDNS_I2C_CONTROL_DIV_A_SHIFT    14
  48 #define CDNS_I2C_CONTROL_DIV_A_MASK     0x0000C000
  49
  50 /* Status register values */
  51 #define CDNS_I2C_STATUS_RXDV    0x00000020
  52 #define CDNS_I2C_STATUS_TXDV    0x00000040
  53 #define CDNS_I2C_STATUS_RXOVF   0x00000080
  54 #define CDNS_I2C_STATUS_BA      0x00000100
  55
  56 /* Interrupt register fields */
  57 #define CDNS_I2C_INTERRUPT_COMP         0x00000001
  58 #define CDNS_I2C_INTERRUPT_DATA         0x00000002
  59 #define CDNS_I2C_INTERRUPT_NACK         0x00000004
  60 #define CDNS_I2C_INTERRUPT_TO           0x00000008
  61 #define CDNS_I2C_INTERRUPT_SLVRDY       0x00000010
  62 #define CDNS_I2C_INTERRUPT_RXOVF        0x00000020
  63 #define CDNS_I2C_INTERRUPT_TXOVF        0x00000040
  64 #define CDNS_I2C_INTERRUPT_RXUNF        0x00000080
  65 #define CDNS_I2C_INTERRUPT_ARBLOST      0x00000200
  66
  67 #define CDNS_I2C_INTERRUPTS_MASK        (CDNS_I2C_INTERRUPT_COMP | \
  68                                         CDNS_I2C_INTERRUPT_DATA | \
  69                                         CDNS_I2C_INTERRUPT_NACK | \
  70                                         CDNS_I2C_INTERRUPT_TO | \
  71                                         CDNS_I2C_INTERRUPT_SLVRDY | \
  72                                         CDNS_I2C_INTERRUPT_RXOVF | \
  73                                         CDNS_I2C_INTERRUPT_TXOVF | \
  74                                         CDNS_I2C_INTERRUPT_RXUNF | \
  75                                         CDNS_I2C_INTERRUPT_ARBLOST)
  76
  77 #define CDNS_I2C_FIFO_DEPTH             16
  78 #define CDNS_I2C_TRANSFER_SIZE_MAX      255 /* Controller transfer limit */
  79 #define CDNS_I2C_TRANSFER_SIZE          (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
  80
  81 #define CDNS_I2C_BROKEN_HOLD_BIT        BIT(0)
  82
  83 #define CDNS_I2C_ARB_LOST_MAX_RETRIES   10
  84
  85 #ifdef DEBUG
  86 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
  87 {
  88         int int_status;
  89         int status;
  90         int_status = readl(&cdns_i2c->interrupt_status);
  91
  92         status = readl(&cdns_i2c->status);
  93         if (int_status || status) {
  94                 debug("Status: ");
  95                 if (int_status & CDNS_I2C_INTERRUPT_COMP)
  96                         debug("COMP ");
  97                 if (int_status & CDNS_I2C_INTERRUPT_DATA)
  98                         debug("DATA ");
  99                 if (int_status & CDNS_I2C_INTERRUPT_NACK)
 100                         debug("NACK ");
 101                 if (int_status & CDNS_I2C_INTERRUPT_TO)
 102                         debug("TO ");
 103                 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
 104                         debug("SLVRDY ");
 105                 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
 106                         debug("RXOVF ");
 107                 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
 108                         debug("TXOVF ");
 109                 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
 110                         debug("RXUNF ");
 111                 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
 112                         debug("ARBLOST ");
 113                 if (status & CDNS_I2C_STATUS_RXDV)
 114                         debug("RXDV ");
 115                 if (status & CDNS_I2C_STATUS_TXDV)
 116                         debug("TXDV ");
 117                 if (status & CDNS_I2C_STATUS_RXOVF)
 118                         debug("RXOVF ");
 119                 if (status & CDNS_I2C_STATUS_BA)
 120                         debug("BA ");
 121                 debug("TS%d ", readl(&cdns_i2c->transfer_size));
 122                 debug("\n");
 123         }
 124 }
 125 #endif
 126
 127 struct i2c_cdns_bus {
 128         int id;
 129         unsigned int input_freq;
 130         struct cdns_i2c_regs __iomem *regs;     /* register base */
 131
 132         int hold_flag;
 133         u32 quirks;
 134 };
 135
 136 struct cdns_i2c_platform_data {
 137         u32 quirks;
 138 };
 139
 140 /* Wait for an interrupt */
 141 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 142 {
 143         int timeout, int_status;
 144
 145         for (timeout = 0; timeout < 100; timeout++) {
 146                 int_status = readl(&cdns_i2c->interrupt_status);
 147                 if (int_status & mask)
 148                         break;
 149                 udelay(100);
 150         }
 151
 152         /* Clear interrupt status flags */
 153         writel(int_status & mask, &cdns_i2c->interrupt_status);
 154
 155         return int_status & mask;
 156 }
 157
 158 #define CDNS_I2C_DIVA_MAX       4
 159 #define CDNS_I2C_DIVB_MAX       64
 160
 161 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
 162                 unsigned int *a, unsigned int *b)
 163 {
 164         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
 165         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
 166         unsigned int last_error, current_error;
 167
 168         /* calculate (divisor_a+1) x (divisor_b+1) */
 169         temp = input_clk / (22 * fscl);
 170
 171         /*
 172          * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
 173          * the fscl input is out of range. Return error.
 174          */
 175         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
 176                 return -EINVAL;
 177
 178         last_error = -1;
 179         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
 180                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
 181
 182                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
 183                         continue;
 184                 div_b--;
 185
 186                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
 187
 188                 if (actual_fscl > fscl)
 189                         continue;
 190
 191                 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
 192                                                         (fscl - actual_fscl));
 193
 194                 if (last_error > current_error) {
 195                         calc_div_a = div_a;
 196                         calc_div_b = div_b;
 197                         best_fscl = actual_fscl;
 198                         last_error = current_error;
 199                 }
 200         }
 201
 202         *a = calc_div_a;
 203         *b = calc_div_b;
 204         *f = best_fscl;
 205
 206         return 0;
 207 }
 208
 209 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 210 {
 211         struct i2c_cdns_bus *bus = dev_get_priv(dev);
 212         u32 div_a = 0, div_b = 0;
 213         unsigned long speed_p = speed;
 214         int ret = 0;
 215
 216         if (speed > 400000) {
 217                 debug("%s, failed to set clock speed to %u\n", __func__,
 218                       speed);
 219                 return -EINVAL;
 220         }
 221
 222         ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
 223         if (ret)
 224                 return ret;
 225
 226         debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
 227               __func__, div_a, div_b, bus->input_freq, speed, speed_p);
 228
 229         writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
 230                (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
 231
 232         /* Enable master mode, ack, and 7-bit addressing */
 233         setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
 234                 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
 235
 236         return 0;
 237 }
 238
 239 static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
 240 {
 241         return (readl(&regs->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
 242 }
 243
 244 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 245                                u32 len)
 246 {
 247         u8 *cur_data = data;
 248         struct cdns_i2c_regs *regs = i2c_bus->regs;
 249         u32 ret;
 250
 251         /* Set the controller in Master transmit mode and clear FIFO */
 252         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
 253         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
 254
 255         /* Check message size against FIFO depth, and set hold bus bit
 256          * if it is greater than FIFO depth
 257          */
 258         if (len > CDNS_I2C_FIFO_DEPTH)
 259                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 260
 261         /* Clear the interrupts in status register */
 262         writel(CDNS_I2C_INTERRUPTS_MASK, &regs->interrupt_status);
 263
 264         writel(addr, &regs->address);
 265
 266         while (len-- && !is_arbitration_lost(regs)) {
 267                 writel(*(cur_data++), &regs->data);
 268                 if (readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
 269                         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 270                                             CDNS_I2C_INTERRUPT_ARBLOST);
 271                         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 272                                 return -EAGAIN;
 273                         if (ret & CDNS_I2C_INTERRUPT_COMP)
 274                                 continue;
 275                         /* Release the bus */
 276                         clrbits_le32(&regs->control,
 277                                      CDNS_I2C_CONTROL_HOLD);
 278                         return -ETIMEDOUT;
 279                 }
 280         }
 281
 282         if (len && is_arbitration_lost(regs))
 283                 return -EAGAIN;
 284
 285         /* All done... release the bus */
 286         if (!i2c_bus->hold_flag)
 287                 clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 288
 289         /* Wait for the address and data to be sent */
 290         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 291                             CDNS_I2C_INTERRUPT_ARBLOST);
 292         if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
 293                      CDNS_I2C_INTERRUPT_COMP)))
 294                 return -ETIMEDOUT;
 295         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 296                 return -EAGAIN;
 297
 298         return 0;
 299 }
 300
 301 static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
 302 {
 303         return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
 304 }
 305
 306 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 307                               u32 recv_count)
 308 {
 309         u8 *cur_data = data;
 310         struct cdns_i2c_regs *regs = i2c_bus->regs;
 311         u32 curr_recv_count;
 312         int updatetx, hold_quirk;
 313         u32 ret;
 314
 315         curr_recv_count = recv_count;
 316
 317         /* Check for the message size against the FIFO depth */
 318         if (recv_count > CDNS_I2C_FIFO_DEPTH)
 319                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 320
 321         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
 322                 CDNS_I2C_CONTROL_RW);
 323
 324         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 325                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 326                 writel(curr_recv_count, &regs->transfer_size);
 327         } else {
 328                 writel(recv_count, &regs->transfer_size);
 329         }
 330
 331         /* Start reading data */
 332         writel(addr, &regs->address);
 333
 334         updatetx = recv_count > curr_recv_count;
 335
 336         hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
 337
 338         while (recv_count && !is_arbitration_lost(regs)) {
 339                 while (readl(&regs->status) & CDNS_I2C_STATUS_RXDV) {
 340                         if (recv_count < CDNS_I2C_FIFO_DEPTH &&
 341                             !i2c_bus->hold_flag) {
 342                                 clrbits_le32(&regs->control,
 343                                              CDNS_I2C_CONTROL_HOLD);
 344                         }
 345                         *(cur_data)++ = readl(&regs->data);
 346                         recv_count--;
 347                         curr_recv_count--;
 348
 349                         if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
 350                                 break;
 351                 }
 352
 353                 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
 354                         /* wait while fifo is full */
 355                         while (readl(&regs->transfer_size) !=
 356                                      (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
 357                                 ;
 358                         /*
 359                          * Check number of bytes to be received against maximum
 360                          * transfer size and update register accordingly.
 361                          */
 362                         if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
 363                             CDNS_I2C_TRANSFER_SIZE) {
 364                                 writel(CDNS_I2C_TRANSFER_SIZE,
 365                                        &regs->transfer_size);
 366                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
 367                                         CDNS_I2C_FIFO_DEPTH;
 368                         } else {
 369                                 writel(recv_count - CDNS_I2C_FIFO_DEPTH,
 370                                        &regs->transfer_size);
 371                                 curr_recv_count = recv_count;
 372                         }
 373                 } else if (recv_count && !hold_quirk && !curr_recv_count) {
 374                         writel(addr, &regs->address);
 375                         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 376                                 writel(CDNS_I2C_TRANSFER_SIZE,
 377                                        &regs->transfer_size);
 378                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 379                         } else {
 380                                 writel(recv_count, &regs->transfer_size);
 381                                 curr_recv_count = recv_count;
 382                         }
 383                 }
 384         }
 385
 386         /* Wait for the address and data to be sent */
 387         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 388                             CDNS_I2C_INTERRUPT_ARBLOST);
 389         if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
 390                      CDNS_I2C_INTERRUPT_COMP)))
 391                 return -ETIMEDOUT;
 392         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 393                 return -EAGAIN;
 394
 395         return 0;
 396 }
 397
 398 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 399                          int nmsgs)
 400 {
 401         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 402         int ret = 0;
 403         int count;
 404         bool hold_quirk;
 405         struct i2c_msg *message = msg;
 406         int num_msgs = nmsgs;
 407
 408         hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
 409
 410         if (nmsgs > 1) {
 411                 /*
 412                  * This controller does not give completion interrupt after a
 413                  * master receive message if HOLD bit is set (repeated start),
 414                  * resulting in SW timeout. Hence, if a receive message is
 415                  * followed by any other message, an error is returned
 416                  * indicating that this sequence is not supported.
 417                  */
 418                 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
 419                         if (msg[count].flags & I2C_M_RD) {
 420                                 printf("Can't do repeated start after a receive message\n");
 421                                 return -EOPNOTSUPP;
 422                         }
 423                 }
 424
 425                 i2c_bus->hold_flag = 1;
 426                 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
 427         } else {
 428                 i2c_bus->hold_flag = 0;
 429         }
 430
 431         debug("i2c_xfer: %d messages\n", nmsgs);
 432         for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
 433              nmsgs > 0; nmsgs--, msg++) {
 434                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 435                 if (msg->flags & I2C_M_RD) {
 436                         ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
 437                                                  msg->len);
 438                 } else {
 439                         ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
 440                                                   msg->len);
 441                 }
 442                 if (ret == -EAGAIN) {
 443                         msg = message;
 444                         nmsgs = num_msgs;
 445                         retry++;
 446                         printf("%s,arbitration lost, retrying:%d\n", __func__,
 447                                retry);
 448                         continue;
 449                 }
 450
 451                 if (ret) {
 452                         debug("i2c_write: error sending\n");
 453                         return -EREMOTEIO;
 454                 }
 455         }
 456
 457         return ret;
 458 }
 459
 460 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 461 {
 462         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 463         struct cdns_i2c_platform_data *pdata =
 464                 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
 465         struct clk clk;
 466         int ret;
 467
 468         i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
 469         if (!i2c_bus->regs)
 470                 return -ENOMEM;
 471
 472         if (pdata)
 473                 i2c_bus->quirks = pdata->quirks;
 474
 475         ret = clk_get_by_index(dev, 0, &clk);
 476         if (ret)
 477                 return ret;
 478
 479         i2c_bus->input_freq = clk_get_rate(&clk);
 480
 481         return 0;
 482 }
 483
 484 static const struct dm_i2c_ops cdns_i2c_ops = {
 485         .xfer = cdns_i2c_xfer,
 486         .set_bus_speed = cdns_i2c_set_bus_speed,
 487 };
 488
 489 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
 490         .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
 491 };
 492
 493 static const struct udevice_id cdns_i2c_of_match[] = {
 494         { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
 495         { .compatible = "cdns,i2c-r1p14" },
 496         { /* end of table */ }
 497 };
 498
 499 U_BOOT_DRIVER(cdns_i2c) = {
 500         .name = "i2c-cdns",
 501         .id = UCLASS_I2C,
 502         .of_match = cdns_i2c_of_match,
 503         .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
 504         .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
 505         .ops = &cdns_i2c_ops,
 506 };