drivers/i2c/i2c-cdns.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
   4  * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   5  *
   6  * This file is based on: drivers/i2c/zynq_i2c.c,
   7  * with added driver-model support and code cleanup.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <log.h>
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/types.h>
  16 #include <linux/io.h>
  17 #include <linux/errno.h>
  18 #include <dm/device_compat.h>
  19 #include <dm/root.h>
  20 #include <i2c.h>
  21 #include <fdtdec.h>
  22 #include <mapmem.h>
  23 #include <wait_bit.h>
  24 #include <clk.h>
  25
  26 /* i2c register set */
  27 struct cdns_i2c_regs {
  28         u32 control;
  29         u32 status;
  30         u32 address;
  31         u32 data;
  32         u32 interrupt_status;
  33         u32 transfer_size;
  34         u32 slave_mon_pause;
  35         u32 time_out;
  36         u32 interrupt_mask;
  37         u32 interrupt_enable;
  38         u32 interrupt_disable;
  39 };
  40
  41 /* Control register fields */
  42 #define CDNS_I2C_CONTROL_RW             0x00000001
  43 #define CDNS_I2C_CONTROL_MS             0x00000002
  44 #define CDNS_I2C_CONTROL_NEA            0x00000004
  45 #define CDNS_I2C_CONTROL_ACKEN          0x00000008
  46 #define CDNS_I2C_CONTROL_HOLD           0x00000010
  47 #define CDNS_I2C_CONTROL_SLVMON         0x00000020
  48 #define CDNS_I2C_CONTROL_CLR_FIFO       0x00000040
  49 #define CDNS_I2C_CONTROL_DIV_B_SHIFT    8
  50 #define CDNS_I2C_CONTROL_DIV_B_MASK     0x00003F00
  51 #define CDNS_I2C_CONTROL_DIV_A_SHIFT    14
  52 #define CDNS_I2C_CONTROL_DIV_A_MASK     0x0000C000
  53
  54 /* Status register values */
  55 #define CDNS_I2C_STATUS_RXDV    0x00000020
  56 #define CDNS_I2C_STATUS_TXDV    0x00000040
  57 #define CDNS_I2C_STATUS_RXOVF   0x00000080
  58 #define CDNS_I2C_STATUS_BA      0x00000100
  59
  60 /* Interrupt register fields */
  61 #define CDNS_I2C_INTERRUPT_COMP         0x00000001
  62 #define CDNS_I2C_INTERRUPT_DATA         0x00000002
  63 #define CDNS_I2C_INTERRUPT_NACK         0x00000004
  64 #define CDNS_I2C_INTERRUPT_TO           0x00000008
  65 #define CDNS_I2C_INTERRUPT_SLVRDY       0x00000010
  66 #define CDNS_I2C_INTERRUPT_RXOVF        0x00000020
  67 #define CDNS_I2C_INTERRUPT_TXOVF        0x00000040
  68 #define CDNS_I2C_INTERRUPT_RXUNF        0x00000080
  69 #define CDNS_I2C_INTERRUPT_ARBLOST      0x00000200
  70
  71 #define CDNS_I2C_INTERRUPTS_MASK        (CDNS_I2C_INTERRUPT_COMP | \
  72                                         CDNS_I2C_INTERRUPT_DATA | \
  73                                         CDNS_I2C_INTERRUPT_NACK | \
  74                                         CDNS_I2C_INTERRUPT_TO | \
  75                                         CDNS_I2C_INTERRUPT_SLVRDY | \
  76                                         CDNS_I2C_INTERRUPT_RXOVF | \
  77                                         CDNS_I2C_INTERRUPT_TXOVF | \
  78                                         CDNS_I2C_INTERRUPT_RXUNF | \
  79                                         CDNS_I2C_INTERRUPT_ARBLOST)
  80
  81 #define CDNS_I2C_FIFO_DEPTH             16
  82 #define CDNS_I2C_TRANSFER_SIZE_MAX      255 /* Controller transfer limit */
  83 #define CDNS_I2C_TRANSFER_SIZE          (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
  84
  85 #define CDNS_I2C_BROKEN_HOLD_BIT        BIT(0)
  86
  87 #define CDNS_I2C_ARB_LOST_MAX_RETRIES   10
  88
  89 #ifdef DEBUG
  90 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
  91 {
  92         int int_status;
  93         int status;
  94         int_status = readl(&cdns_i2c->interrupt_status);
  95
  96         status = readl(&cdns_i2c->status);
  97         if (int_status || status) {
  98                 debug("Status: ");
  99                 if (int_status & CDNS_I2C_INTERRUPT_COMP)
 100                         debug("COMP ");
 101                 if (int_status & CDNS_I2C_INTERRUPT_DATA)
 102                         debug("DATA ");
 103                 if (int_status & CDNS_I2C_INTERRUPT_NACK)
 104                         debug("NACK ");
 105                 if (int_status & CDNS_I2C_INTERRUPT_TO)
 106                         debug("TO ");
 107                 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
 108                         debug("SLVRDY ");
 109                 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
 110                         debug("RXOVF ");
 111                 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
 112                         debug("TXOVF ");
 113                 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
 114                         debug("RXUNF ");
 115                 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
 116                         debug("ARBLOST ");
 117                 if (status & CDNS_I2C_STATUS_RXDV)
 118                         debug("RXDV ");
 119                 if (status & CDNS_I2C_STATUS_TXDV)
 120                         debug("TXDV ");
 121                 if (status & CDNS_I2C_STATUS_RXOVF)
 122                         debug("RXOVF ");
 123                 if (status & CDNS_I2C_STATUS_BA)
 124                         debug("BA ");
 125                 debug("TS%d ", readl(&cdns_i2c->transfer_size));
 126                 debug("\n");
 127         }
 128 }
 129 #endif
 130
 131 struct i2c_cdns_bus {
 132         int id;
 133         unsigned int input_freq;
 134         struct cdns_i2c_regs __iomem *regs;     /* register base */
 135
 136         int hold_flag;
 137         u32 quirks;
 138 };
 139
 140 struct cdns_i2c_platform_data {
 141         u32 quirks;
 142 };
 143
 144 /* Wait for an interrupt */
 145 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 146 {
 147         int timeout, int_status;
 148
 149         for (timeout = 0; timeout < 100; timeout++) {
 150                 int_status = readl(&cdns_i2c->interrupt_status);
 151                 if (int_status & mask)
 152                         break;
 153                 udelay(100);
 154         }
 155
 156         /* Clear interrupt status flags */
 157         writel(int_status & mask, &cdns_i2c->interrupt_status);
 158
 159         return int_status & mask;
 160 }
 161
 162 #define CDNS_I2C_DIVA_MAX       4
 163 #define CDNS_I2C_DIVB_MAX       64
 164
 165 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
 166                 unsigned int *a, unsigned int *b)
 167 {
 168         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
 169         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
 170         unsigned int last_error, current_error;
 171
 172         /* calculate (divisor_a+1) x (divisor_b+1) */
 173         temp = input_clk / (22 * fscl);
 174
 175         /*
 176          * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
 177          * the fscl input is out of range. Return error.
 178          */
 179         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
 180                 return -EINVAL;
 181
 182         last_error = -1;
 183         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
 184                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
 185
 186                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
 187                         continue;
 188                 div_b--;
 189
 190                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
 191
 192                 if (actual_fscl > fscl)
 193                         continue;
 194
 195                 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
 196                                                         (fscl - actual_fscl));
 197
 198                 if (last_error > current_error) {
 199                         calc_div_a = div_a;
 200                         calc_div_b = div_b;
 201                         best_fscl = actual_fscl;
 202                         last_error = current_error;
 203                 }
 204         }
 205
 206         *a = calc_div_a;
 207         *b = calc_div_b;
 208         *f = best_fscl;
 209
 210         return 0;
 211 }
 212
 213 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 214 {
 215         struct i2c_cdns_bus *bus = dev_get_priv(dev);
 216         u32 div_a = 0, div_b = 0;
 217         unsigned long speed_p = speed;
 218         int ret = 0;
 219
 220         if (speed > I2C_SPEED_FAST_RATE) {
 221                 debug("%s, failed to set clock speed to %u\n", __func__,
 222                       speed);
 223                 return -EINVAL;
 224         }
 225
 226         ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
 227         if (ret)
 228                 return ret;
 229
 230         debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
 231               __func__, div_a, div_b, bus->input_freq, speed, speed_p);
 232
 233         writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
 234                (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
 235
 236         /* Enable master mode, ack, and 7-bit addressing */
 237         setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
 238                 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
 239
 240         return 0;
 241 }
 242
 243 static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
 244 {
 245         return (readl(&regs->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
 246 }
 247
 248 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 249                                u32 len)
 250 {
 251         u8 *cur_data = data;
 252         struct cdns_i2c_regs *regs = i2c_bus->regs;
 253         u32 ret;
 254         bool start = 1;
 255
 256         /* Set the controller in Master transmit mode and clear FIFO */
 257         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
 258         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
 259
 260         /*
 261          * For sequential data load hold the bus.
 262          */
 263         if (len > 1)
 264                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 265
 266         /* Clear the interrupts in status register */
 267         writel(CDNS_I2C_INTERRUPTS_MASK, &regs->interrupt_status);
 268
 269         /* In case of Probe (i.e no data), start the transfer */
 270         if (!len)
 271                 writel(addr, &regs->address);
 272
 273         while (len-- && !is_arbitration_lost(regs)) {
 274                 writel(*(cur_data++), &regs->data);
 275                 /* Trigger write only after loading data */
 276                 if (start) {
 277                         writel(addr, &regs->address);
 278                         start = 0;
 279                 }
 280                 if (len && readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
 281                         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 282                                             CDNS_I2C_INTERRUPT_ARBLOST);
 283                         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 284                                 return -EAGAIN;
 285                         if (ret & CDNS_I2C_INTERRUPT_COMP)
 286                                 continue;
 287                         /* Release the bus */
 288                         clrbits_le32(&regs->control,
 289                                      CDNS_I2C_CONTROL_HOLD);
 290                         return -ETIMEDOUT;
 291                 }
 292         }
 293
 294         if (len && is_arbitration_lost(regs))
 295                 return -EAGAIN;
 296
 297         /* All done... release the bus */
 298         if (!i2c_bus->hold_flag)
 299                 clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 300
 301         /* Wait for the address and data to be sent */
 302         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 303                             CDNS_I2C_INTERRUPT_ARBLOST);
 304         if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
 305                      CDNS_I2C_INTERRUPT_COMP)))
 306                 return -ETIMEDOUT;
 307         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 308                 return -EAGAIN;
 309
 310         return 0;
 311 }
 312
 313 static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
 314 {
 315         return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
 316 }
 317
 318 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 319                               u32 recv_count)
 320 {
 321         u8 *cur_data = data;
 322         struct cdns_i2c_regs *regs = i2c_bus->regs;
 323         u32 curr_recv_count;
 324         int updatetx, hold_quirk;
 325         u32 ret;
 326
 327         curr_recv_count = recv_count;
 328
 329         /* Check for the message size against the FIFO depth */
 330         if (recv_count > CDNS_I2C_FIFO_DEPTH)
 331                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 332
 333         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
 334                 CDNS_I2C_CONTROL_RW);
 335
 336         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 337                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 338                 writel(curr_recv_count, &regs->transfer_size);
 339         } else {
 340                 writel(recv_count, &regs->transfer_size);
 341         }
 342
 343         /* Start reading data */
 344         writel(addr, &regs->address);
 345
 346         updatetx = recv_count > curr_recv_count;
 347
 348         hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
 349
 350         while (recv_count && !is_arbitration_lost(regs)) {
 351                 while (readl(&regs->status) & CDNS_I2C_STATUS_RXDV) {
 352                         if (recv_count < CDNS_I2C_FIFO_DEPTH &&
 353                             !i2c_bus->hold_flag) {
 354                                 clrbits_le32(&regs->control,
 355                                              CDNS_I2C_CONTROL_HOLD);
 356                         }
 357                         *(cur_data)++ = readl(&regs->data);
 358                         recv_count--;
 359                         curr_recv_count--;
 360
 361                         if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
 362                                 break;
 363                 }
 364
 365                 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
 366                         /* wait while fifo is full */
 367                         while (readl(&regs->transfer_size) !=
 368                                      (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
 369                                 ;
 370                         /*
 371                          * Check number of bytes to be received against maximum
 372                          * transfer size and update register accordingly.
 373                          */
 374                         if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
 375                             CDNS_I2C_TRANSFER_SIZE) {
 376                                 writel(CDNS_I2C_TRANSFER_SIZE,
 377                                        &regs->transfer_size);
 378                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
 379                                         CDNS_I2C_FIFO_DEPTH;
 380                         } else {
 381                                 writel(recv_count - CDNS_I2C_FIFO_DEPTH,
 382                                        &regs->transfer_size);
 383                                 curr_recv_count = recv_count;
 384                         }
 385                 } else if (recv_count && !hold_quirk && !curr_recv_count) {
 386                         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 387                                 writel(CDNS_I2C_TRANSFER_SIZE,
 388                                        &regs->transfer_size);
 389                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 390                         } else {
 391                                 writel(recv_count, &regs->transfer_size);
 392                                 curr_recv_count = recv_count;
 393                         }
 394                         writel(addr, &regs->address);
 395                 }
 396         }
 397
 398         /* Wait for the address and data to be sent */
 399         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 400                             CDNS_I2C_INTERRUPT_ARBLOST);
 401         if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
 402                      CDNS_I2C_INTERRUPT_COMP)))
 403                 return -ETIMEDOUT;
 404         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 405                 return -EAGAIN;
 406
 407         return 0;
 408 }
 409
 410 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 411                          int nmsgs)
 412 {
 413         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 414         int ret = 0;
 415         int count;
 416         bool hold_quirk;
 417         struct i2c_msg *message = msg;
 418         int num_msgs = nmsgs;
 419
 420         hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
 421
 422         if (nmsgs > 1) {
 423                 /*
 424                  * This controller does not give completion interrupt after a
 425                  * master receive message if HOLD bit is set (repeated start),
 426                  * resulting in SW timeout. Hence, if a receive message is
 427                  * followed by any other message, an error is returned
 428                  * indicating that this sequence is not supported.
 429                  */
 430                 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
 431                         if (msg[count].flags & I2C_M_RD) {
 432                                 printf("Can't do repeated start after a receive message\n");
 433                                 return -EOPNOTSUPP;
 434                         }
 435                 }
 436
 437                 i2c_bus->hold_flag = 1;
 438                 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
 439         } else {
 440                 i2c_bus->hold_flag = 0;
 441         }
 442
 443         debug("i2c_xfer: %d messages\n", nmsgs);
 444         for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
 445              nmsgs > 0; nmsgs--, msg++) {
 446                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 447                 if (msg->flags & I2C_M_RD) {
 448                         ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
 449                                                  msg->len);
 450                 } else {
 451                         ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
 452                                                   msg->len);
 453                 }
 454                 if (ret == -EAGAIN) {
 455                         msg = message;
 456                         nmsgs = num_msgs;
 457                         retry++;
 458                         printf("%s,arbitration lost, retrying:%d\n", __func__,
 459                                retry);
 460                         continue;
 461                 }
 462
 463                 if (ret) {
 464                         debug("i2c_write: error sending\n");
 465                         return -EREMOTEIO;
 466                 }
 467         }
 468
 469         return ret;
 470 }
 471
 472 static int cdns_i2c_of_to_plat(struct udevice *dev)
 473 {
 474         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 475         struct cdns_i2c_platform_data *pdata =
 476                 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
 477         struct clk clk;
 478         int ret;
 479
 480         i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
 481         if (!i2c_bus->regs)
 482                 return -ENOMEM;
 483
 484         if (pdata)
 485                 i2c_bus->quirks = pdata->quirks;
 486
 487         ret = clk_get_by_index(dev, 0, &clk);
 488         if (ret)
 489                 return ret;
 490
 491         i2c_bus->input_freq = clk_get_rate(&clk);
 492
 493         ret = clk_enable(&clk);
 494         if (ret) {
 495                 dev_err(dev, "failed to enable clock\n");
 496                 return ret;
 497         }
 498
 499         return 0;
 500 }
 501
 502 static const struct dm_i2c_ops cdns_i2c_ops = {
 503         .xfer = cdns_i2c_xfer,
 504         .set_bus_speed = cdns_i2c_set_bus_speed,
 505 };
 506
 507 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
 508         .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
 509 };
 510
 511 static const struct udevice_id cdns_i2c_of_match[] = {
 512         { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
 513         { .compatible = "cdns,i2c-r1p14" },
 514         { /* end of table */ }
 515 };
 516
 517 U_BOOT_DRIVER(cdns_i2c) = {
 518         .name = "i2c_cdns",
 519         .id = UCLASS_I2C,
 520         .of_match = cdns_i2c_of_match,
 521         .of_to_plat = cdns_i2c_of_to_plat,
 522         .priv_auto      = sizeof(struct i2c_cdns_bus),
 523         .ops = &cdns_i2c_ops,
 524 };