1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2006,2009 Freescale Semiconductor, Inc.
5 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Changes for multibus/multiadapter I2C support.
11 #include <i2c.h> /* Functional interface */
14 #include <asm/global_data.h>
16 #include <asm/fsl_i2c.h> /* HW definitions */
20 #include <linux/delay.h>
22 /* The maximum number of microseconds we will wait until another master has
23 * released the bus. If not defined in the board header file, then use a
26 #ifndef CONFIG_I2C_MBB_TIMEOUT
27 #define CONFIG_I2C_MBB_TIMEOUT 100000
30 /* The maximum number of microseconds we will wait for a read or write
31 * operation to complete. If not defined in the board header file, then use a
34 #ifndef CONFIG_I2C_TIMEOUT
35 #define CONFIG_I2C_TIMEOUT 100000
38 #define I2C_READ_BIT 1
39 #define I2C_WRITE_BIT 0
41 DECLARE_GLOBAL_DATA_PTR;
44 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
47 #if !CONFIG_IS_ENABLED(DM_I2C)
48 static const struct fsl_i2c_base *i2c_base[4] = {
49 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
50 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
51 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
53 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
54 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
56 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
57 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
62 /* I2C speed map for a DFSR value of 1 */
66 * Map I2C frequency dividers to FDR and DFSR values
68 * This structure is used to define the elements of a table that maps I2C
69 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
70 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
71 * Sampling Rate (DFSR) registers.
73 * The actual table should be defined in the board file, and it must be called
74 * fsl_i2c_speed_map[].
76 * The last entry of the table must have a value of {-1, X}, where X is same
77 * FDR/DFSR values as the second-to-last entry. This guarantees that any
78 * search through the array will always find a match.
80 * The values of the divider must be in increasing numerical order, i.e.
81 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
83 * For this table, the values are based on a value of 1 for the DFSR
84 * register. See the application note AN2919 "Determining the I2C Frequency
85 * Divider Ratio for SCL"
87 * ColdFire I2C frequency dividers for FDR values are different from
88 * PowerPC. The protocol to use the I2C module is still the same.
89 * A different table is defined and are based on MCF5xxx user manual.
93 unsigned short divider;
95 } fsl_i2c_speed_map[] = {
96 {20, 32}, {22, 33}, {24, 34}, {26, 35},
97 {28, 0}, {28, 36}, {30, 1}, {32, 37},
98 {34, 2}, {36, 38}, {40, 3}, {40, 39},
99 {44, 4}, {48, 5}, {48, 40}, {56, 6},
100 {56, 41}, {64, 42}, {68, 7}, {72, 43},
101 {80, 8}, {80, 44}, {88, 9}, {96, 41},
102 {104, 10}, {112, 42}, {128, 11}, {128, 43},
103 {144, 12}, {160, 13}, {160, 48}, {192, 14},
104 {192, 49}, {224, 50}, {240, 15}, {256, 51},
105 {288, 16}, {320, 17}, {320, 52}, {384, 18},
106 {384, 53}, {448, 54}, {480, 19}, {512, 55},
107 {576, 20}, {640, 21}, {640, 56}, {768, 22},
108 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
109 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
110 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
111 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
117 * Set the I2C bus speed for a given I2C device
119 * @param base: the I2C device registers
120 * @i2c_clk: I2C bus clock frequency
121 * @speed: the desired speed of the bus
123 * The I2C device must be stopped before calling this function.
125 * The return value is the actual bus speed that is set.
127 static uint set_i2c_bus_speed(const struct fsl_i2c_base *base,
128 uint i2c_clk, uint speed)
130 ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);
133 * We want to choose an FDR/DFSR that generates an I2C bus speed that
134 * is equal to or lower than the requested speed. That means that we
135 * want the first divider that is equal to or greater than the
136 * calculated divider.
139 u8 dfsr, fdr = 0x31; /* Default if no FDR found */
140 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
142 ulong c_div, est_div;
144 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
145 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
147 /* Condition 1: dfsr <= 50/T */
148 dfsr = (5 * (i2c_clk / 1000)) / 100000;
150 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
151 fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
152 speed = i2c_clk / divider; /* Fake something */
154 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
159 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
160 for (gb = 0; gb < 8; gb++) {
162 c_div = b * (a + ((3 * dfsr) / b) * 2);
163 if (c_div > divider && c_div < est_div) {
164 ushort bin_gb, bin_ga;
168 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
169 fdr = bin_gb | bin_ga;
170 speed = i2c_clk / est_div;
172 debug("FDR: 0x%.2x, ", fdr);
173 debug("div: %ld, ", est_div);
174 debug("ga: 0x%x, gb: 0x%x, ", ga, gb);
175 debug("a: %d, b: %d, speed: %d\n", a, b, speed);
177 /* Condition 2 not accounted for */
178 debug("Tr <= %d ns\n",
179 (b - 3 * dfsr) * 1000000 /
188 debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr);
189 debug("FDR: 0x%.2x, speed: %d\n", fdr, speed);
191 writeb(dfsr, &base->dfsrr); /* set default filter */
192 writeb(fdr, &base->fdr); /* set bus speed */
196 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
197 if (fsl_i2c_speed_map[i].divider >= divider) {
200 fdr = fsl_i2c_speed_map[i].fdr;
201 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
202 writeb(fdr, &base->fdr); /* set bus speed */
210 #if !CONFIG_IS_ENABLED(DM_I2C)
211 static uint get_i2c_clock(int bus)
214 return gd->arch.i2c2_clk; /* I2C2 clock */
216 return gd->arch.i2c1_clk; /* I2C1 clock */
220 static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
222 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
223 unsigned long long timeval = 0;
227 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
228 uint svr = get_svr();
230 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
231 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
235 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
237 timeval = get_ticks();
238 while (!(readb(&base->sr) & I2C_SR_MBB)) {
239 if ((get_ticks() - timeval) > timeout)
243 if (readb(&base->sr) & I2C_SR_MAL) {
244 /* SDA is stuck low */
245 writeb(0, &base->cr);
247 writeb(I2C_CR_MSTA | flags, &base->cr);
248 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
253 timeval = get_ticks();
254 while (!(readb(&base->sr) & I2C_SR_MIF)) {
255 if ((get_ticks() - timeval) > timeout)
261 writeb(I2C_CR_MEN | flags, &base->cr);
262 writeb(0, &base->sr);
268 static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
269 slaveadd, int i2c_clk, int busnum)
271 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
272 unsigned long long timeval;
274 #ifdef CONFIG_SYS_I2C_INIT_BOARD
275 /* Call board specific i2c bus reset routine before accessing the
276 * environment, which might be in a chip on that bus. For details
277 * about this problem see doc/I2C_Edge_Conditions.
281 writeb(0, &base->cr); /* stop I2C controller */
282 udelay(5); /* let it shutdown in peace */
283 set_i2c_bus_speed(base, i2c_clk, speed);
284 writeb(slaveadd << 1, &base->adr);/* write slave address */
285 writeb(0x0, &base->sr); /* clear status register */
286 writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
288 timeval = get_ticks();
289 while (readb(&base->sr) & I2C_SR_MBB) {
290 if ((get_ticks() - timeval) < timeout)
293 if (fsl_i2c_fixup(base))
294 debug("i2c_init: BUS#%d failed to init\n",
301 static int i2c_wait4bus(const struct fsl_i2c_base *base)
303 unsigned long long timeval = get_ticks();
304 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
306 while (readb(&base->sr) & I2C_SR_MBB) {
307 if ((get_ticks() - timeval) > timeout)
314 static int i2c_wait(const struct fsl_i2c_base *base, int write)
317 unsigned long long timeval = get_ticks();
318 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
321 csr = readb(&base->sr);
322 if (!(csr & I2C_SR_MIF))
324 /* Read again to allow register to stabilise */
325 csr = readb(&base->sr);
327 writeb(0x0, &base->sr);
329 if (csr & I2C_SR_MAL) {
330 debug("%s: MAL\n", __func__);
334 if (!(csr & I2C_SR_MCF)) {
335 debug("%s: unfinished\n", __func__);
339 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
340 debug("%s: No RXACK\n", __func__);
345 } while ((get_ticks() - timeval) < timeout);
347 debug("%s: timed out\n", __func__);
351 static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
354 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
355 | (rsta ? I2C_CR_RSTA : 0),
358 writeb((dev << 1) | dir, &base->dr);
360 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
366 static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data,
371 for (i = 0; i < length; i++) {
372 writeb(data[i], &base->dr);
374 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
381 static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
386 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
392 for (i = 0; i < length; i++) {
393 if (i2c_wait(base, I2C_READ_BIT) < 0)
396 /* Generate ack on last next to last byte */
398 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
401 /* Do not generate stop on last byte */
403 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
406 data[i] = readb(&base->dr);
412 static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset,
413 int olen, u8 *data, int dlen)
415 int ret = -1; /* signal error */
417 if (i2c_wait4bus(base) < 0)
420 /* Some drivers use offset lengths in excess of 4 bytes. These drivers
421 * adhere to the following convention:
422 * - the offset length is passed as negative (that is, the absolute
423 * value of olen is the actual offset length)
424 * - the offset itself is passed in data, which is overwritten by the
425 * subsequent read operation
428 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
429 ret = __i2c_write_data(base, data, -olen);
434 if (dlen && i2c_write_addr(base, chip_addr,
435 I2C_READ_BIT, 1) != 0)
436 ret = __i2c_read_data(base, data, dlen);
438 if ((!dlen || olen > 0) &&
439 i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
440 __i2c_write_data(base, offset, olen) == olen)
441 ret = 0; /* No error so far */
443 if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
445 ret = __i2c_read_data(base, data, dlen);
448 writeb(I2C_CR_MEN, &base->cr);
450 if (i2c_wait4bus(base)) /* Wait until STOP */
451 debug("i2c_read: wait4bus timed out\n");
459 static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr,
460 u8 *offset, int olen, u8 *data, int dlen)
462 int ret = -1; /* signal error */
464 if (i2c_wait4bus(base) < 0)
467 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
468 __i2c_write_data(base, offset, olen) == olen) {
469 ret = __i2c_write_data(base, data, dlen);
472 writeb(I2C_CR_MEN, &base->cr);
473 if (i2c_wait4bus(base)) /* Wait until STOP */
474 debug("i2c_write: wait4bus timed out\n");
482 static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
484 /* For unknown reason the controller will ACK when
485 * probing for a slave with the same address, so skip
488 if (chip == (readb(&base->adr) >> 1))
491 return __i2c_read(base, chip, 0, 0, NULL, 0);
494 static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base,
495 uint speed, int i2c_clk)
497 writeb(0, &base->cr); /* stop controller */
498 set_i2c_bus_speed(base, i2c_clk, speed);
499 writeb(I2C_CR_MEN, &base->cr); /* start controller */
504 #if !CONFIG_IS_ENABLED(DM_I2C)
505 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
507 __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
508 get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
511 static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
513 return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
516 static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset,
517 int olen, u8 *data, int dlen)
519 u8 *o = (u8 *)&offset;
521 return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
525 static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset,
526 int olen, u8 *data, int dlen)
528 u8 *o = (u8 *)&offset;
530 return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
534 static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
536 return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
537 get_i2c_clock(adap->hwadapnr));
541 * Register fsl i2c adapters
543 U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
544 fsl_i2c_write, fsl_i2c_set_bus_speed,
545 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
547 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
548 U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
549 fsl_i2c_write, fsl_i2c_set_bus_speed,
550 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
553 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
554 U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
555 fsl_i2c_write, fsl_i2c_set_bus_speed,
556 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
559 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
560 U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
561 fsl_i2c_write, fsl_i2c_set_bus_speed,
562 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
565 #else /* CONFIG_DM_I2C */
566 static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
569 struct fsl_i2c_dev *dev = dev_get_priv(bus);
571 return __i2c_probe_chip(dev->base, chip_addr);
574 static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed)
576 struct fsl_i2c_dev *dev = dev_get_priv(bus);
578 return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
581 static int fsl_i2c_of_to_plat(struct udevice *bus)
583 struct fsl_i2c_dev *dev = dev_get_priv(bus);
586 dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base));
591 dev->index = dev_read_u32_default(bus, "cell-index", -1);
592 dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr",
594 dev->speed = dev_read_u32_default(bus, "clock-frequency",
595 I2C_SPEED_FAST_RATE);
597 if (!clk_get_by_index(bus, 0, &clock))
598 dev->i2c_clk = clk_get_rate(&clock);
600 dev->i2c_clk = dev->index ? gd->arch.i2c2_clk :
606 static int fsl_i2c_probe(struct udevice *bus)
608 struct fsl_i2c_dev *dev = dev_get_priv(bus);
610 __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
615 static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
617 struct fsl_i2c_dev *dev = dev_get_priv(bus);
618 struct i2c_msg *dmsg, *omsg, dummy;
620 memset(&dummy, 0, sizeof(struct i2c_msg));
622 /* We expect either two messages (one with an offset and one with the
623 * actual data) or one message (just data)
625 if (nmsgs > 2 || nmsgs == 0) {
626 debug("%s: Only one or two messages are supported.", __func__);
630 omsg = nmsgs == 1 ? &dummy : msg;
631 dmsg = nmsgs == 1 ? msg : msg + 1;
633 if (dmsg->flags & I2C_M_RD)
634 return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
635 dmsg->buf, dmsg->len);
637 return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
638 dmsg->buf, dmsg->len);
641 static const struct dm_i2c_ops fsl_i2c_ops = {
642 .xfer = fsl_i2c_xfer,
643 .probe_chip = fsl_i2c_probe_chip,
644 .set_bus_speed = fsl_i2c_set_bus_speed,
647 static const struct udevice_id fsl_i2c_ids[] = {
648 { .compatible = "fsl-i2c", },
652 U_BOOT_DRIVER(i2c_fsl) = {
655 .of_match = fsl_i2c_ids,
656 .probe = fsl_i2c_probe,
657 .of_to_plat = fsl_i2c_of_to_plat,
658 .priv_auto = sizeof(struct fsl_i2c_dev),
662 #endif /* CONFIG_DM_I2C */