2 * Copyright 2006 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #ifdef CONFIG_HARD_I2C
25 #include <i2c.h> /* Functional interface */
28 #include <asm/fsl_i2c.h> /* HW definitions */
30 #define I2C_TIMEOUT (CFG_HZ / 4)
32 #define I2C_READ_BIT 1
33 #define I2C_WRITE_BIT 0
35 DECLARE_GLOBAL_DATA_PTR;
37 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
38 * Default is bus 0. This is necessary because the DDR initialization
39 * runs from ROM, and we can't switch buses because we can't modify
40 * the global variables.
42 #ifdef CFG_SPD_BUS_NUM
43 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
45 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
48 static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED};
50 static const struct fsl_i2c *i2c_dev[2] = {
51 (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
52 #ifdef CFG_I2C2_OFFSET
53 (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
57 /* I2C speed map for a DFSR value of 1 */
60 * Map I2C frequency dividers to FDR and DFSR values
62 * This structure is used to define the elements of a table that maps I2C
63 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
64 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
65 * Sampling Rate (DFSR) registers.
67 * The actual table should be defined in the board file, and it must be called
68 * fsl_i2c_speed_map[].
70 * The last entry of the table must have a value of {-1, X}, where X is same
71 * FDR/DFSR values as the second-to-last entry. This guarantees that any
72 * search through the array will always find a match.
74 * The values of the divider must be in increasing numerical order, i.e.
75 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
77 * For this table, the values are based on a value of 1 for the DFSR
78 * register. See the application note AN2919 "Determining the I2C Frequency
79 * Divider Ratio for SCL"
82 unsigned short divider;
85 } fsl_i2c_speed_map[] = {
86 {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35},
87 {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2},
88 {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4},
89 {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3},
90 {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7},
91 {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9},
92 {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46},
93 {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12},
94 {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14},
95 {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16},
96 {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19},
97 {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22},
98 {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24},
99 {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27},
100 {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30},
101 {61440, 1, 31}, {-1, 1, 31}
105 * Set the I2C bus speed for a given I2C device
107 * @param dev: the I2C device
108 * @i2c_clk: I2C bus clock frequency
109 * @speed: the desired speed of the bus
111 * The I2C device must be stopped before calling this function.
113 * The return value is the actual bus speed that is set.
115 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
116 unsigned int i2c_clk, unsigned int speed)
118 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
122 * We want to choose an FDR/DFSR that generates an I2C bus speed that
123 * is equal to or lower than the requested speed. That means that we
124 * want the first divider that is equal to or greater than the
125 * calculated divider.
128 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
129 if (fsl_i2c_speed_map[i].divider >= divider) {
131 dfsr = fsl_i2c_speed_map[i].dfsr;
132 fdr = fsl_i2c_speed_map[i].fdr;
133 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
134 writeb(fdr, &dev->fdr); /* set bus speed */
135 writeb(dfsr, &dev->dfsrr); /* set default filter */
143 i2c_init(int speed, int slaveadd)
148 dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
150 writeb(0, &dev->cr); /* stop I2C controller */
151 udelay(5); /* let it shutdown in peace */
152 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
153 if (gd->flags & GD_FLG_RELOC)
154 i2c_bus_speed[0] = temp;
155 writeb(slaveadd << 1, &dev->adr); /* write slave address */
156 writeb(0x0, &dev->sr); /* clear status register */
157 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
159 #ifdef CFG_I2C2_OFFSET
160 dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
162 writeb(0, &dev->cr); /* stop I2C controller */
163 udelay(5); /* let it shutdown in peace */
164 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
165 if (gd->flags & GD_FLG_RELOC)
166 i2c_bus_speed[1] = temp;
167 writeb(slaveadd << 1, &dev->adr); /* write slave address */
168 writeb(0x0, &dev->sr); /* clear status register */
169 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
173 static __inline__ int
176 unsigned long long timeval = get_ticks();
178 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
179 if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT))
186 static __inline__ int
190 unsigned long long timeval = get_ticks();
193 csr = readb(&i2c_dev[i2c_bus_num]->sr);
194 if (!(csr & I2C_SR_MIF))
197 writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
199 if (csr & I2C_SR_MAL) {
200 debug("i2c_wait: MAL\n");
204 if (!(csr & I2C_SR_MCF)) {
205 debug("i2c_wait: unfinished\n");
209 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
210 debug("i2c_wait: No RXACK\n");
215 } while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT));
217 debug("i2c_wait: timed out\n");
221 static __inline__ int
222 i2c_write_addr (u8 dev, u8 dir, int rsta)
224 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
225 | (rsta ? I2C_CR_RSTA : 0),
226 &i2c_dev[i2c_bus_num]->cr);
228 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
230 if (i2c_wait(I2C_WRITE_BIT) < 0)
236 static __inline__ int
237 __i2c_write(u8 *data, int length)
241 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
242 &i2c_dev[i2c_bus_num]->cr);
244 for (i = 0; i < length; i++) {
245 writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
247 if (i2c_wait(I2C_WRITE_BIT) < 0)
254 static __inline__ int
255 __i2c_read(u8 *data, int length)
259 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
260 &i2c_dev[i2c_bus_num]->cr);
263 readb(&i2c_dev[i2c_bus_num]->dr);
265 for (i = 0; i < length; i++) {
266 if (i2c_wait(I2C_READ_BIT) < 0)
269 /* Generate ack on last next to last byte */
271 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
272 &i2c_dev[i2c_bus_num]->cr);
274 /* Generate stop on last byte */
276 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
278 data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
285 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
287 int i = -1; /* signal error */
290 if (i2c_wait4bus() >= 0
291 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
292 && __i2c_write(&a[4 - alen], alen) == alen)
293 i = 0; /* No error so far */
296 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
297 i = __i2c_read(data, length);
299 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
308 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
310 int i = -1; /* signal error */
313 if (i2c_wait4bus() >= 0
314 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
315 && __i2c_write(&a[4 - alen], alen) == alen) {
316 i = __i2c_write(data, length);
319 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
328 i2c_probe(uchar chip)
330 /* For unknow reason the controller will ACK when
331 * probing for a slave with the same address, so skip
334 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
337 return i2c_read(chip, 0, 0, NULL, 0);
341 i2c_reg_read(uchar i2c_addr, uchar reg)
345 i2c_read(i2c_addr, reg, 1, buf, 1);
351 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
353 i2c_write(i2c_addr, reg, 1, &val, 1);
356 int i2c_set_bus_num(unsigned int bus)
358 #ifdef CFG_I2C2_OFFSET
371 int i2c_set_bus_speed(unsigned int speed)
373 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
375 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
376 i2c_bus_speed[i2c_bus_num] =
377 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
378 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
383 unsigned int i2c_get_bus_num(void)
388 unsigned int i2c_get_bus_speed(void)
390 return i2c_bus_speed[i2c_bus_num];
393 #endif /* CONFIG_HARD_I2C */
394 #endif /* CONFIG_FSL_I2C */