drivers/i2c/designware_i2c_pci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  * Copyright 2019 Google Inc
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <spl.h>
  12 #include <acpi/acpigen.h>
  13 #include <acpi/acpi_device.h>
  14 #include <asm/lpss.h>
  15 #include <dm/acpi.h>
  16 #include <dm/device-internal.h>
  17 #include <dm/uclass-internal.h>
  18 #include "designware_i2c.h"
  19
  20 enum {
  21         VANILLA         = 0,    /* standard I2C with no tweaks */
  22         INTEL_APL,              /* Apollo Lake I2C */
  23 };
  24
  25 /* BayTrail HCNT/LCNT/SDA hold time */
  26 static struct dw_scl_sda_cfg byt_config = {
  27         .ss_hcnt = 0x200,
  28         .fs_hcnt = 0x55,
  29         .ss_lcnt = 0x200,
  30         .fs_lcnt = 0x99,
  31         .sda_hold = 0x6,
  32 };
  33
  34 /* Have a weak function for now - possibly should be a new uclass */
  35 __weak void lpss_reset_release(void *regs);
  36
  37 static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
  38 {
  39         struct dw_i2c *priv = dev_get_priv(dev);
  40
  41         if (spl_phase() < PHASE_SPL) {
  42                 u32 base;
  43                 int ret;
  44
  45                 ret = dev_read_u32(dev, "early-regs", &base);
  46                 if (ret)
  47                         return log_msg_ret("early-regs", ret);
  48
  49                 /* Set i2c base address */
  50                 dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
  51
  52                 /* Enable memory access and bus master */
  53                 dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
  54                                       PCI_COMMAND_MASTER);
  55         }
  56
  57         if (spl_phase() < PHASE_BOARD_F) {
  58                 /* Handle early, fixed mapping into a different address space */
  59                 priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
  60         } else {
  61                 priv->regs = (struct i2c_regs *)
  62                         dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
  63         }
  64         if (!priv->regs)
  65                 return -EINVAL;
  66
  67         /* Save base address from PCI BAR */
  68         if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
  69                 /* Use BayTrail specific timing values */
  70                 priv->scl_sda_cfg = &byt_config;
  71         if (dev_get_driver_data(dev) == INTEL_APL)
  72                 priv->has_spk_cnt = true;
  73
  74         return designware_i2c_ofdata_to_platdata(dev);
  75 }
  76
  77 static int designware_i2c_pci_probe(struct udevice *dev)
  78 {
  79         struct dw_i2c *priv = dev_get_priv(dev);
  80
  81         if (dev_get_driver_data(dev) == INTEL_APL) {
  82                 /* Ensure controller is in D0 state */
  83                 lpss_set_power_state(dev, STATE_D0);
  84
  85                 lpss_reset_release(priv->regs);
  86         }
  87
  88         return designware_i2c_probe(dev);
  89 }
  90
  91 static int designware_i2c_pci_bind(struct udevice *dev)
  92 {
  93         char name[20];
  94
  95         if (dev_of_valid(dev))
  96                 return 0;
  97
  98         /*
  99          * Create a unique device name for PCI type devices
 100          * ToDo:
 101          * Setting req_seq in the driver is probably not recommended.
 102          * But without a DT alias the number is not configured. And
 103          * using this driver is impossible for PCIe I2C devices.
 104          * This can be removed, once a better (correct) way for this
 105          * is found and implemented.
 106          *
 107          * TODO(sjg@chromium.org): Perhaps if uclasses had platdata this would
 108          * be possible. We cannot use static data in drivers since they may be
 109          * used in SPL or before relocation.
 110          */
 111         dev->req_seq = uclass_find_next_free_req_seq(UCLASS_I2C);
 112         sprintf(name, "i2c_designware#%u", dev->req_seq);
 113         device_set_name(dev, name);
 114
 115         return 0;
 116 }
 117
 118 /*
 119  * Write ACPI object to describe speed configuration.
 120  *
 121  * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
 122  *
 123  * SSCN: I2C_SPEED_STANDARD
 124  * FMCN: I2C_SPEED_FAST
 125  * FPCN: I2C_SPEED_FAST_PLUS
 126  * HSCN: I2C_SPEED_HIGH
 127  */
 128 static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
 129                                            struct dw_i2c_speed_config *config)
 130 {
 131         switch (config->speed_mode) {
 132         case IC_SPEED_MODE_HIGH:
 133                 acpigen_write_name(ctx, "HSCN");
 134                 break;
 135         case IC_SPEED_MODE_FAST_PLUS:
 136                 acpigen_write_name(ctx, "FPCN");
 137                 break;
 138         case IC_SPEED_MODE_FAST:
 139                 acpigen_write_name(ctx, "FMCN");
 140                 break;
 141         case IC_SPEED_MODE_STANDARD:
 142         default:
 143                 acpigen_write_name(ctx, "SSCN");
 144         }
 145
 146         /* Package () { scl_lcnt, scl_hcnt, sda_hold } */
 147         acpigen_write_package(ctx, 3);
 148         acpigen_write_word(ctx, config->scl_hcnt);
 149         acpigen_write_word(ctx, config->scl_lcnt);
 150         acpigen_write_dword(ctx, config->sda_hold);
 151         acpigen_pop_len(ctx);
 152 }
 153
 154 /*
 155  * Generate I2C timing information into the SSDT for the OS driver to consume,
 156  * optionally applying override values provided by the caller.
 157  */
 158 static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
 159                                  struct acpi_ctx *ctx)
 160 {
 161         struct dw_i2c_speed_config config;
 162         char path[ACPI_PATH_MAX];
 163         u32 speeds[4];
 164         uint speed;
 165         int size;
 166         int ret;
 167
 168         /* If no device-tree node, ignore this since we assume it isn't used */
 169         if (!dev_of_valid(dev))
 170                 return 0;
 171
 172         ret = acpi_device_path(dev, path, sizeof(path));
 173         if (ret)
 174                 return log_msg_ret("path", ret);
 175
 176         size = dev_read_size(dev, "i2c,speeds");
 177         if (size < 0)
 178                 return log_msg_ret("i2c,speeds", -EINVAL);
 179
 180         size /= sizeof(u32);
 181         if (size > ARRAY_SIZE(speeds))
 182                 return log_msg_ret("array", -E2BIG);
 183
 184         ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size);
 185         if (ret)
 186                 return log_msg_ret("read", -E2BIG);
 187
 188         speed = dev_read_u32_default(dev, "clock-frequency", 100000);
 189         acpigen_write_scope(ctx, path);
 190         ret = dw_i2c_gen_speed_config(dev, speed, &config);
 191         if (ret)
 192                 return log_msg_ret("config", ret);
 193         dw_i2c_acpi_write_speed_config(ctx, &config);
 194         acpigen_pop_len(ctx);
 195
 196         return 0;
 197 }
 198
 199 struct acpi_ops dw_i2c_acpi_ops = {
 200         .fill_ssdt      = dw_i2c_acpi_fill_ssdt,
 201 };
 202
 203 static const struct udevice_id designware_i2c_pci_ids[] = {
 204         { .compatible = "snps,designware-i2c-pci" },
 205         { .compatible = "intel,apl-i2c", .data = INTEL_APL },
 206         { }
 207 };
 208
 209 U_BOOT_DRIVER(i2c_designware_pci) = {
 210         .name   = "i2c_designware_pci",
 211         .id     = UCLASS_I2C,
 212         .of_match = designware_i2c_pci_ids,
 213         .bind   = designware_i2c_pci_bind,
 214         .ofdata_to_platdata     = designware_i2c_pci_ofdata_to_platdata,
 215         .probe  = designware_i2c_pci_probe,
 216         .priv_auto      = sizeof(struct dw_i2c),
 217         .remove = designware_i2c_remove,
 218         .flags = DM_FLAG_OS_PREPARE,
 219         .ops    = &designware_i2c_ops,
 220         ACPI_OPS_PTR(&dw_i2c_acpi_ops)
 221 };
 222
 223 static struct pci_device_id designware_pci_supported[] = {
 224         /* Intel BayTrail has 7 I2C controller located on the PCI bus */
 225         { PCI_VDEVICE(INTEL, 0x0f41) },
 226         { PCI_VDEVICE(INTEL, 0x0f42) },
 227         { PCI_VDEVICE(INTEL, 0x0f43) },
 228         { PCI_VDEVICE(INTEL, 0x0f44) },
 229         { PCI_VDEVICE(INTEL, 0x0f45) },
 230         { PCI_VDEVICE(INTEL, 0x0f46) },
 231         { PCI_VDEVICE(INTEL, 0x0f47) },
 232         { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
 233         { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
 234         { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
 235         { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
 236         { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
 237         { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
 238         {},
 239 };
 240
 241 U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);