1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
5 * Copyright 2019 Google Inc
12 #include <acpi/acpigen.h>
13 #include <acpi/acpi_device.h>
16 #include <dm/device-internal.h>
17 #include <dm/uclass-internal.h>
18 #include "designware_i2c.h"
21 VANILLA = 0, /* standard I2C with no tweaks */
22 INTEL_APL, /* Apollo Lake I2C */
25 /* BayTrail HCNT/LCNT/SDA hold time */
26 static struct dw_scl_sda_cfg byt_config = {
34 /* Have a weak function for now - possibly should be a new uclass */
35 __weak void lpss_reset_release(void *regs);
37 static int designware_i2c_pci_of_to_plat(struct udevice *dev)
39 struct dw_i2c *priv = dev_get_priv(dev);
41 if (spl_phase() < PHASE_SPL) {
45 ret = dev_read_u32(dev, "early-regs", &base);
47 return log_msg_ret("early-regs", ret);
49 /* Set i2c base address */
50 dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
52 /* Enable memory access and bus master */
53 dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
57 if (spl_phase() < PHASE_BOARD_F) {
58 /* Handle early, fixed mapping into a different address space */
59 priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
61 priv->regs = (struct i2c_regs *)
62 dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
63 PCI_REGION_TYPE, PCI_REGION_MEM);
68 /* Save base address from PCI BAR */
69 if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
70 /* Use BayTrail specific timing values */
71 priv->scl_sda_cfg = &byt_config;
72 if (dev_get_driver_data(dev) == INTEL_APL)
73 priv->has_spk_cnt = true;
75 return designware_i2c_of_to_plat(dev);
78 static int designware_i2c_pci_probe(struct udevice *dev)
80 struct dw_i2c *priv = dev_get_priv(dev);
82 if (dev_get_driver_data(dev) == INTEL_APL) {
83 /* Ensure controller is in D0 state */
84 lpss_set_power_state(dev, STATE_D0);
86 lpss_reset_release(priv->regs);
89 return designware_i2c_probe(dev);
92 static int designware_i2c_pci_bind(struct udevice *dev)
96 if (dev_has_ofnode(dev))
99 sprintf(name, "i2c_designware#%u", dev_seq(dev));
100 device_set_name(dev, name);
106 * Write ACPI object to describe speed configuration.
108 * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
110 * SSCN: I2C_SPEED_STANDARD
111 * FMCN: I2C_SPEED_FAST
112 * FPCN: I2C_SPEED_FAST_PLUS
113 * HSCN: I2C_SPEED_HIGH
115 static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
116 struct dw_i2c_speed_config *config)
118 switch (config->speed_mode) {
119 case IC_SPEED_MODE_HIGH:
120 acpigen_write_name(ctx, "HSCN");
122 case IC_SPEED_MODE_FAST_PLUS:
123 acpigen_write_name(ctx, "FPCN");
125 case IC_SPEED_MODE_FAST:
126 acpigen_write_name(ctx, "FMCN");
128 case IC_SPEED_MODE_STANDARD:
130 acpigen_write_name(ctx, "SSCN");
133 /* Package () { scl_lcnt, scl_hcnt, sda_hold } */
134 acpigen_write_package(ctx, 3);
135 acpigen_write_word(ctx, config->scl_hcnt);
136 acpigen_write_word(ctx, config->scl_lcnt);
137 acpigen_write_dword(ctx, config->sda_hold);
138 acpigen_pop_len(ctx);
142 * Generate I2C timing information into the SSDT for the OS driver to consume,
143 * optionally applying override values provided by the caller.
145 static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
146 struct acpi_ctx *ctx)
148 struct dw_i2c_speed_config config;
149 char path[ACPI_PATH_MAX];
155 /* If no device-tree node, ignore this since we assume it isn't used */
156 if (!dev_has_ofnode(dev))
159 ret = acpi_device_path(dev, path, sizeof(path));
161 return log_msg_ret("path", ret);
163 size = dev_read_size(dev, "i2c,speeds");
165 return log_msg_ret("i2c,speeds", -EINVAL);
168 if (size > ARRAY_SIZE(speeds))
169 return log_msg_ret("array", -E2BIG);
171 ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size);
173 return log_msg_ret("read", -E2BIG);
175 speed = dev_read_u32_default(dev, "clock-frequency", 100000);
176 acpigen_write_scope(ctx, path);
177 ret = dw_i2c_gen_speed_config(dev, speed, &config);
179 return log_msg_ret("config", ret);
180 dw_i2c_acpi_write_speed_config(ctx, &config);
181 acpigen_pop_len(ctx);
186 struct acpi_ops dw_i2c_acpi_ops = {
187 .fill_ssdt = dw_i2c_acpi_fill_ssdt,
190 static const struct udevice_id designware_i2c_pci_ids[] = {
191 { .compatible = "snps,designware-i2c-pci" },
192 { .compatible = "intel,apl-i2c", .data = INTEL_APL },
196 DM_DRIVER_ALIAS(i2c_designware_pci, intel_apl_i2c)
198 U_BOOT_DRIVER(i2c_designware_pci) = {
199 .name = "i2c_designware_pci",
201 .of_match = designware_i2c_pci_ids,
202 .bind = designware_i2c_pci_bind,
203 .of_to_plat = designware_i2c_pci_of_to_plat,
204 .probe = designware_i2c_pci_probe,
205 .priv_auto = sizeof(struct dw_i2c),
206 .remove = designware_i2c_remove,
207 .flags = DM_FLAG_OS_PREPARE,
208 .ops = &designware_i2c_ops,
209 ACPI_OPS_PTR(&dw_i2c_acpi_ops)
212 static struct pci_device_id designware_pci_supported[] = {
213 /* Intel BayTrail has 7 I2C controller located on the PCI bus */
214 { PCI_VDEVICE(INTEL, 0x0f41) },
215 { PCI_VDEVICE(INTEL, 0x0f42) },
216 { PCI_VDEVICE(INTEL, 0x0f43) },
217 { PCI_VDEVICE(INTEL, 0x0f44) },
218 { PCI_VDEVICE(INTEL, 0x0f45) },
219 { PCI_VDEVICE(INTEL, 0x0f46) },
220 { PCI_VDEVICE(INTEL, 0x0f47) },
221 { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
222 { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
223 { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
224 { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
225 { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
226 { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
230 U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);