drivers/i2c/designware_i2c.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #ifndef __DW_I2C_H_
   8 #define __DW_I2C_H_
   9
  10 #include <clk.h>
  11 #include <reset.h>
  12
  13 struct i2c_regs {
  14         u32 ic_con;             /* 0x00 */
  15         u32 ic_tar;             /* 0x04 */
  16         u32 ic_sar;             /* 0x08 */
  17         u32 ic_hs_maddr;        /* 0x0c */
  18         u32 ic_cmd_data;        /* 0x10 */
  19         u32 ic_ss_scl_hcnt;     /* 0x14 */
  20         u32 ic_ss_scl_lcnt;     /* 0x18 */
  21         u32 ic_fs_scl_hcnt;     /* 0x1c */
  22         u32 ic_fs_scl_lcnt;     /* 0x20 */
  23         u32 ic_hs_scl_hcnt;     /* 0x24 */
  24         u32 ic_hs_scl_lcnt;     /* 0x28 */
  25         u32 ic_intr_stat;       /* 0x2c */
  26         u32 ic_intr_mask;       /* 0x30 */
  27         u32 ic_raw_intr_stat;   /* 0x34 */
  28         u32 ic_rx_tl;           /* 0x38 */
  29         u32 ic_tx_tl;           /* 0x3c */
  30         u32 ic_clr_intr;        /* 0x40 */
  31         u32 ic_clr_rx_under;    /* 0x44 */
  32         u32 ic_clr_rx_over;     /* 0x48 */
  33         u32 ic_clr_tx_over;     /* 0x4c */
  34         u32 ic_clr_rd_req;      /* 0x50 */
  35         u32 ic_clr_tx_abrt;     /* 0x54 */
  36         u32 ic_clr_rx_done;     /* 0x58 */
  37         u32 ic_clr_activity;    /* 0x5c */
  38         u32 ic_clr_stop_det;    /* 0x60 */
  39         u32 ic_clr_start_det;   /* 0x64 */
  40         u32 ic_clr_gen_call;    /* 0x68 */
  41         u32 ic_enable;          /* 0x6c */
  42         u32 ic_status;          /* 0x70 */
  43         u32 ic_txflr;           /* 0x74 */
  44         u32 ic_rxflr;           /* 0x78 */
  45         u32 ic_sda_hold;        /* 0x7c */
  46         u32 ic_tx_abrt_source;  /* 0x80 */
  47         u32 slv_data_nak_only;
  48         u32 dma_cr;
  49         u32 dma_tdlr;
  50         u32 dma_rdlr;
  51         u32 sda_setup;
  52         u32 ack_general_call;
  53         u32 ic_enable_status;   /* 0x9c */
  54         u32 fs_spklen;
  55         u32 hs_spklen;
  56         u32 clr_restart_det;
  57         u8 reserved[0xf4 - 0xac];
  58         u32 comp_param1;        /* 0xf4 */
  59         u32 comp_version;
  60         u32 comp_type;
  61 };
  62
  63 #define IC_CLK                  166666666
  64 #define NANO_TO_KILO            1000000
  65
  66 /* High and low times in different speed modes (in ns) */
  67 #define MIN_SS_SCL_HIGHTIME     4000
  68 #define MIN_SS_SCL_LOWTIME      4700
  69 #define MIN_FS_SCL_HIGHTIME     600
  70 #define MIN_FS_SCL_LOWTIME      1300
  71 #define MIN_HS_SCL_HIGHTIME     60
  72 #define MIN_HS_SCL_LOWTIME      160
  73
  74 /* Worst case timeout for 1 byte is kept as 2ms */
  75 #define I2C_BYTE_TO             (CONFIG_SYS_HZ/500)
  76 #define I2C_STOPDET_TO          (CONFIG_SYS_HZ/500)
  77 #define I2C_BYTE_TO_BB          (I2C_BYTE_TO * 16)
  78
  79 /* i2c control register definitions */
  80 #define IC_CON_SD               0x0040
  81 #define IC_CON_RE               0x0020
  82 #define IC_CON_10BITADDRMASTER  0x0010
  83 #define IC_CON_10BITADDR_SLAVE  0x0008
  84 #define IC_CON_SPD_MSK          0x0006
  85 #define IC_CON_SPD_SS           0x0002
  86 #define IC_CON_SPD_FS           0x0004
  87 #define IC_CON_SPD_HS           0x0006
  88 #define IC_CON_MM               0x0001
  89
  90 /* i2c target address register definitions */
  91 #define TAR_ADDR                0x0050
  92
  93 /* i2c slave address register definitions */
  94 #define IC_SLAVE_ADDR           0x0002
  95
  96 /* i2c data buffer and command register definitions */
  97 #define IC_CMD                  0x0100
  98 #define IC_STOP                 0x0200
  99
 100 /* i2c interrupt status register definitions */
 101 #define IC_GEN_CALL             0x0800
 102 #define IC_START_DET            0x0400
 103 #define IC_STOP_DET             0x0200
 104 #define IC_ACTIVITY             0x0100
 105 #define IC_RX_DONE              0x0080
 106 #define IC_TX_ABRT              0x0040
 107 #define IC_RD_REQ               0x0020
 108 #define IC_TX_EMPTY             0x0010
 109 #define IC_TX_OVER              0x0008
 110 #define IC_RX_FULL              0x0004
 111 #define IC_RX_OVER              0x0002
 112 #define IC_RX_UNDER             0x0001
 113
 114 /* fifo threshold register definitions */
 115 #define IC_TL0                  0x00
 116 #define IC_TL1                  0x01
 117 #define IC_TL2                  0x02
 118 #define IC_TL3                  0x03
 119 #define IC_TL4                  0x04
 120 #define IC_TL5                  0x05
 121 #define IC_TL6                  0x06
 122 #define IC_TL7                  0x07
 123 #define IC_RX_TL                IC_TL0
 124 #define IC_TX_TL                IC_TL0
 125
 126 /* i2c enable register definitions */
 127 #define IC_ENABLE_0B            0x0001
 128
 129 /* i2c status register  definitions */
 130 #define IC_STATUS_SA            0x0040
 131 #define IC_STATUS_MA            0x0020
 132 #define IC_STATUS_RFF           0x0010
 133 #define IC_STATUS_RFNE          0x0008
 134 #define IC_STATUS_TFE           0x0004
 135 #define IC_STATUS_TFNF          0x0002
 136 #define IC_STATUS_ACT           0x0001
 137
 138 /* Speed Selection */
 139 enum i2c_speed_mode {
 140         IC_SPEED_MODE_STANDARD,
 141         IC_SPEED_MODE_FAST,
 142         IC_SPEED_MODE_HIGH,
 143
 144         IC_SPEED_MODE_COUNT,
 145 };
 146
 147 #define I2C_HIGH_SPEED          3400000
 148 #define I2C_FAST_SPEED          400000
 149 #define I2C_STANDARD_SPEED      100000
 150
 151 /**
 152  * struct dw_scl_sda_cfg - I2C timing configuration
 153  *
 154  * @has_high_speed: Support high speed (3.4Mbps)
 155  * @ss_hcnt: Standard speed high time in ns
 156  * @fs_hcnt: Fast speed high time in ns
 157  * @ss_lcnt: Standard speed low time in ns
 158  * @fs_lcnt: Fast speed low time in ns
 159  * @sda_hold: SDA hold time
 160  */
 161 struct dw_scl_sda_cfg {
 162         bool has_high_speed;
 163         u32 ss_hcnt;
 164         u32 fs_hcnt;
 165         u32 ss_lcnt;
 166         u32 fs_lcnt;
 167         u32 sda_hold;
 168 };
 169
 170 /**
 171  * struct dw_i2c - private information for the bus
 172  *
 173  * @regs: Registers pointer
 174  * @scl_sda_cfg: Deprecated information for x86 (should move to device tree)
 175  * @resets: Resets for the I2C controller
 176  * @scl_rise_time_ns: Configured SCL rise time in nanoseconds
 177  * @scl_fall_time_ns: Configured SCL fall time in nanoseconds
 178  * @sda_hold_time_ns: Configured SDA hold time in nanoseconds
 179  * @has_spk_cnt: true if the spike-count register is present
 180  * @clk: Clock input to the I2C controller
 181  */
 182 struct dw_i2c {
 183         struct i2c_regs *regs;
 184         struct dw_scl_sda_cfg *scl_sda_cfg;
 185         struct reset_ctl_bulk resets;
 186         u32 scl_rise_time_ns;
 187         u32 scl_fall_time_ns;
 188         u32 sda_hold_time_ns;
 189         bool has_spk_cnt;
 190 #if CONFIG_IS_ENABLED(CLK)
 191         struct clk clk;
 192 #endif
 193 };
 194
 195 extern const struct dm_i2c_ops designware_i2c_ops;
 196
 197 int designware_i2c_probe(struct udevice *bus);
 198 int designware_i2c_remove(struct udevice *dev);
 199 int designware_i2c_ofdata_to_platdata(struct udevice *bus);
 200
 201 #endif /* __DW_I2C_H_ */