1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
16 #include <linux/delay.h>
17 #include "designware_i2c.h"
18 #include <dm/device_compat.h>
19 #include <linux/err.h>
21 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
22 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
24 u32 ena = enable ? IC_ENABLE_0B : 0;
26 writel(ena, &i2c_base->ic_enable);
31 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
33 u32 ena = enable ? IC_ENABLE_0B : 0;
37 writel(ena, &i2c_base->ic_enable);
38 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
42 * Wait 10 times the signaling period of the highest I2C
43 * transfer supported by the driver (for 400KHz this is
44 * 25us) as described in the DesignWare I2C databook.
48 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
54 /* High and low times in different speed modes (in ns) */
57 DEFAULT_SDA_HOLD_TIME = 300,
61 * calc_counts() - Convert a period to a number of IC clk cycles
63 * @ic_clk: Input clock in Hz
64 * @period_ns: Period to represent, in ns
65 * @return calculated count
67 static uint calc_counts(uint ic_clk, uint period_ns)
69 return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
73 * struct i2c_mode_info - Information about an I2C speed mode
75 * Each speed mode has its own characteristics. This struct holds these to aid
76 * calculations in dw_i2c_calc_timing().
79 * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
80 * @min_scl_hightime_ns: Minimum value for SCL high period in ns
81 * @def_rise_time_ns: Default rise time in ns
82 * @def_fall_time_ns: Default fall time in ns
84 struct i2c_mode_info {
86 int min_scl_hightime_ns;
87 int min_scl_lowtime_ns;
92 static const struct i2c_mode_info info_for_mode[] = {
93 [IC_SPEED_MODE_STANDARD] = {
94 I2C_SPEED_STANDARD_RATE,
100 [IC_SPEED_MODE_FAST] = {
107 [IC_SPEED_MODE_FAST_PLUS] = {
108 I2C_SPEED_FAST_PLUS_RATE,
114 [IC_SPEED_MODE_HIGH] = {
124 * dw_i2c_calc_timing() - Calculate the timings to use for a bus
126 * @priv: Bus private information (NULL if not using driver model)
127 * @mode: Speed mode to use
128 * @ic_clk: IC clock speed in Hz
129 * @spk_cnt: Spike-suppression count
130 * @config: Returns value to use
131 * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
133 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
134 int ic_clk, int spk_cnt,
135 struct dw_i2c_speed_config *config)
137 int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
138 int hcnt, lcnt, period_cnt, diff, tot;
139 int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
140 const struct i2c_mode_info *info;
143 * Find the period, rise, fall, min tlow, and min thigh in terms of
144 * counts of the IC clock
146 info = &info_for_mode[mode];
147 period_cnt = ic_clk / info->speed;
148 scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
149 priv->scl_rise_time_ns : info->def_rise_time_ns;
150 scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
151 priv->scl_fall_time_ns : info->def_fall_time_ns;
152 rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
153 fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
154 min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
155 min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
157 debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
158 period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
162 * Back-solve for hcnt and lcnt according to the following equations:
163 * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
164 * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
166 hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
167 lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
169 if (hcnt < 0 || lcnt < 0) {
170 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
175 * Now add things back up to ensure the period is hit. If it is off,
176 * split the difference and bias to lcnt for remainder
178 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
180 if (tot < period_cnt) {
181 diff = (period_cnt - tot) / 2;
184 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
185 lcnt += period_cnt - tot;
188 config->scl_lcnt = lcnt;
189 config->scl_hcnt = hcnt;
191 /* Use internal default unless other value is specified */
192 sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
193 priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
194 config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
196 debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
202 static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
203 struct dw_i2c_speed_config *config)
205 const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
206 struct i2c_regs *regs = priv->regs;
207 enum i2c_speed_mode i2c_spd;
212 comp_param1 = readl(®s->comp_param1);
215 scl_sda_cfg = priv->scl_sda_cfg;
216 /* Allow high speed if there is no config, or the config allows it */
217 if (speed >= I2C_SPEED_HIGH_RATE)
218 i2c_spd = IC_SPEED_MODE_HIGH;
219 else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
220 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
221 else if (speed >= I2C_SPEED_FAST_RATE)
222 i2c_spd = IC_SPEED_MODE_FAST;
224 i2c_spd = IC_SPEED_MODE_STANDARD;
226 /* Check is high speed possible and fall back to fast mode if not */
227 if (i2c_spd == IC_SPEED_MODE_HIGH) {
228 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
229 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
230 i2c_spd = IC_SPEED_MODE_FAST;
233 /* Get the proper spike-suppression count based on target speed */
234 if (!priv || !priv->has_spk_cnt)
236 else if (i2c_spd >= IC_SPEED_MODE_HIGH)
237 spk_cnt = readl(®s->hs_spklen);
239 spk_cnt = readl(®s->fs_spklen);
241 config->sda_hold = scl_sda_cfg->sda_hold;
242 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
243 config->scl_hcnt = scl_sda_cfg->ss_hcnt;
244 config->scl_lcnt = scl_sda_cfg->ss_lcnt;
245 } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
246 config->scl_hcnt = scl_sda_cfg->hs_hcnt;
247 config->scl_lcnt = scl_sda_cfg->hs_lcnt;
249 config->scl_hcnt = scl_sda_cfg->fs_hcnt;
250 config->scl_lcnt = scl_sda_cfg->fs_lcnt;
253 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
256 return log_msg_ret("gen_confg", ret);
258 config->speed_mode = i2c_spd;
264 * _dw_i2c_set_bus_speed - Set the i2c speed
265 * @speed: required i2c speed
269 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
270 unsigned int speed, unsigned int bus_clk)
272 struct dw_i2c_speed_config config;
277 ret = calc_bus_speed(priv, speed, bus_clk, &config);
281 /* Get enable setting for restore later */
282 ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
284 /* to set speed cltr must be disabled */
285 dw_i2c_enable(i2c_base, false);
287 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
289 switch (config.speed_mode) {
290 case IC_SPEED_MODE_HIGH:
291 cntl |= IC_CON_SPD_HS;
292 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
293 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
295 case IC_SPEED_MODE_STANDARD:
296 cntl |= IC_CON_SPD_SS;
297 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
298 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
300 case IC_SPEED_MODE_FAST_PLUS:
301 case IC_SPEED_MODE_FAST:
303 cntl |= IC_CON_SPD_FS;
304 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
305 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
309 writel(cntl, &i2c_base->ic_con);
311 /* Configure SDA Hold Time if required */
313 writel(config.sda_hold, &i2c_base->ic_sda_hold);
315 /* Restore back i2c now speed set */
316 if (ena == IC_ENABLE_0B)
317 dw_i2c_enable(i2c_base, true);
323 * i2c_setaddress - Sets the target slave address
324 * @i2c_addr: target i2c address
326 * Sets the target slave address.
328 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
331 dw_i2c_enable(i2c_base, false);
333 writel(i2c_addr, &i2c_base->ic_tar);
336 dw_i2c_enable(i2c_base, true);
340 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
342 * Flushes the i2c RX FIFO
344 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
346 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
347 readl(&i2c_base->ic_cmd_data);
351 * i2c_wait_for_bb - Waits for bus busy
355 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
357 unsigned long start_time_bb = get_timer(0);
359 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
360 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
362 /* Evaluate timeout */
363 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
370 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
373 if (i2c_wait_for_bb(i2c_base))
376 i2c_setaddress(i2c_base, chip);
379 /* high byte address going out first */
380 writel((addr >> (alen * 8)) & 0xff,
381 &i2c_base->ic_cmd_data);
386 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
388 ulong start_stop_det = get_timer(0);
391 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
392 readl(&i2c_base->ic_clr_stop_det);
394 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
399 if (i2c_wait_for_bb(i2c_base)) {
400 printf("Timed out waiting for bus\n");
404 i2c_flush_rxfifo(i2c_base);
410 * i2c_read - Read from i2c memory
411 * @chip: target i2c address
412 * @addr: address to read from
414 * @buffer: buffer for read data
415 * @len: no of bytes to be read
417 * Read from i2c memory.
419 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
420 int alen, u8 *buffer, int len)
422 unsigned long start_time_rx;
423 unsigned int active = 0;
425 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
427 * EEPROM chips that implement "address overflow" are ones
428 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
429 * address and the extra bits end up in the "chip address"
430 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
431 * four 256 byte chips.
433 * Note that we consider the length of the address field to
434 * still be one byte because the extra address bits are
435 * hidden in the chip address.
437 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
438 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
440 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
444 if (i2c_xfer_init(i2c_base, dev, addr, alen))
447 start_time_rx = get_timer(0);
451 * Avoid writing to ic_cmd_data multiple times
452 * in case this loop spins too quickly and the
453 * ic_status RFNE bit isn't set after the first
454 * write. Subsequent writes to ic_cmd_data can
455 * trigger spurious i2c transfer.
458 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
460 writel(IC_CMD, &i2c_base->ic_cmd_data);
464 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
465 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
467 start_time_rx = get_timer(0);
469 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
474 return i2c_xfer_finish(i2c_base);
478 * i2c_write - Write to i2c memory
479 * @chip: target i2c address
480 * @addr: address to read from
482 * @buffer: buffer for read data
483 * @len: no of bytes to be read
485 * Write to i2c memory.
487 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
488 int alen, u8 *buffer, int len)
491 unsigned long start_time_tx;
493 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
495 * EEPROM chips that implement "address overflow" are ones
496 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
497 * address and the extra bits end up in the "chip address"
498 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
499 * four 256 byte chips.
501 * Note that we consider the length of the address field to
502 * still be one byte because the extra address bits are
503 * hidden in the chip address.
505 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
506 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
508 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
512 if (i2c_xfer_init(i2c_base, dev, addr, alen))
515 start_time_tx = get_timer(0);
517 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
519 writel(*buffer | IC_STOP,
520 &i2c_base->ic_cmd_data);
522 writel(*buffer, &i2c_base->ic_cmd_data);
525 start_time_tx = get_timer(0);
527 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
528 printf("Timed out. i2c write Failed\n");
533 return i2c_xfer_finish(i2c_base);
537 * __dw_i2c_init - Init function
538 * @speed: required i2c speed
539 * @slaveaddr: slave address for the device
541 * Initialization function.
543 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
548 ret = dw_i2c_enable(i2c_base, false);
552 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
554 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
555 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
556 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
557 #ifndef CONFIG_DM_I2C
558 _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
559 writel(slaveaddr, &i2c_base->ic_sar);
563 ret = dw_i2c_enable(i2c_base, true);
570 #ifndef CONFIG_DM_I2C
572 * The legacy I2C functions. These need to get removed once
573 * all users of this driver are converted to DM.
575 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
577 switch (adap->hwadapnr) {
578 #if CONFIG_SYS_I2C_BUS_MAX >= 4
580 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
582 #if CONFIG_SYS_I2C_BUS_MAX >= 3
584 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
586 #if CONFIG_SYS_I2C_BUS_MAX >= 2
588 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
591 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
593 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
599 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
603 return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
606 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
608 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
611 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
612 int alen, u8 *buffer, int len)
614 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
617 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
618 int alen, u8 *buffer, int len)
620 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
623 /* dw_i2c_probe - Probe the i2c chip */
624 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
626 struct i2c_regs *i2c_base = i2c_get_base(adap);
631 * Try to read the first location of the chip.
633 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
635 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
640 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
641 dw_i2c_write, dw_i2c_set_bus_speed,
642 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
644 #if CONFIG_SYS_I2C_BUS_MAX >= 2
645 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
646 dw_i2c_write, dw_i2c_set_bus_speed,
647 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
650 #if CONFIG_SYS_I2C_BUS_MAX >= 3
651 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
652 dw_i2c_write, dw_i2c_set_bus_speed,
653 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
656 #if CONFIG_SYS_I2C_BUS_MAX >= 4
657 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
658 dw_i2c_write, dw_i2c_set_bus_speed,
659 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
662 #else /* CONFIG_DM_I2C */
663 /* The DM I2C functions */
665 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
668 struct dw_i2c *i2c = dev_get_priv(bus);
671 debug("i2c_xfer: %d messages\n", nmsgs);
672 for (; nmsgs > 0; nmsgs--, msg++) {
673 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
674 if (msg->flags & I2C_M_RD) {
675 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
678 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
682 debug("i2c_write: error sending\n");
690 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
692 struct dw_i2c *i2c = dev_get_priv(bus);
695 #if CONFIG_IS_ENABLED(CLK)
696 rate = clk_get_rate(&i2c->clk);
697 if (IS_ERR_VALUE(rate))
702 return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
705 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
708 struct dw_i2c *i2c = dev_get_priv(bus);
709 struct i2c_regs *i2c_base = i2c->regs;
713 /* Try to read the first location of the chip */
714 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
716 __dw_i2c_init(i2c_base, 0, 0);
721 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
723 struct dw_i2c *priv = dev_get_priv(bus);
727 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
728 dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
729 dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
730 dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
732 ret = reset_get_bulk(bus, &priv->resets);
734 dev_warn(bus, "Can't get reset: %d\n", ret);
736 reset_deassert_bulk(&priv->resets);
738 #if CONFIG_IS_ENABLED(CLK)
739 ret = clk_get_by_index(bus, 0, &priv->clk);
743 ret = clk_enable(&priv->clk);
744 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
745 clk_free(&priv->clk);
746 dev_err(bus, "failed to enable clock\n");
754 int designware_i2c_probe(struct udevice *bus)
756 struct dw_i2c *priv = dev_get_priv(bus);
758 return __dw_i2c_init(priv->regs, 0, 0);
761 int designware_i2c_remove(struct udevice *dev)
763 struct dw_i2c *priv = dev_get_priv(dev);
765 #if CONFIG_IS_ENABLED(CLK)
766 clk_disable(&priv->clk);
767 clk_free(&priv->clk);
770 return reset_release_bulk(&priv->resets);
773 const struct dm_i2c_ops designware_i2c_ops = {
774 .xfer = designware_i2c_xfer,
775 .probe_chip = designware_i2c_probe_chip,
776 .set_bus_speed = designware_i2c_set_bus_speed,
779 static const struct udevice_id designware_i2c_ids[] = {
780 { .compatible = "snps,designware-i2c" },
784 U_BOOT_DRIVER(i2c_designware) = {
785 .name = "i2c_designware",
787 .of_match = designware_i2c_ids,
788 .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
789 .probe = designware_i2c_probe,
790 .priv_auto_alloc_size = sizeof(struct dw_i2c),
791 .remove = designware_i2c_remove,
792 .flags = DM_FLAG_OS_PREPARE,
793 .ops = &designware_i2c_ops,
796 #endif /* CONFIG_DM_I2C */