Prepare v2024.10
[platform/kernel/u-boot.git] / drivers / i2c / designware_i2c.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2009
4  * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
5  */
6
7 #include <clk.h>
8 #include <dm.h>
9 #include <i2c.h>
10 #include <log.h>
11 #include <malloc.h>
12 #include <pci.h>
13 #include <reset.h>
14 #include <asm/io.h>
15 #include <linux/delay.h>
16 #include "designware_i2c.h"
17 #include <dm/device_compat.h>
18 #include <linux/err.h>
19
20 /*
21  * This assigned unique hex value is constant and is derived from the two ASCII
22  * letters 'DW' followed by a 16-bit unsigned number
23  */
24 #define DW_I2C_COMP_TYPE        0x44570140
25
26 /*
27  * This constant is used to calculate when during the clock high phase the data
28  * bit shall be read. The value was copied from the Linux v6.5 function
29  * i2c_dw_scl_hcnt() which provides the following explanation:
30  *
31  * "This is just an experimental rule: the tHD;STA period turned out to be
32  * proportinal to (_HCNT + 3). With this setting, we could meet both tHIGH and
33  * tHD;STA timing specs."
34  */
35 #define T_HD_STA_OFFSET 3
36
37 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
38 {
39         u32 ena = enable ? IC_ENABLE_0B : 0;
40         int timeout = 100;
41
42         do {
43                 writel(ena, &i2c_base->ic_enable);
44                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
45                         return 0;
46
47                 /*
48                  * Wait 10 times the signaling period of the highest I2C
49                  * transfer supported by the driver (for 400KHz this is
50                  * 25us) as described in the DesignWare I2C databook.
51                  */
52                 udelay(25);
53         } while (timeout--);
54         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
55
56         return -ETIMEDOUT;
57 }
58
59 /* High and low times in different speed modes (in ns) */
60 enum {
61         /* SDA Hold Time */
62         DEFAULT_SDA_HOLD_TIME           = 300,
63 };
64
65 /**
66  * calc_counts() - Convert a period to a number of IC clk cycles
67  *
68  * @ic_clk: Input clock in Hz
69  * @period_ns: Period to represent, in ns
70  * Return: calculated count
71  */
72 static uint calc_counts(uint ic_clk, uint period_ns)
73 {
74         return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
75 }
76
77 /**
78  * struct i2c_mode_info - Information about an I2C speed mode
79  *
80  * Each speed mode has its own characteristics. This struct holds these to aid
81  * calculations in dw_i2c_calc_timing().
82  *
83  * @speed: Speed in Hz
84  * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
85  * @min_scl_hightime_ns: Minimum value for SCL high period in ns
86  * @def_rise_time_ns: Default rise time in ns
87  * @def_fall_time_ns: Default fall time in ns
88  */
89 struct i2c_mode_info {
90         int speed;
91         int min_scl_hightime_ns;
92         int min_scl_lowtime_ns;
93         int def_rise_time_ns;
94         int def_fall_time_ns;
95 };
96
97 static const struct i2c_mode_info info_for_mode[] = {
98         [IC_SPEED_MODE_STANDARD] = {
99                 I2C_SPEED_STANDARD_RATE,
100                 MIN_SS_SCL_HIGHTIME,
101                 MIN_SS_SCL_LOWTIME,
102                 1000,
103                 300,
104         },
105         [IC_SPEED_MODE_FAST] = {
106                 I2C_SPEED_FAST_RATE,
107                 MIN_FS_SCL_HIGHTIME,
108                 MIN_FS_SCL_LOWTIME,
109                 300,
110                 300,
111         },
112         [IC_SPEED_MODE_FAST_PLUS] = {
113                 I2C_SPEED_FAST_PLUS_RATE,
114                 MIN_FP_SCL_HIGHTIME,
115                 MIN_FP_SCL_LOWTIME,
116                 260,
117                 500,
118         },
119         [IC_SPEED_MODE_HIGH] = {
120                 I2C_SPEED_HIGH_RATE,
121                 MIN_HS_SCL_HIGHTIME,
122                 MIN_HS_SCL_LOWTIME,
123                 120,
124                 120,
125         },
126 };
127
128 /**
129  * dw_i2c_calc_timing() - Calculate the timings to use for a bus
130  *
131  * @priv: Bus private information (NULL if not using driver model)
132  * @mode: Speed mode to use
133  * @ic_clk: IC clock speed in Hz
134  * @spk_cnt: Spike-suppression count
135  * @config: Returns value to use
136  * Return: 0 if OK, -EINVAL if the calculation failed due to invalid data
137  */
138 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
139                               int ic_clk, int spk_cnt,
140                               struct dw_i2c_speed_config *config)
141 {
142         int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
143         int hcnt, lcnt, period_cnt, diff, tot;
144         int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
145         const struct i2c_mode_info *info;
146
147         /*
148          * Find the period, rise, fall, min tlow, and min thigh in terms of
149          * counts of the IC clock
150          */
151         info = &info_for_mode[mode];
152         period_cnt = ic_clk / info->speed;
153         scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
154                  priv->scl_rise_time_ns : info->def_rise_time_ns;
155         scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
156                  priv->scl_fall_time_ns : info->def_fall_time_ns;
157         rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
158         fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
159         min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
160         min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
161
162         debug("dw_i2c: mode %d, ic_clk %d, speed %d, period %d rise %d fall %d tlow %d thigh %d spk %d\n",
163               mode, ic_clk, info->speed, period_cnt, rise_cnt, fall_cnt,
164               min_tlow_cnt, min_thigh_cnt, spk_cnt);
165
166         /*
167          * Back-solve for hcnt and lcnt according to the following equations:
168          * SCL_High_time = [(HCNT + IC_*_SPKLEN + T_HD_STA_OFFSET) * ic_clk] + SCL_Fall_time
169          * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
170          */
171         hcnt = min_thigh_cnt - fall_cnt - T_HD_STA_OFFSET - spk_cnt;
172         lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
173
174         if (hcnt < 0 || lcnt < 0) {
175                 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
176                 return log_msg_ret("counts", -EINVAL);
177         }
178
179         /*
180          * Now add things back up to ensure the period is hit. If it is off,
181          * split the difference and bias to lcnt for remainder
182          */
183         tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1;
184
185         if (tot < period_cnt) {
186                 diff = (period_cnt - tot) / 2;
187                 hcnt += diff;
188                 lcnt += diff;
189                 tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1;
190                 lcnt += period_cnt - tot;
191         }
192
193         config->scl_lcnt = lcnt;
194         config->scl_hcnt = hcnt;
195
196         /* Use internal default unless other value is specified */
197         sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
198                  priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
199         config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
200
201         debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
202               config->sda_hold);
203
204         return 0;
205 }
206
207 /**
208  * calc_bus_speed() - Calculate the config to use for a particular i2c speed
209  *
210  * @priv: Private information for the driver (NULL if not using driver model)
211  * @i2c_base: Registers for the I2C controller
212  * @speed: Required i2c speed in Hz
213  * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
214  * @config: Returns the config to use for this speed
215  * Return: 0 if OK, -ve on error
216  */
217 static int calc_bus_speed(struct dw_i2c *priv, struct i2c_regs *regs, int speed,
218                           ulong bus_clk, struct dw_i2c_speed_config *config)
219 {
220         const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
221         enum i2c_speed_mode i2c_spd;
222         int spk_cnt;
223         int ret;
224
225         if (priv)
226                 scl_sda_cfg = priv->scl_sda_cfg;
227         /* Allow high speed if there is no config, or the config allows it */
228         if (speed >= I2C_SPEED_HIGH_RATE)
229                 i2c_spd = IC_SPEED_MODE_HIGH;
230         else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
231                 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
232         else if (speed >= I2C_SPEED_FAST_RATE)
233                 i2c_spd = IC_SPEED_MODE_FAST;
234         else
235                 i2c_spd = IC_SPEED_MODE_STANDARD;
236
237         /* Check is high speed possible and fall back to fast mode if not */
238         if (i2c_spd == IC_SPEED_MODE_HIGH) {
239                 u32 comp_param1;
240
241                 comp_param1 = readl(&regs->comp_param1);
242                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
243                                 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
244                         i2c_spd = IC_SPEED_MODE_FAST;
245         }
246
247         /* Get the proper spike-suppression count based on target speed */
248         if (!priv || !priv->has_spk_cnt)
249                 spk_cnt = 0;
250         else if (i2c_spd >= IC_SPEED_MODE_HIGH)
251                 spk_cnt = readl(&regs->hs_spklen);
252         else
253                 spk_cnt = readl(&regs->fs_spklen);
254         if (scl_sda_cfg) {
255                 config->sda_hold = scl_sda_cfg->sda_hold;
256                 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
257                         config->scl_hcnt = scl_sda_cfg->ss_hcnt;
258                         config->scl_lcnt = scl_sda_cfg->ss_lcnt;
259                 } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
260                         config->scl_hcnt = scl_sda_cfg->hs_hcnt;
261                         config->scl_lcnt = scl_sda_cfg->hs_lcnt;
262                 } else {
263                         config->scl_hcnt = scl_sda_cfg->fs_hcnt;
264                         config->scl_lcnt = scl_sda_cfg->fs_lcnt;
265                 }
266         } else {
267                 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
268                                          config);
269                 if (ret)
270                         return log_msg_ret("gen_confg", ret);
271         }
272         config->speed_mode = i2c_spd;
273
274         return 0;
275 }
276
277 /**
278  * _dw_i2c_set_bus_speed() - Set the i2c speed
279  *
280  * @priv: Private information for the driver (NULL if not using driver model)
281  * @i2c_base: Registers for the I2C controller
282  * @speed: Required i2c speed in Hz
283  * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
284  * Return: 0 if OK, -ve on error
285  */
286 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
287                                  unsigned int speed, unsigned int bus_clk)
288 {
289         struct dw_i2c_speed_config config;
290         unsigned int cntl;
291         unsigned int ena;
292         int ret;
293
294         ret = calc_bus_speed(priv, i2c_base, speed, bus_clk, &config);
295         if (ret)
296                 return ret;
297
298         /* Get enable setting for restore later */
299         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
300
301         /* to set speed cltr must be disabled */
302         dw_i2c_enable(i2c_base, false);
303
304         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
305
306         switch (config.speed_mode) {
307         case IC_SPEED_MODE_HIGH:
308                 cntl |= IC_CON_SPD_HS;
309                 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
310                 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
311                 break;
312         case IC_SPEED_MODE_STANDARD:
313                 cntl |= IC_CON_SPD_SS;
314                 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
315                 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
316                 break;
317         case IC_SPEED_MODE_FAST_PLUS:
318         case IC_SPEED_MODE_FAST:
319         default:
320                 cntl |= IC_CON_SPD_FS;
321                 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
322                 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
323                 break;
324         }
325
326         writel(cntl, &i2c_base->ic_con);
327
328         /* Configure SDA Hold Time if required */
329         if (config.sda_hold)
330                 writel(config.sda_hold, &i2c_base->ic_sda_hold);
331
332         /* Restore back i2c now speed set */
333         if (ena == IC_ENABLE_0B)
334                 dw_i2c_enable(i2c_base, true);
335         if (priv)
336                 priv->config = config;
337
338         return 0;
339 }
340
341 int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
342                             struct dw_i2c_speed_config *config)
343 {
344         struct dw_i2c *priv = dev_get_priv(dev);
345         ulong rate;
346         int ret;
347
348 #if CONFIG_IS_ENABLED(CLK)
349         rate = clk_get_rate(&priv->clk);
350         if (IS_ERR_VALUE(rate))
351                 return log_msg_ret("clk", -EINVAL);
352 #else
353         rate = IC_CLK;
354 #endif
355
356         ret = calc_bus_speed(priv, priv->regs, speed_hz, rate, config);
357         if (ret)
358                 printf("%s: ret=%d\n", __func__, ret);
359         if (ret)
360                 return log_msg_ret("calc_bus_speed", ret);
361
362         return 0;
363 }
364
365 /*
366  * i2c_setaddress - Sets the target slave address
367  * @i2c_addr:   target i2c address
368  *
369  * Sets the target slave address.
370  */
371 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
372 {
373         /* Disable i2c */
374         dw_i2c_enable(i2c_base, false);
375
376         writel(i2c_addr, &i2c_base->ic_tar);
377
378         /* Enable i2c */
379         dw_i2c_enable(i2c_base, true);
380 }
381
382 /*
383  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
384  *
385  * Flushes the i2c RX FIFO
386  */
387 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
388 {
389         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
390                 readl(&i2c_base->ic_cmd_data);
391 }
392
393 /*
394  * i2c_wait_for_bb - Waits for bus busy
395  *
396  * Waits for bus busy
397  */
398 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
399 {
400         unsigned long start_time_bb = get_timer(0);
401
402         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
403                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
404
405                 /* Evaluate timeout */
406                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
407                         return 1;
408         }
409
410         return 0;
411 }
412
413 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
414                          int alen)
415 {
416         if (i2c_wait_for_bb(i2c_base))
417                 return 1;
418
419         i2c_setaddress(i2c_base, chip);
420         while (alen) {
421                 alen--;
422                 /* high byte address going out first */
423                 writel((addr >> (alen * 8)) & 0xff,
424                        &i2c_base->ic_cmd_data);
425         }
426         return 0;
427 }
428
429 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
430 {
431         ulong start_stop_det = get_timer(0);
432
433         while (1) {
434                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
435                         readl(&i2c_base->ic_clr_stop_det);
436                         break;
437                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
438                         break;
439                 }
440         }
441
442         if (i2c_wait_for_bb(i2c_base)) {
443                 printf("Timed out waiting for bus\n");
444                 return 1;
445         }
446
447         i2c_flush_rxfifo(i2c_base);
448
449         return 0;
450 }
451
452 /*
453  * i2c_read - Read from i2c memory
454  * @chip:       target i2c address
455  * @addr:       address to read from
456  * @alen:
457  * @buffer:     buffer for read data
458  * @len:        no of bytes to be read
459  *
460  * Read from i2c memory.
461  */
462 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
463                          int alen, u8 *buffer, int len)
464 {
465         unsigned long start_time_rx;
466         unsigned int active = 0;
467
468 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
469         /*
470          * EEPROM chips that implement "address overflow" are ones
471          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
472          * address and the extra bits end up in the "chip address"
473          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
474          * four 256 byte chips.
475          *
476          * Note that we consider the length of the address field to
477          * still be one byte because the extra address bits are
478          * hidden in the chip address.
479          */
480         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
481         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
482
483         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
484               addr);
485 #endif
486
487         if (i2c_xfer_init(i2c_base, dev, addr, alen))
488                 return 1;
489
490         start_time_rx = get_timer(0);
491         while (len) {
492                 if (!active) {
493                         /*
494                          * Avoid writing to ic_cmd_data multiple times
495                          * in case this loop spins too quickly and the
496                          * ic_status RFNE bit isn't set after the first
497                          * write. Subsequent writes to ic_cmd_data can
498                          * trigger spurious i2c transfer.
499                          */
500                         if (len == 1)
501                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
502                         else
503                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
504                         active = 1;
505                 }
506
507                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
508                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
509                         len--;
510                         start_time_rx = get_timer(0);
511                         active = 0;
512                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
513                         return 1;
514                 }
515         }
516
517         return i2c_xfer_finish(i2c_base);
518 }
519
520 /*
521  * i2c_write - Write to i2c memory
522  * @chip:       target i2c address
523  * @addr:       address to read from
524  * @alen:
525  * @buffer:     buffer for read data
526  * @len:        no of bytes to be read
527  *
528  * Write to i2c memory.
529  */
530 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
531                           int alen, u8 *buffer, int len)
532 {
533         int nb = len;
534         unsigned long start_time_tx;
535
536 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
537         /*
538          * EEPROM chips that implement "address overflow" are ones
539          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
540          * address and the extra bits end up in the "chip address"
541          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
542          * four 256 byte chips.
543          *
544          * Note that we consider the length of the address field to
545          * still be one byte because the extra address bits are
546          * hidden in the chip address.
547          */
548         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
549         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
550
551         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
552               addr);
553 #endif
554
555         if (i2c_xfer_init(i2c_base, dev, addr, alen))
556                 return 1;
557
558         start_time_tx = get_timer(0);
559         while (len) {
560                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
561                         if (--len == 0) {
562                                 writel(*buffer | IC_STOP,
563                                        &i2c_base->ic_cmd_data);
564                         } else {
565                                 writel(*buffer, &i2c_base->ic_cmd_data);
566                         }
567                         buffer++;
568                         start_time_tx = get_timer(0);
569
570                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
571                                 printf("Timed out. i2c write Failed\n");
572                                 return 1;
573                 }
574         }
575
576         return i2c_xfer_finish(i2c_base);
577 }
578
579 /*
580  * __dw_i2c_init - Init function
581  * @speed:      required i2c speed
582  * @slaveaddr:  slave address for the device
583  *
584  * Initialization function.
585  */
586 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
587 {
588         int ret;
589
590         /* Disable i2c */
591         ret = dw_i2c_enable(i2c_base, false);
592         if (ret)
593                 return ret;
594
595         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
596                &i2c_base->ic_con);
597         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
598         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
599         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
600 #if !CONFIG_IS_ENABLED(DM_I2C)
601         _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
602         writel(slaveaddr, &i2c_base->ic_sar);
603 #endif
604
605         /* Enable i2c */
606         ret = dw_i2c_enable(i2c_base, true);
607         if (ret)
608                 return ret;
609
610         return 0;
611 }
612
613 #if !CONFIG_IS_ENABLED(DM_I2C)
614 /*
615  * The legacy I2C functions. These need to get removed once
616  * all users of this driver are converted to DM.
617  */
618 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
619 {
620         switch (adap->hwadapnr) {
621 #if CONFIG_SYS_I2C_BUS_MAX >= 4
622         case 3:
623                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
624 #endif
625 #if CONFIG_SYS_I2C_BUS_MAX >= 3
626         case 2:
627                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
628 #endif
629 #if CONFIG_SYS_I2C_BUS_MAX >= 2
630         case 1:
631                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
632 #endif
633         case 0:
634                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
635         default:
636                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
637         }
638
639         return NULL;
640 }
641
642 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
643                                          unsigned int speed)
644 {
645         adap->speed = speed;
646         return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
647 }
648
649 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
650 {
651         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
652 }
653
654 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
655                        int alen, u8 *buffer, int len)
656 {
657         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
658 }
659
660 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
661                         int alen, u8 *buffer, int len)
662 {
663         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
664 }
665
666 /* dw_i2c_probe - Probe the i2c chip */
667 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
668 {
669         struct i2c_regs *i2c_base = i2c_get_base(adap);
670         u32 tmp;
671         int ret;
672
673         /*
674          * Try to read the first location of the chip.
675          */
676         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
677         if (ret)
678                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
679
680         return ret;
681 }
682
683 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
684                          dw_i2c_write, dw_i2c_set_bus_speed,
685                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
686
687 #else /* CONFIG_DM_I2C */
688 /* The DM I2C functions */
689
690 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
691                                int nmsgs)
692 {
693         struct dw_i2c *i2c = dev_get_priv(bus);
694         int ret;
695
696         debug("i2c_xfer: %d messages\n", nmsgs);
697         for (; nmsgs > 0; nmsgs--, msg++) {
698                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
699                 if (msg->flags & I2C_M_RD) {
700                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
701                                             msg->buf, msg->len);
702                 } else {
703                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
704                                              msg->buf, msg->len);
705                 }
706                 if (ret) {
707                         debug("i2c_write: error sending\n");
708                         return -EREMOTEIO;
709                 }
710         }
711
712         return 0;
713 }
714
715 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
716 {
717         struct dw_i2c *i2c = dev_get_priv(bus);
718         ulong rate;
719
720 #if CONFIG_IS_ENABLED(CLK)
721         rate = clk_get_rate(&i2c->clk);
722         if (IS_ERR_VALUE(rate))
723                 return log_ret(-EINVAL);
724 #else
725         rate = IC_CLK;
726 #endif
727         return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
728 }
729
730 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
731                                      uint chip_flags)
732 {
733         struct dw_i2c *i2c = dev_get_priv(bus);
734         struct i2c_regs *i2c_base = i2c->regs;
735         u32 tmp;
736         int ret;
737
738         /* Try to read the first location of the chip */
739         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
740         if (ret)
741                 __dw_i2c_init(i2c_base, 0, 0);
742
743         return ret;
744 }
745
746 int designware_i2c_of_to_plat(struct udevice *bus)
747 {
748         struct dw_i2c *priv = dev_get_priv(bus);
749         int ret;
750
751         if (!priv->regs)
752                 priv->regs = dev_read_addr_ptr(bus);
753         dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
754         dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
755         dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
756
757         ret = reset_get_bulk(bus, &priv->resets);
758         if (ret) {
759                 if (ret != -ENOTSUPP)
760                         dev_warn(bus, "Can't get reset: %d\n", ret);
761         } else {
762                 reset_deassert_bulk(&priv->resets);
763         }
764
765 #if CONFIG_IS_ENABLED(CLK)
766         ret = clk_get_by_index(bus, 0, &priv->clk);
767         if (ret)
768                 return ret;
769
770         ret = clk_enable(&priv->clk);
771         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
772                 dev_err(bus, "failed to enable clock\n");
773                 return ret;
774         }
775 #endif
776
777         return 0;
778 }
779
780 int designware_i2c_probe(struct udevice *bus)
781 {
782         struct dw_i2c *priv = dev_get_priv(bus);
783         uint comp_type;
784
785         comp_type = readl(&priv->regs->comp_type);
786         if (comp_type != DW_I2C_COMP_TYPE) {
787                 log_err("I2C bus %s has unknown type %#x\n", bus->name,
788                         comp_type);
789                 return -ENXIO;
790         }
791
792         log_debug("I2C bus %s version %#x\n", bus->name,
793                   readl(&priv->regs->comp_version));
794
795         return __dw_i2c_init(priv->regs, 0, 0);
796 }
797
798 int designware_i2c_remove(struct udevice *dev)
799 {
800         struct dw_i2c *priv = dev_get_priv(dev);
801
802 #if CONFIG_IS_ENABLED(CLK)
803         clk_disable(&priv->clk);
804 #endif
805
806         return reset_release_bulk(&priv->resets);
807 }
808
809 const struct dm_i2c_ops designware_i2c_ops = {
810         .xfer           = designware_i2c_xfer,
811         .probe_chip     = designware_i2c_probe_chip,
812         .set_bus_speed  = designware_i2c_set_bus_speed,
813 };
814
815 static const struct udevice_id designware_i2c_ids[] = {
816         { .compatible = "snps,designware-i2c" },
817         { }
818 };
819
820 U_BOOT_DRIVER(i2c_designware) = {
821         .name   = "i2c_designware",
822         .id     = UCLASS_I2C,
823         .of_match = designware_i2c_ids,
824         .of_to_plat = designware_i2c_of_to_plat,
825         .probe  = designware_i2c_probe,
826         .priv_auto      = sizeof(struct dw_i2c),
827         .remove = designware_i2c_remove,
828         .flags  = DM_FLAG_OS_PREPARE,
829         .ops    = &designware_i2c_ops,
830 };
831
832 #endif /* CONFIG_DM_I2C */