drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <malloc.h>
  12 #include <pci.h>
  13 #include <reset.h>
  14 #include <asm/io.h>
  15 #include "designware_i2c.h"
  16 #include <dm/device_compat.h>
  17 #include <linux/err.h>
  18
  19 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  20 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  21 {
  22         u32 ena = enable ? IC_ENABLE_0B : 0;
  23
  24         writel(ena, &i2c_base->ic_enable);
  25
  26         return 0;
  27 }
  28 #else
  29 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  30 {
  31         u32 ena = enable ? IC_ENABLE_0B : 0;
  32         int timeout = 100;
  33
  34         do {
  35                 writel(ena, &i2c_base->ic_enable);
  36                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  37                         return 0;
  38
  39                 /*
  40                  * Wait 10 times the signaling period of the highest I2C
  41                  * transfer supported by the driver (for 400KHz this is
  42                  * 25us) as described in the DesignWare I2C databook.
  43                  */
  44                 udelay(25);
  45         } while (timeout--);
  46         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  47
  48         return -ETIMEDOUT;
  49 }
  50 #endif
  51
  52 /* High and low times in different speed modes (in ns) */
  53 enum {
  54         /* SDA Hold Time */
  55         DEFAULT_SDA_HOLD_TIME           = 300,
  56 };
  57
  58 /**
  59  * calc_counts() - Convert a period to a number of IC clk cycles
  60  *
  61  * @ic_clk: Input clock in Hz
  62  * @period_ns: Period to represent, in ns
  63  * @return calculated count
  64  */
  65 static uint calc_counts(uint ic_clk, uint period_ns)
  66 {
  67         return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  68 }
  69
  70 /**
  71  * struct i2c_mode_info - Information about an I2C speed mode
  72  *
  73  * Each speed mode has its own characteristics. This struct holds these to aid
  74  * calculations in dw_i2c_calc_timing().
  75  *
  76  * @speed: Speed in Hz
  77  * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  78  * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  79  * @def_rise_time_ns: Default rise time in ns
  80  * @def_fall_time_ns: Default fall time in ns
  81  */
  82 struct i2c_mode_info {
  83         int speed;
  84         int min_scl_hightime_ns;
  85         int min_scl_lowtime_ns;
  86         int def_rise_time_ns;
  87         int def_fall_time_ns;
  88 };
  89
  90 static const struct i2c_mode_info info_for_mode[] = {
  91         [IC_SPEED_MODE_STANDARD] = {
  92                 I2C_SPEED_STANDARD_RATE,
  93                 MIN_SS_SCL_HIGHTIME,
  94                 MIN_SS_SCL_LOWTIME,
  95                 1000,
  96                 300,
  97         },
  98         [IC_SPEED_MODE_FAST] = {
  99                 I2C_SPEED_FAST_RATE,
 100                 MIN_FS_SCL_HIGHTIME,
 101                 MIN_FS_SCL_LOWTIME,
 102                 300,
 103                 300,
 104         },
 105         [IC_SPEED_MODE_FAST_PLUS] = {
 106                 I2C_SPEED_FAST_PLUS_RATE,
 107                 MIN_FP_SCL_HIGHTIME,
 108                 MIN_FP_SCL_LOWTIME,
 109                 260,
 110                 500,
 111         },
 112         [IC_SPEED_MODE_HIGH] = {
 113                 I2C_SPEED_HIGH_RATE,
 114                 MIN_HS_SCL_HIGHTIME,
 115                 MIN_HS_SCL_LOWTIME,
 116                 120,
 117                 120,
 118         },
 119 };
 120
 121 /**
 122  * dw_i2c_calc_timing() - Calculate the timings to use for a bus
 123  *
 124  * @priv: Bus private information (NULL if not using driver model)
 125  * @mode: Speed mode to use
 126  * @ic_clk: IC clock speed in Hz
 127  * @spk_cnt: Spike-suppression count
 128  * @config: Returns value to use
 129  * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
 130  */
 131 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 132                               int ic_clk, int spk_cnt,
 133                               struct dw_i2c_speed_config *config)
 134 {
 135         int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
 136         int hcnt, lcnt, period_cnt, diff, tot;
 137         int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
 138         const struct i2c_mode_info *info;
 139
 140         /*
 141          * Find the period, rise, fall, min tlow, and min thigh in terms of
 142          * counts of the IC clock
 143          */
 144         info = &info_for_mode[mode];
 145         period_cnt = ic_clk / info->speed;
 146         scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
 147                  priv->scl_rise_time_ns : info->def_rise_time_ns;
 148         scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
 149                  priv->scl_fall_time_ns : info->def_fall_time_ns;
 150         rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
 151         fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
 152         min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
 153         min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
 154
 155         debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
 156               period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
 157               spk_cnt);
 158
 159         /*
 160          * Back-solve for hcnt and lcnt according to the following equations:
 161          * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
 162          * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
 163          */
 164         hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
 165         lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
 166
 167         if (hcnt < 0 || lcnt < 0) {
 168                 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
 169                 return -EINVAL;
 170         }
 171
 172         /*
 173          * Now add things back up to ensure the period is hit. If it is off,
 174          * split the difference and bias to lcnt for remainder
 175          */
 176         tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 177
 178         if (tot < period_cnt) {
 179                 diff = (period_cnt - tot) / 2;
 180                 hcnt += diff;
 181                 lcnt += diff;
 182                 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 183                 lcnt += period_cnt - tot;
 184         }
 185
 186         config->scl_lcnt = lcnt;
 187         config->scl_hcnt = hcnt;
 188
 189         /* Use internal default unless other value is specified */
 190         sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
 191                  priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
 192         config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
 193
 194         debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
 195               config->sda_hold);
 196
 197         return 0;
 198 }
 199
 200 static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
 201                           struct dw_i2c_speed_config *config)
 202 {
 203         const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
 204         struct i2c_regs *regs = priv->regs;
 205         enum i2c_speed_mode i2c_spd;
 206         int spk_cnt;
 207         int ret;
 208
 209         if (priv)
 210                 scl_sda_cfg = priv->scl_sda_cfg;
 211         /* Allow high speed if there is no config, or the config allows it */
 212         if (speed >= I2C_SPEED_HIGH_RATE &&
 213             (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
 214                 i2c_spd = IC_SPEED_MODE_HIGH;
 215         else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
 216                 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
 217         else if (speed >= I2C_SPEED_FAST_RATE)
 218                 i2c_spd = IC_SPEED_MODE_FAST;
 219         else
 220                 i2c_spd = IC_SPEED_MODE_STANDARD;
 221
 222         /* Get the proper spike-suppression count based on target speed */
 223         if (!priv || !priv->has_spk_cnt)
 224                 spk_cnt = 0;
 225         else if (i2c_spd >= IC_SPEED_MODE_HIGH)
 226                 spk_cnt = readl(&regs->hs_spklen);
 227         else
 228                 spk_cnt = readl(&regs->fs_spklen);
 229         if (scl_sda_cfg) {
 230                 config->sda_hold = scl_sda_cfg->sda_hold;
 231                 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
 232                         config->scl_hcnt = scl_sda_cfg->ss_hcnt;
 233                         config->scl_lcnt = scl_sda_cfg->ss_lcnt;
 234                 } else {
 235                         config->scl_hcnt = scl_sda_cfg->fs_hcnt;
 236                         config->scl_lcnt = scl_sda_cfg->fs_lcnt;
 237                 }
 238         } else {
 239                 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
 240                                          config);
 241                 if (ret)
 242                         return log_msg_ret("gen_confg", ret);
 243         }
 244         config->speed_mode = i2c_spd;
 245
 246         return 0;
 247 }
 248
 249 /*
 250  * _dw_i2c_set_bus_speed - Set the i2c speed
 251  * @speed:      required i2c speed
 252  *
 253  * Set the i2c speed.
 254  */
 255 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
 256                                  unsigned int speed, unsigned int bus_clk)
 257 {
 258         struct dw_i2c_speed_config config;
 259         unsigned int cntl;
 260         unsigned int ena;
 261         int ret;
 262
 263         ret = calc_bus_speed(priv, speed, bus_clk, &config);
 264         if (ret)
 265                 return ret;
 266
 267         /* Get enable setting for restore later */
 268         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
 269
 270         /* to set speed cltr must be disabled */
 271         dw_i2c_enable(i2c_base, false);
 272
 273         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 274
 275         switch (config.speed_mode) {
 276         case IC_SPEED_MODE_HIGH:
 277                 cntl |= IC_CON_SPD_SS;
 278                 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
 279                 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
 280                 break;
 281         case IC_SPEED_MODE_STANDARD:
 282                 cntl |= IC_CON_SPD_SS;
 283                 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
 284                 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
 285                 break;
 286         case IC_SPEED_MODE_FAST_PLUS:
 287         case IC_SPEED_MODE_FAST:
 288         default:
 289                 cntl |= IC_CON_SPD_FS;
 290                 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
 291                 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
 292                 break;
 293         }
 294
 295         writel(cntl, &i2c_base->ic_con);
 296
 297         /* Configure SDA Hold Time if required */
 298         if (config.sda_hold)
 299                 writel(config.sda_hold, &i2c_base->ic_sda_hold);
 300
 301         /* Restore back i2c now speed set */
 302         if (ena == IC_ENABLE_0B)
 303                 dw_i2c_enable(i2c_base, true);
 304
 305         return 0;
 306 }
 307
 308 /*
 309  * i2c_setaddress - Sets the target slave address
 310  * @i2c_addr:   target i2c address
 311  *
 312  * Sets the target slave address.
 313  */
 314 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 315 {
 316         /* Disable i2c */
 317         dw_i2c_enable(i2c_base, false);
 318
 319         writel(i2c_addr, &i2c_base->ic_tar);
 320
 321         /* Enable i2c */
 322         dw_i2c_enable(i2c_base, true);
 323 }
 324
 325 /*
 326  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 327  *
 328  * Flushes the i2c RX FIFO
 329  */
 330 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 331 {
 332         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 333                 readl(&i2c_base->ic_cmd_data);
 334 }
 335
 336 /*
 337  * i2c_wait_for_bb - Waits for bus busy
 338  *
 339  * Waits for bus busy
 340  */
 341 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 342 {
 343         unsigned long start_time_bb = get_timer(0);
 344
 345         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 346                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 347
 348                 /* Evaluate timeout */
 349                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 350                         return 1;
 351         }
 352
 353         return 0;
 354 }
 355
 356 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 357                          int alen)
 358 {
 359         if (i2c_wait_for_bb(i2c_base))
 360                 return 1;
 361
 362         i2c_setaddress(i2c_base, chip);
 363         while (alen) {
 364                 alen--;
 365                 /* high byte address going out first */
 366                 writel((addr >> (alen * 8)) & 0xff,
 367                        &i2c_base->ic_cmd_data);
 368         }
 369         return 0;
 370 }
 371
 372 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 373 {
 374         ulong start_stop_det = get_timer(0);
 375
 376         while (1) {
 377                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 378                         readl(&i2c_base->ic_clr_stop_det);
 379                         break;
 380                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 381                         break;
 382                 }
 383         }
 384
 385         if (i2c_wait_for_bb(i2c_base)) {
 386                 printf("Timed out waiting for bus\n");
 387                 return 1;
 388         }
 389
 390         i2c_flush_rxfifo(i2c_base);
 391
 392         return 0;
 393 }
 394
 395 /*
 396  * i2c_read - Read from i2c memory
 397  * @chip:       target i2c address
 398  * @addr:       address to read from
 399  * @alen:
 400  * @buffer:     buffer for read data
 401  * @len:        no of bytes to be read
 402  *
 403  * Read from i2c memory.
 404  */
 405 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 406                          int alen, u8 *buffer, int len)
 407 {
 408         unsigned long start_time_rx;
 409         unsigned int active = 0;
 410
 411 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 412         /*
 413          * EEPROM chips that implement "address overflow" are ones
 414          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 415          * address and the extra bits end up in the "chip address"
 416          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 417          * four 256 byte chips.
 418          *
 419          * Note that we consider the length of the address field to
 420          * still be one byte because the extra address bits are
 421          * hidden in the chip address.
 422          */
 423         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 424         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 425
 426         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 427               addr);
 428 #endif
 429
 430         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 431                 return 1;
 432
 433         start_time_rx = get_timer(0);
 434         while (len) {
 435                 if (!active) {
 436                         /*
 437                          * Avoid writing to ic_cmd_data multiple times
 438                          * in case this loop spins too quickly and the
 439                          * ic_status RFNE bit isn't set after the first
 440                          * write. Subsequent writes to ic_cmd_data can
 441                          * trigger spurious i2c transfer.
 442                          */
 443                         if (len == 1)
 444                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 445                         else
 446                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 447                         active = 1;
 448                 }
 449
 450                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 451                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 452                         len--;
 453                         start_time_rx = get_timer(0);
 454                         active = 0;
 455                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 456                         return 1;
 457                 }
 458         }
 459
 460         return i2c_xfer_finish(i2c_base);
 461 }
 462
 463 /*
 464  * i2c_write - Write to i2c memory
 465  * @chip:       target i2c address
 466  * @addr:       address to read from
 467  * @alen:
 468  * @buffer:     buffer for read data
 469  * @len:        no of bytes to be read
 470  *
 471  * Write to i2c memory.
 472  */
 473 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 474                           int alen, u8 *buffer, int len)
 475 {
 476         int nb = len;
 477         unsigned long start_time_tx;
 478
 479 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 480         /*
 481          * EEPROM chips that implement "address overflow" are ones
 482          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 483          * address and the extra bits end up in the "chip address"
 484          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 485          * four 256 byte chips.
 486          *
 487          * Note that we consider the length of the address field to
 488          * still be one byte because the extra address bits are
 489          * hidden in the chip address.
 490          */
 491         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 492         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 493
 494         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 495               addr);
 496 #endif
 497
 498         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 499                 return 1;
 500
 501         start_time_tx = get_timer(0);
 502         while (len) {
 503                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 504                         if (--len == 0) {
 505                                 writel(*buffer | IC_STOP,
 506                                        &i2c_base->ic_cmd_data);
 507                         } else {
 508                                 writel(*buffer, &i2c_base->ic_cmd_data);
 509                         }
 510                         buffer++;
 511                         start_time_tx = get_timer(0);
 512
 513                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 514                                 printf("Timed out. i2c write Failed\n");
 515                                 return 1;
 516                 }
 517         }
 518
 519         return i2c_xfer_finish(i2c_base);
 520 }
 521
 522 /*
 523  * __dw_i2c_init - Init function
 524  * @speed:      required i2c speed
 525  * @slaveaddr:  slave address for the device
 526  *
 527  * Initialization function.
 528  */
 529 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 530 {
 531         int ret;
 532
 533         /* Disable i2c */
 534         ret = dw_i2c_enable(i2c_base, false);
 535         if (ret)
 536                 return ret;
 537
 538         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 539                &i2c_base->ic_con);
 540         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 541         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 542         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 543 #ifndef CONFIG_DM_I2C
 544         _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
 545         writel(slaveaddr, &i2c_base->ic_sar);
 546 #endif
 547
 548         /* Enable i2c */
 549         ret = dw_i2c_enable(i2c_base, true);
 550         if (ret)
 551                 return ret;
 552
 553         return 0;
 554 }
 555
 556 #ifndef CONFIG_DM_I2C
 557 /*
 558  * The legacy I2C functions. These need to get removed once
 559  * all users of this driver are converted to DM.
 560  */
 561 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 562 {
 563         switch (adap->hwadapnr) {
 564 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 565         case 3:
 566                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 567 #endif
 568 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 569         case 2:
 570                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 571 #endif
 572 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 573         case 1:
 574                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 575 #endif
 576         case 0:
 577                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 578         default:
 579                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 580         }
 581
 582         return NULL;
 583 }
 584
 585 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 586                                          unsigned int speed)
 587 {
 588         adap->speed = speed;
 589         return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
 590 }
 591
 592 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 593 {
 594         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 595 }
 596
 597 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 598                        int alen, u8 *buffer, int len)
 599 {
 600         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 601 }
 602
 603 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 604                         int alen, u8 *buffer, int len)
 605 {
 606         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 607 }
 608
 609 /* dw_i2c_probe - Probe the i2c chip */
 610 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 611 {
 612         struct i2c_regs *i2c_base = i2c_get_base(adap);
 613         u32 tmp;
 614         int ret;
 615
 616         /*
 617          * Try to read the first location of the chip.
 618          */
 619         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 620         if (ret)
 621                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 622
 623         return ret;
 624 }
 625
 626 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 627                          dw_i2c_write, dw_i2c_set_bus_speed,
 628                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 629
 630 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 631 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 632                          dw_i2c_write, dw_i2c_set_bus_speed,
 633                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 634 #endif
 635
 636 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 637 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 638                          dw_i2c_write, dw_i2c_set_bus_speed,
 639                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 640 #endif
 641
 642 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 643 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 644                          dw_i2c_write, dw_i2c_set_bus_speed,
 645                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 646 #endif
 647
 648 #else /* CONFIG_DM_I2C */
 649 /* The DM I2C functions */
 650
 651 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 652                                int nmsgs)
 653 {
 654         struct dw_i2c *i2c = dev_get_priv(bus);
 655         int ret;
 656
 657         debug("i2c_xfer: %d messages\n", nmsgs);
 658         for (; nmsgs > 0; nmsgs--, msg++) {
 659                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 660                 if (msg->flags & I2C_M_RD) {
 661                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 662                                             msg->buf, msg->len);
 663                 } else {
 664                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 665                                              msg->buf, msg->len);
 666                 }
 667                 if (ret) {
 668                         debug("i2c_write: error sending\n");
 669                         return -EREMOTEIO;
 670                 }
 671         }
 672
 673         return 0;
 674 }
 675
 676 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 677 {
 678         struct dw_i2c *i2c = dev_get_priv(bus);
 679         ulong rate;
 680
 681 #if CONFIG_IS_ENABLED(CLK)
 682         rate = clk_get_rate(&i2c->clk);
 683         if (IS_ERR_VALUE(rate))
 684                 return -EINVAL;
 685 #else
 686         rate = IC_CLK;
 687 #endif
 688         return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
 689 }
 690
 691 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 692                                      uint chip_flags)
 693 {
 694         struct dw_i2c *i2c = dev_get_priv(bus);
 695         struct i2c_regs *i2c_base = i2c->regs;
 696         u32 tmp;
 697         int ret;
 698
 699         /* Try to read the first location of the chip */
 700         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 701         if (ret)
 702                 __dw_i2c_init(i2c_base, 0, 0);
 703
 704         return ret;
 705 }
 706
 707 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 708 {
 709         struct dw_i2c *priv = dev_get_priv(bus);
 710         int ret;
 711
 712         if (!priv->regs)
 713                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 714         dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
 715         dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
 716         dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
 717
 718         ret = reset_get_bulk(bus, &priv->resets);
 719         if (ret)
 720                 dev_warn(bus, "Can't get reset: %d\n", ret);
 721         else
 722                 reset_deassert_bulk(&priv->resets);
 723
 724 #if CONFIG_IS_ENABLED(CLK)
 725         ret = clk_get_by_index(bus, 0, &priv->clk);
 726         if (ret)
 727                 return ret;
 728
 729         ret = clk_enable(&priv->clk);
 730         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 731                 clk_free(&priv->clk);
 732                 dev_err(bus, "failed to enable clock\n");
 733                 return ret;
 734         }
 735 #endif
 736
 737         return 0;
 738 }
 739
 740 int designware_i2c_probe(struct udevice *bus)
 741 {
 742         struct dw_i2c *priv = dev_get_priv(bus);
 743
 744         return __dw_i2c_init(priv->regs, 0, 0);
 745 }
 746
 747 int designware_i2c_remove(struct udevice *dev)
 748 {
 749         struct dw_i2c *priv = dev_get_priv(dev);
 750
 751 #if CONFIG_IS_ENABLED(CLK)
 752         clk_disable(&priv->clk);
 753         clk_free(&priv->clk);
 754 #endif
 755
 756         return reset_release_bulk(&priv->resets);
 757 }
 758
 759 const struct dm_i2c_ops designware_i2c_ops = {
 760         .xfer           = designware_i2c_xfer,
 761         .probe_chip     = designware_i2c_probe_chip,
 762         .set_bus_speed  = designware_i2c_set_bus_speed,
 763 };
 764
 765 static const struct udevice_id designware_i2c_ids[] = {
 766         { .compatible = "snps,designware-i2c" },
 767         { }
 768 };
 769
 770 U_BOOT_DRIVER(i2c_designware) = {
 771         .name   = "i2c_designware",
 772         .id     = UCLASS_I2C,
 773         .of_match = designware_i2c_ids,
 774         .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
 775         .probe  = designware_i2c_probe,
 776         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 777         .remove = designware_i2c_remove,
 778         .flags  = DM_FLAG_OS_PREPARE,
 779         .ops    = &designware_i2c_ops,
 780 };
 781
 782 #endif /* CONFIG_DM_I2C */