3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include "designware_i2c.h"
15 struct dw_scl_sda_cfg {
24 /* BayTrail HCNT/LCNT/SDA hold time */
25 static struct dw_scl_sda_cfg byt_config = {
35 struct i2c_regs *regs;
36 struct dw_scl_sda_cfg *scl_sda_cfg;
39 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
40 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
42 u32 ena = enable ? IC_ENABLE_0B : 0;
44 writel(ena, &i2c_base->ic_enable);
47 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
49 u32 ena = enable ? IC_ENABLE_0B : 0;
53 writel(ena, &i2c_base->ic_enable);
54 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
58 * Wait 10 times the signaling period of the highest I2C
59 * transfer supported by the driver (for 400KHz this is
60 * 25us) as described in the DesignWare I2C databook.
65 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
70 * i2c_set_bus_speed - Set the i2c speed
71 * @speed: required i2c speed
75 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
76 struct dw_scl_sda_cfg *scl_sda_cfg,
80 unsigned int hcnt, lcnt;
83 if (speed >= I2C_MAX_SPEED)
84 i2c_spd = IC_SPEED_MODE_MAX;
85 else if (speed >= I2C_FAST_SPEED)
86 i2c_spd = IC_SPEED_MODE_FAST;
88 i2c_spd = IC_SPEED_MODE_STANDARD;
90 /* to set speed cltr must be disabled */
91 dw_i2c_enable(i2c_base, false);
93 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
96 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
97 case IC_SPEED_MODE_MAX:
98 cntl |= IC_CON_SPD_SS;
100 hcnt = scl_sda_cfg->fs_hcnt;
101 lcnt = scl_sda_cfg->fs_lcnt;
103 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
104 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
106 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
107 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
111 case IC_SPEED_MODE_STANDARD:
112 cntl |= IC_CON_SPD_SS;
114 hcnt = scl_sda_cfg->ss_hcnt;
115 lcnt = scl_sda_cfg->ss_lcnt;
117 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
118 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
120 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
121 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
124 case IC_SPEED_MODE_FAST:
126 cntl |= IC_CON_SPD_FS;
128 hcnt = scl_sda_cfg->fs_hcnt;
129 lcnt = scl_sda_cfg->fs_lcnt;
131 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
132 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
134 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
135 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
139 writel(cntl, &i2c_base->ic_con);
141 /* Configure SDA Hold Time if required */
143 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
145 /* Enable back i2c now speed set */
146 dw_i2c_enable(i2c_base, true);
152 * i2c_setaddress - Sets the target slave address
153 * @i2c_addr: target i2c address
155 * Sets the target slave address.
157 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
160 dw_i2c_enable(i2c_base, false);
162 writel(i2c_addr, &i2c_base->ic_tar);
165 dw_i2c_enable(i2c_base, true);
169 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
171 * Flushes the i2c RX FIFO
173 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
175 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
176 readl(&i2c_base->ic_cmd_data);
180 * i2c_wait_for_bb - Waits for bus busy
184 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
186 unsigned long start_time_bb = get_timer(0);
188 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
189 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
191 /* Evaluate timeout */
192 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
199 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
202 if (i2c_wait_for_bb(i2c_base))
205 i2c_setaddress(i2c_base, chip);
208 /* high byte address going out first */
209 writel((addr >> (alen * 8)) & 0xff,
210 &i2c_base->ic_cmd_data);
215 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
217 ulong start_stop_det = get_timer(0);
220 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
221 readl(&i2c_base->ic_clr_stop_det);
223 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
228 if (i2c_wait_for_bb(i2c_base)) {
229 printf("Timed out waiting for bus\n");
233 i2c_flush_rxfifo(i2c_base);
239 * i2c_read - Read from i2c memory
240 * @chip: target i2c address
241 * @addr: address to read from
243 * @buffer: buffer for read data
244 * @len: no of bytes to be read
246 * Read from i2c memory.
248 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
249 int alen, u8 *buffer, int len)
251 unsigned long start_time_rx;
253 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
255 * EEPROM chips that implement "address overflow" are ones
256 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
257 * address and the extra bits end up in the "chip address"
258 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
259 * four 256 byte chips.
261 * Note that we consider the length of the address field to
262 * still be one byte because the extra address bits are
263 * hidden in the chip address.
265 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
266 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
268 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
272 if (i2c_xfer_init(i2c_base, dev, addr, alen))
275 start_time_rx = get_timer(0);
278 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
280 writel(IC_CMD, &i2c_base->ic_cmd_data);
282 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
283 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
285 start_time_rx = get_timer(0);
287 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
292 return i2c_xfer_finish(i2c_base);
296 * i2c_write - Write to i2c memory
297 * @chip: target i2c address
298 * @addr: address to read from
300 * @buffer: buffer for read data
301 * @len: no of bytes to be read
303 * Write to i2c memory.
305 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
306 int alen, u8 *buffer, int len)
309 unsigned long start_time_tx;
311 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
313 * EEPROM chips that implement "address overflow" are ones
314 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
315 * address and the extra bits end up in the "chip address"
316 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
317 * four 256 byte chips.
319 * Note that we consider the length of the address field to
320 * still be one byte because the extra address bits are
321 * hidden in the chip address.
323 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
324 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
326 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
330 if (i2c_xfer_init(i2c_base, dev, addr, alen))
333 start_time_tx = get_timer(0);
335 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
337 writel(*buffer | IC_STOP,
338 &i2c_base->ic_cmd_data);
340 writel(*buffer, &i2c_base->ic_cmd_data);
343 start_time_tx = get_timer(0);
345 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
346 printf("Timed out. i2c write Failed\n");
351 return i2c_xfer_finish(i2c_base);
355 * __dw_i2c_init - Init function
356 * @speed: required i2c speed
357 * @slaveaddr: slave address for the device
359 * Initialization function.
361 static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
364 dw_i2c_enable(i2c_base, false);
366 writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
367 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
368 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
369 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
370 #ifndef CONFIG_DM_I2C
371 __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
372 writel(slaveaddr, &i2c_base->ic_sar);
376 dw_i2c_enable(i2c_base, true);
379 #ifndef CONFIG_DM_I2C
381 * The legacy I2C functions. These need to get removed once
382 * all users of this driver are converted to DM.
384 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
386 switch (adap->hwadapnr) {
387 #if CONFIG_SYS_I2C_BUS_MAX >= 4
389 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
391 #if CONFIG_SYS_I2C_BUS_MAX >= 3
393 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
395 #if CONFIG_SYS_I2C_BUS_MAX >= 2
397 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
400 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
402 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
408 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
412 return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
415 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
417 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
420 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
421 int alen, u8 *buffer, int len)
423 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
426 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
427 int alen, u8 *buffer, int len)
429 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
432 /* dw_i2c_probe - Probe the i2c chip */
433 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
435 struct i2c_regs *i2c_base = i2c_get_base(adap);
440 * Try to read the first location of the chip.
442 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
444 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
449 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
450 dw_i2c_write, dw_i2c_set_bus_speed,
451 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
453 #if CONFIG_SYS_I2C_BUS_MAX >= 2
454 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
455 dw_i2c_write, dw_i2c_set_bus_speed,
456 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
459 #if CONFIG_SYS_I2C_BUS_MAX >= 3
460 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
461 dw_i2c_write, dw_i2c_set_bus_speed,
462 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
465 #if CONFIG_SYS_I2C_BUS_MAX >= 4
466 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
467 dw_i2c_write, dw_i2c_set_bus_speed,
468 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
471 #else /* CONFIG_DM_I2C */
472 /* The DM I2C functions */
474 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
477 struct dw_i2c *i2c = dev_get_priv(bus);
480 debug("i2c_xfer: %d messages\n", nmsgs);
481 for (; nmsgs > 0; nmsgs--, msg++) {
482 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
483 if (msg->flags & I2C_M_RD) {
484 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
487 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
491 debug("i2c_write: error sending\n");
499 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
501 struct dw_i2c *i2c = dev_get_priv(bus);
503 return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
506 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
509 struct dw_i2c *i2c = dev_get_priv(bus);
510 struct i2c_regs *i2c_base = i2c->regs;
514 /* Try to read the first location of the chip */
515 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
517 __dw_i2c_init(i2c_base, 0, 0);
522 static int designware_i2c_probe(struct udevice *bus)
524 struct dw_i2c *priv = dev_get_priv(bus);
526 if (device_is_on_pci_bus(bus)) {
528 /* Save base address from PCI BAR */
529 priv->regs = (struct i2c_regs *)
530 dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
532 /* Use BayTrail specific timing values */
533 priv->scl_sda_cfg = &byt_config;
537 priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus);
540 __dw_i2c_init(priv->regs, 0, 0);
545 static int designware_i2c_bind(struct udevice *dev)
547 static int num_cards;
550 /* Create a unique device name for PCI type devices */
551 if (device_is_on_pci_bus(dev)) {
554 * Setting req_seq in the driver is probably not recommended.
555 * But without a DT alias the number is not configured. And
556 * using this driver is impossible for PCIe I2C devices.
557 * This can be removed, once a better (correct) way for this
558 * is found and implemented.
560 dev->req_seq = num_cards;
561 sprintf(name, "i2c_designware#%u", num_cards++);
562 device_set_name(dev, name);
568 static const struct dm_i2c_ops designware_i2c_ops = {
569 .xfer = designware_i2c_xfer,
570 .probe_chip = designware_i2c_probe_chip,
571 .set_bus_speed = designware_i2c_set_bus_speed,
574 static const struct udevice_id designware_i2c_ids[] = {
575 { .compatible = "snps,designware-i2c" },
579 U_BOOT_DRIVER(i2c_designware) = {
580 .name = "i2c_designware",
582 .of_match = designware_i2c_ids,
583 .bind = designware_i2c_bind,
584 .probe = designware_i2c_probe,
585 .priv_auto_alloc_size = sizeof(struct dw_i2c),
586 .ops = &designware_i2c_ops,
590 static struct pci_device_id designware_pci_supported[] = {
591 /* Intel BayTrail has 7 I2C controller located on the PCI bus */
592 { PCI_VDEVICE(INTEL, 0x0f41) },
593 { PCI_VDEVICE(INTEL, 0x0f42) },
594 { PCI_VDEVICE(INTEL, 0x0f43) },
595 { PCI_VDEVICE(INTEL, 0x0f44) },
596 { PCI_VDEVICE(INTEL, 0x0f45) },
597 { PCI_VDEVICE(INTEL, 0x0f46) },
598 { PCI_VDEVICE(INTEL, 0x0f47) },
602 U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
605 #endif /* CONFIG_DM_I2C */