drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <pci.h>
  12 #include <reset.h>
  13 #include <asm/io.h>
  14 #include "designware_i2c.h"
  15
  16 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  17 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  18 {
  19         u32 ena = enable ? IC_ENABLE_0B : 0;
  20
  21         writel(ena, &i2c_base->ic_enable);
  22
  23         return 0;
  24 }
  25 #else
  26 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  27 {
  28         u32 ena = enable ? IC_ENABLE_0B : 0;
  29         int timeout = 100;
  30
  31         do {
  32                 writel(ena, &i2c_base->ic_enable);
  33                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  34                         return 0;
  35
  36                 /*
  37                  * Wait 10 times the signaling period of the highest I2C
  38                  * transfer supported by the driver (for 400KHz this is
  39                  * 25us) as described in the DesignWare I2C databook.
  40                  */
  41                 udelay(25);
  42         } while (timeout--);
  43         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  44
  45         return -ETIMEDOUT;
  46 }
  47 #endif
  48
  49 /*
  50  * i2c_set_bus_speed - Set the i2c speed
  51  * @speed:      required i2c speed
  52  *
  53  * Set the i2c speed.
  54  */
  55 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
  56                                            struct dw_scl_sda_cfg *scl_sda_cfg,
  57                                            unsigned int speed,
  58                                            unsigned int bus_clk)
  59 {
  60         ulong bus_khz = bus_clk / 1000;
  61         enum i2c_speed_mode i2c_spd;
  62         unsigned int cntl;
  63         unsigned int hcnt, lcnt;
  64         unsigned int ena;
  65
  66         /* Allow high speed if there is no config, or the config allows it */
  67         if (speed >= I2C_HIGH_SPEED &&
  68             (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
  69                 i2c_spd = IC_SPEED_MODE_HIGH;
  70         else if (speed >= I2C_FAST_SPEED)
  71                 i2c_spd = IC_SPEED_MODE_FAST;
  72         else
  73                 i2c_spd = IC_SPEED_MODE_STANDARD;
  74
  75         /* Get enable setting for restore later */
  76         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
  77
  78         /* to set speed cltr must be disabled */
  79         dw_i2c_enable(i2c_base, false);
  80
  81         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
  82
  83         switch (i2c_spd) {
  84         case IC_SPEED_MODE_HIGH:
  85                 cntl |= IC_CON_SPD_SS;
  86                 if (scl_sda_cfg) {
  87                         hcnt = scl_sda_cfg->fs_hcnt;
  88                         lcnt = scl_sda_cfg->fs_lcnt;
  89                 } else {
  90                         hcnt = (bus_khz * MIN_HS_SCL_HIGHTIME) / NANO_TO_KILO;
  91                         lcnt = (bus_khz * MIN_HS_SCL_LOWTIME) / NANO_TO_KILO;
  92                 }
  93                 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
  94                 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
  95                 break;
  96
  97         case IC_SPEED_MODE_STANDARD:
  98                 cntl |= IC_CON_SPD_SS;
  99                 if (scl_sda_cfg) {
 100                         hcnt = scl_sda_cfg->ss_hcnt;
 101                         lcnt = scl_sda_cfg->ss_lcnt;
 102                 } else {
 103                         hcnt = (bus_khz * MIN_SS_SCL_HIGHTIME) / NANO_TO_KILO;
 104                         lcnt = (bus_khz * MIN_SS_SCL_LOWTIME) / NANO_TO_KILO;
 105                 }
 106                 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
 107                 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
 108                 break;
 109
 110         case IC_SPEED_MODE_FAST:
 111         default:
 112                 cntl |= IC_CON_SPD_FS;
 113                 if (scl_sda_cfg) {
 114                         hcnt = scl_sda_cfg->fs_hcnt;
 115                         lcnt = scl_sda_cfg->fs_lcnt;
 116                 } else {
 117                         hcnt = (bus_khz * MIN_FS_SCL_HIGHTIME) / NANO_TO_KILO;
 118                         lcnt = (bus_khz * MIN_FS_SCL_LOWTIME) / NANO_TO_KILO;
 119                 }
 120                 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
 121                 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
 122                 break;
 123         }
 124
 125         writel(cntl, &i2c_base->ic_con);
 126
 127         /* Configure SDA Hold Time if required */
 128         if (scl_sda_cfg)
 129                 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
 130
 131         /* Restore back i2c now speed set */
 132         if (ena == IC_ENABLE_0B)
 133                 dw_i2c_enable(i2c_base, true);
 134
 135         return 0;
 136 }
 137
 138 /*
 139  * i2c_setaddress - Sets the target slave address
 140  * @i2c_addr:   target i2c address
 141  *
 142  * Sets the target slave address.
 143  */
 144 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 145 {
 146         /* Disable i2c */
 147         dw_i2c_enable(i2c_base, false);
 148
 149         writel(i2c_addr, &i2c_base->ic_tar);
 150
 151         /* Enable i2c */
 152         dw_i2c_enable(i2c_base, true);
 153 }
 154
 155 /*
 156  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 157  *
 158  * Flushes the i2c RX FIFO
 159  */
 160 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 161 {
 162         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 163                 readl(&i2c_base->ic_cmd_data);
 164 }
 165
 166 /*
 167  * i2c_wait_for_bb - Waits for bus busy
 168  *
 169  * Waits for bus busy
 170  */
 171 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 172 {
 173         unsigned long start_time_bb = get_timer(0);
 174
 175         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 176                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 177
 178                 /* Evaluate timeout */
 179                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 180                         return 1;
 181         }
 182
 183         return 0;
 184 }
 185
 186 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 187                          int alen)
 188 {
 189         if (i2c_wait_for_bb(i2c_base))
 190                 return 1;
 191
 192         i2c_setaddress(i2c_base, chip);
 193         while (alen) {
 194                 alen--;
 195                 /* high byte address going out first */
 196                 writel((addr >> (alen * 8)) & 0xff,
 197                        &i2c_base->ic_cmd_data);
 198         }
 199         return 0;
 200 }
 201
 202 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 203 {
 204         ulong start_stop_det = get_timer(0);
 205
 206         while (1) {
 207                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 208                         readl(&i2c_base->ic_clr_stop_det);
 209                         break;
 210                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 211                         break;
 212                 }
 213         }
 214
 215         if (i2c_wait_for_bb(i2c_base)) {
 216                 printf("Timed out waiting for bus\n");
 217                 return 1;
 218         }
 219
 220         i2c_flush_rxfifo(i2c_base);
 221
 222         return 0;
 223 }
 224
 225 /*
 226  * i2c_read - Read from i2c memory
 227  * @chip:       target i2c address
 228  * @addr:       address to read from
 229  * @alen:
 230  * @buffer:     buffer for read data
 231  * @len:        no of bytes to be read
 232  *
 233  * Read from i2c memory.
 234  */
 235 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 236                          int alen, u8 *buffer, int len)
 237 {
 238         unsigned long start_time_rx;
 239         unsigned int active = 0;
 240
 241 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 242         /*
 243          * EEPROM chips that implement "address overflow" are ones
 244          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 245          * address and the extra bits end up in the "chip address"
 246          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 247          * four 256 byte chips.
 248          *
 249          * Note that we consider the length of the address field to
 250          * still be one byte because the extra address bits are
 251          * hidden in the chip address.
 252          */
 253         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 254         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 255
 256         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 257               addr);
 258 #endif
 259
 260         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 261                 return 1;
 262
 263         start_time_rx = get_timer(0);
 264         while (len) {
 265                 if (!active) {
 266                         /*
 267                          * Avoid writing to ic_cmd_data multiple times
 268                          * in case this loop spins too quickly and the
 269                          * ic_status RFNE bit isn't set after the first
 270                          * write. Subsequent writes to ic_cmd_data can
 271                          * trigger spurious i2c transfer.
 272                          */
 273                         if (len == 1)
 274                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 275                         else
 276                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 277                         active = 1;
 278                 }
 279
 280                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 281                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 282                         len--;
 283                         start_time_rx = get_timer(0);
 284                         active = 0;
 285                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 286                         return 1;
 287                 }
 288         }
 289
 290         return i2c_xfer_finish(i2c_base);
 291 }
 292
 293 /*
 294  * i2c_write - Write to i2c memory
 295  * @chip:       target i2c address
 296  * @addr:       address to read from
 297  * @alen:
 298  * @buffer:     buffer for read data
 299  * @len:        no of bytes to be read
 300  *
 301  * Write to i2c memory.
 302  */
 303 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 304                           int alen, u8 *buffer, int len)
 305 {
 306         int nb = len;
 307         unsigned long start_time_tx;
 308
 309 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 310         /*
 311          * EEPROM chips that implement "address overflow" are ones
 312          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 313          * address and the extra bits end up in the "chip address"
 314          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 315          * four 256 byte chips.
 316          *
 317          * Note that we consider the length of the address field to
 318          * still be one byte because the extra address bits are
 319          * hidden in the chip address.
 320          */
 321         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 322         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 323
 324         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 325               addr);
 326 #endif
 327
 328         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 329                 return 1;
 330
 331         start_time_tx = get_timer(0);
 332         while (len) {
 333                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 334                         if (--len == 0) {
 335                                 writel(*buffer | IC_STOP,
 336                                        &i2c_base->ic_cmd_data);
 337                         } else {
 338                                 writel(*buffer, &i2c_base->ic_cmd_data);
 339                         }
 340                         buffer++;
 341                         start_time_tx = get_timer(0);
 342
 343                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 344                                 printf("Timed out. i2c write Failed\n");
 345                                 return 1;
 346                 }
 347         }
 348
 349         return i2c_xfer_finish(i2c_base);
 350 }
 351
 352 /*
 353  * __dw_i2c_init - Init function
 354  * @speed:      required i2c speed
 355  * @slaveaddr:  slave address for the device
 356  *
 357  * Initialization function.
 358  */
 359 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 360 {
 361         int ret;
 362
 363         /* Disable i2c */
 364         ret = dw_i2c_enable(i2c_base, false);
 365         if (ret)
 366                 return ret;
 367
 368         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 369                &i2c_base->ic_con);
 370         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 371         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 372         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 373 #ifndef CONFIG_DM_I2C
 374         __dw_i2c_set_bus_speed(i2c_base, NULL, speed, IC_CLK);
 375         writel(slaveaddr, &i2c_base->ic_sar);
 376 #endif
 377
 378         /* Enable i2c */
 379         ret = dw_i2c_enable(i2c_base, true);
 380         if (ret)
 381                 return ret;
 382
 383         return 0;
 384 }
 385
 386 #ifndef CONFIG_DM_I2C
 387 /*
 388  * The legacy I2C functions. These need to get removed once
 389  * all users of this driver are converted to DM.
 390  */
 391 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 392 {
 393         switch (adap->hwadapnr) {
 394 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 395         case 3:
 396                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 397 #endif
 398 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 399         case 2:
 400                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 401 #endif
 402 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 403         case 1:
 404                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 405 #endif
 406         case 0:
 407                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 408         default:
 409                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 410         }
 411
 412         return NULL;
 413 }
 414
 415 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 416                                          unsigned int speed)
 417 {
 418         adap->speed = speed;
 419         return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed, IC_CLK);
 420 }
 421
 422 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 423 {
 424         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 425 }
 426
 427 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 428                        int alen, u8 *buffer, int len)
 429 {
 430         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 431 }
 432
 433 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 434                         int alen, u8 *buffer, int len)
 435 {
 436         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 437 }
 438
 439 /* dw_i2c_probe - Probe the i2c chip */
 440 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 441 {
 442         struct i2c_regs *i2c_base = i2c_get_base(adap);
 443         u32 tmp;
 444         int ret;
 445
 446         /*
 447          * Try to read the first location of the chip.
 448          */
 449         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 450         if (ret)
 451                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 452
 453         return ret;
 454 }
 455
 456 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 457                          dw_i2c_write, dw_i2c_set_bus_speed,
 458                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 459
 460 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 461 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 462                          dw_i2c_write, dw_i2c_set_bus_speed,
 463                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 464 #endif
 465
 466 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 467 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 468                          dw_i2c_write, dw_i2c_set_bus_speed,
 469                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 470 #endif
 471
 472 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 473 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 474                          dw_i2c_write, dw_i2c_set_bus_speed,
 475                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 476 #endif
 477
 478 #else /* CONFIG_DM_I2C */
 479 /* The DM I2C functions */
 480
 481 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 482                                int nmsgs)
 483 {
 484         struct dw_i2c *i2c = dev_get_priv(bus);
 485         int ret;
 486
 487         debug("i2c_xfer: %d messages\n", nmsgs);
 488         for (; nmsgs > 0; nmsgs--, msg++) {
 489                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 490                 if (msg->flags & I2C_M_RD) {
 491                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 492                                             msg->buf, msg->len);
 493                 } else {
 494                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 495                                              msg->buf, msg->len);
 496                 }
 497                 if (ret) {
 498                         debug("i2c_write: error sending\n");
 499                         return -EREMOTEIO;
 500                 }
 501         }
 502
 503         return 0;
 504 }
 505
 506 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 507 {
 508         struct dw_i2c *i2c = dev_get_priv(bus);
 509         ulong rate;
 510
 511 #if CONFIG_IS_ENABLED(CLK)
 512         rate = clk_get_rate(&i2c->clk);
 513         if (IS_ERR_VALUE(rate))
 514                 return -EINVAL;
 515 #else
 516         rate = IC_CLK;
 517 #endif
 518         return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed,
 519                                       rate);
 520 }
 521
 522 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 523                                      uint chip_flags)
 524 {
 525         struct dw_i2c *i2c = dev_get_priv(bus);
 526         struct i2c_regs *i2c_base = i2c->regs;
 527         u32 tmp;
 528         int ret;
 529
 530         /* Try to read the first location of the chip */
 531         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 532         if (ret)
 533                 __dw_i2c_init(i2c_base, 0, 0);
 534
 535         return ret;
 536 }
 537
 538 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 539 {
 540         struct dw_i2c *priv = dev_get_priv(bus);
 541
 542         if (!priv->regs)
 543                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 544         dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
 545         dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
 546         dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
 547
 548         return 0;
 549 }
 550
 551 int designware_i2c_probe(struct udevice *bus)
 552 {
 553         struct dw_i2c *priv = dev_get_priv(bus);
 554         int ret;
 555
 556         ret = reset_get_bulk(bus, &priv->resets);
 557         if (ret)
 558                 dev_warn(bus, "Can't get reset: %d\n", ret);
 559         else
 560                 reset_deassert_bulk(&priv->resets);
 561
 562 #if CONFIG_IS_ENABLED(CLK)
 563         ret = clk_get_by_index(bus, 0, &priv->clk);
 564         if (ret)
 565                 return ret;
 566
 567         ret = clk_enable(&priv->clk);
 568         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 569                 clk_free(&priv->clk);
 570                 dev_err(bus, "failed to enable clock\n");
 571                 return ret;
 572         }
 573 #endif
 574
 575         return __dw_i2c_init(priv->regs, 0, 0);
 576 }
 577
 578 int designware_i2c_remove(struct udevice *dev)
 579 {
 580         struct dw_i2c *priv = dev_get_priv(dev);
 581
 582 #if CONFIG_IS_ENABLED(CLK)
 583         clk_disable(&priv->clk);
 584         clk_free(&priv->clk);
 585 #endif
 586
 587         return reset_release_bulk(&priv->resets);
 588 }
 589
 590 const struct dm_i2c_ops designware_i2c_ops = {
 591         .xfer           = designware_i2c_xfer,
 592         .probe_chip     = designware_i2c_probe_chip,
 593         .set_bus_speed  = designware_i2c_set_bus_speed,
 594 };
 595
 596 static const struct udevice_id designware_i2c_ids[] = {
 597         { .compatible = "snps,designware-i2c" },
 598         { }
 599 };
 600
 601 U_BOOT_DRIVER(i2c_designware) = {
 602         .name   = "i2c_designware",
 603         .id     = UCLASS_I2C,
 604         .of_match = designware_i2c_ids,
 605         .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
 606         .probe  = designware_i2c_probe,
 607         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 608         .remove = designware_i2c_remove,
 609         .flags  = DM_FLAG_OS_PREPARE,
 610         .ops    = &designware_i2c_ops,
 611 };
 612
 613 #endif /* CONFIG_DM_I2C */