drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <clk.h>
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <pci.h>
  12 #include <reset.h>
  13 #include <asm/io.h>
  14 #include "designware_i2c.h"
  15
  16 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  17 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  18 {
  19         u32 ena = enable ? IC_ENABLE_0B : 0;
  20
  21         writel(ena, &i2c_base->ic_enable);
  22
  23         return 0;
  24 }
  25 #else
  26 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  27 {
  28         u32 ena = enable ? IC_ENABLE_0B : 0;
  29         int timeout = 100;
  30
  31         do {
  32                 writel(ena, &i2c_base->ic_enable);
  33                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  34                         return 0;
  35
  36                 /*
  37                  * Wait 10 times the signaling period of the highest I2C
  38                  * transfer supported by the driver (for 400KHz this is
  39                  * 25us) as described in the DesignWare I2C databook.
  40                  */
  41                 udelay(25);
  42         } while (timeout--);
  43         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  44
  45         return -ETIMEDOUT;
  46 }
  47 #endif
  48
  49 /*
  50  * i2c_set_bus_speed - Set the i2c speed
  51  * @speed:      required i2c speed
  52  *
  53  * Set the i2c speed.
  54  */
  55 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
  56                                            struct dw_scl_sda_cfg *scl_sda_cfg,
  57                                            unsigned int speed,
  58                                            unsigned int bus_mhz)
  59 {
  60         unsigned int cntl;
  61         unsigned int hcnt, lcnt;
  62         unsigned int ena;
  63         int i2c_spd;
  64
  65         /* Allow max speed if there is no config, or the config allows it */
  66         if (speed >= I2C_MAX_SPEED &&
  67             (!scl_sda_cfg || scl_sda_cfg->has_max_speed))
  68                 i2c_spd = IC_SPEED_MODE_MAX;
  69         else if (speed >= I2C_FAST_SPEED)
  70                 i2c_spd = IC_SPEED_MODE_FAST;
  71         else
  72                 i2c_spd = IC_SPEED_MODE_STANDARD;
  73
  74         /* Get enable setting for restore later */
  75         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
  76
  77         /* to set speed cltr must be disabled */
  78         dw_i2c_enable(i2c_base, false);
  79
  80         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
  81
  82         switch (i2c_spd) {
  83         case IC_SPEED_MODE_MAX:
  84                 cntl |= IC_CON_SPD_SS;
  85                 if (scl_sda_cfg) {
  86                         hcnt = scl_sda_cfg->fs_hcnt;
  87                         lcnt = scl_sda_cfg->fs_lcnt;
  88                 } else {
  89                         hcnt = (bus_mhz * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
  90                         lcnt = (bus_mhz * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
  91                 }
  92                 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
  93                 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
  94                 break;
  95
  96         case IC_SPEED_MODE_STANDARD:
  97                 cntl |= IC_CON_SPD_SS;
  98                 if (scl_sda_cfg) {
  99                         hcnt = scl_sda_cfg->ss_hcnt;
 100                         lcnt = scl_sda_cfg->ss_lcnt;
 101                 } else {
 102                         hcnt = (bus_mhz * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
 103                         lcnt = (bus_mhz * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
 104                 }
 105                 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
 106                 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
 107                 break;
 108
 109         case IC_SPEED_MODE_FAST:
 110         default:
 111                 cntl |= IC_CON_SPD_FS;
 112                 if (scl_sda_cfg) {
 113                         hcnt = scl_sda_cfg->fs_hcnt;
 114                         lcnt = scl_sda_cfg->fs_lcnt;
 115                 } else {
 116                         hcnt = (bus_mhz * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
 117                         lcnt = (bus_mhz * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
 118                 }
 119                 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
 120                 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
 121                 break;
 122         }
 123
 124         writel(cntl, &i2c_base->ic_con);
 125
 126         /* Configure SDA Hold Time if required */
 127         if (scl_sda_cfg)
 128                 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
 129
 130         /* Restore back i2c now speed set */
 131         if (ena == IC_ENABLE_0B)
 132                 dw_i2c_enable(i2c_base, true);
 133
 134         return 0;
 135 }
 136
 137 /*
 138  * i2c_setaddress - Sets the target slave address
 139  * @i2c_addr:   target i2c address
 140  *
 141  * Sets the target slave address.
 142  */
 143 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 144 {
 145         /* Disable i2c */
 146         dw_i2c_enable(i2c_base, false);
 147
 148         writel(i2c_addr, &i2c_base->ic_tar);
 149
 150         /* Enable i2c */
 151         dw_i2c_enable(i2c_base, true);
 152 }
 153
 154 /*
 155  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 156  *
 157  * Flushes the i2c RX FIFO
 158  */
 159 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 160 {
 161         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 162                 readl(&i2c_base->ic_cmd_data);
 163 }
 164
 165 /*
 166  * i2c_wait_for_bb - Waits for bus busy
 167  *
 168  * Waits for bus busy
 169  */
 170 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 171 {
 172         unsigned long start_time_bb = get_timer(0);
 173
 174         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 175                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 176
 177                 /* Evaluate timeout */
 178                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 179                         return 1;
 180         }
 181
 182         return 0;
 183 }
 184
 185 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 186                          int alen)
 187 {
 188         if (i2c_wait_for_bb(i2c_base))
 189                 return 1;
 190
 191         i2c_setaddress(i2c_base, chip);
 192         while (alen) {
 193                 alen--;
 194                 /* high byte address going out first */
 195                 writel((addr >> (alen * 8)) & 0xff,
 196                        &i2c_base->ic_cmd_data);
 197         }
 198         return 0;
 199 }
 200
 201 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 202 {
 203         ulong start_stop_det = get_timer(0);
 204
 205         while (1) {
 206                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 207                         readl(&i2c_base->ic_clr_stop_det);
 208                         break;
 209                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 210                         break;
 211                 }
 212         }
 213
 214         if (i2c_wait_for_bb(i2c_base)) {
 215                 printf("Timed out waiting for bus\n");
 216                 return 1;
 217         }
 218
 219         i2c_flush_rxfifo(i2c_base);
 220
 221         return 0;
 222 }
 223
 224 /*
 225  * i2c_read - Read from i2c memory
 226  * @chip:       target i2c address
 227  * @addr:       address to read from
 228  * @alen:
 229  * @buffer:     buffer for read data
 230  * @len:        no of bytes to be read
 231  *
 232  * Read from i2c memory.
 233  */
 234 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 235                          int alen, u8 *buffer, int len)
 236 {
 237         unsigned long start_time_rx;
 238         unsigned int active = 0;
 239
 240 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 241         /*
 242          * EEPROM chips that implement "address overflow" are ones
 243          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 244          * address and the extra bits end up in the "chip address"
 245          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 246          * four 256 byte chips.
 247          *
 248          * Note that we consider the length of the address field to
 249          * still be one byte because the extra address bits are
 250          * hidden in the chip address.
 251          */
 252         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 253         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 254
 255         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 256               addr);
 257 #endif
 258
 259         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 260                 return 1;
 261
 262         start_time_rx = get_timer(0);
 263         while (len) {
 264                 if (!active) {
 265                         /*
 266                          * Avoid writing to ic_cmd_data multiple times
 267                          * in case this loop spins too quickly and the
 268                          * ic_status RFNE bit isn't set after the first
 269                          * write. Subsequent writes to ic_cmd_data can
 270                          * trigger spurious i2c transfer.
 271                          */
 272                         if (len == 1)
 273                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 274                         else
 275                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 276                         active = 1;
 277                 }
 278
 279                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 280                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 281                         len--;
 282                         start_time_rx = get_timer(0);
 283                         active = 0;
 284                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 285                         return 1;
 286                 }
 287         }
 288
 289         return i2c_xfer_finish(i2c_base);
 290 }
 291
 292 /*
 293  * i2c_write - Write to i2c memory
 294  * @chip:       target i2c address
 295  * @addr:       address to read from
 296  * @alen:
 297  * @buffer:     buffer for read data
 298  * @len:        no of bytes to be read
 299  *
 300  * Write to i2c memory.
 301  */
 302 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 303                           int alen, u8 *buffer, int len)
 304 {
 305         int nb = len;
 306         unsigned long start_time_tx;
 307
 308 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 309         /*
 310          * EEPROM chips that implement "address overflow" are ones
 311          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 312          * address and the extra bits end up in the "chip address"
 313          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 314          * four 256 byte chips.
 315          *
 316          * Note that we consider the length of the address field to
 317          * still be one byte because the extra address bits are
 318          * hidden in the chip address.
 319          */
 320         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 321         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 322
 323         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 324               addr);
 325 #endif
 326
 327         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 328                 return 1;
 329
 330         start_time_tx = get_timer(0);
 331         while (len) {
 332                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 333                         if (--len == 0) {
 334                                 writel(*buffer | IC_STOP,
 335                                        &i2c_base->ic_cmd_data);
 336                         } else {
 337                                 writel(*buffer, &i2c_base->ic_cmd_data);
 338                         }
 339                         buffer++;
 340                         start_time_tx = get_timer(0);
 341
 342                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 343                                 printf("Timed out. i2c write Failed\n");
 344                                 return 1;
 345                 }
 346         }
 347
 348         return i2c_xfer_finish(i2c_base);
 349 }
 350
 351 /*
 352  * __dw_i2c_init - Init function
 353  * @speed:      required i2c speed
 354  * @slaveaddr:  slave address for the device
 355  *
 356  * Initialization function.
 357  */
 358 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 359 {
 360         int ret;
 361
 362         /* Disable i2c */
 363         ret = dw_i2c_enable(i2c_base, false);
 364         if (ret)
 365                 return ret;
 366
 367         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 368                &i2c_base->ic_con);
 369         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 370         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 371         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 372 #ifndef CONFIG_DM_I2C
 373         __dw_i2c_set_bus_speed(i2c_base, NULL, speed, IC_CLK);
 374         writel(slaveaddr, &i2c_base->ic_sar);
 375 #endif
 376
 377         /* Enable i2c */
 378         ret = dw_i2c_enable(i2c_base, true);
 379         if (ret)
 380                 return ret;
 381
 382         return 0;
 383 }
 384
 385 #ifndef CONFIG_DM_I2C
 386 /*
 387  * The legacy I2C functions. These need to get removed once
 388  * all users of this driver are converted to DM.
 389  */
 390 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 391 {
 392         switch (adap->hwadapnr) {
 393 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 394         case 3:
 395                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 396 #endif
 397 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 398         case 2:
 399                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 400 #endif
 401 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 402         case 1:
 403                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 404 #endif
 405         case 0:
 406                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 407         default:
 408                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 409         }
 410
 411         return NULL;
 412 }
 413
 414 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 415                                          unsigned int speed)
 416 {
 417         adap->speed = speed;
 418         return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed, IC_CLK);
 419 }
 420
 421 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 422 {
 423         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 424 }
 425
 426 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 427                        int alen, u8 *buffer, int len)
 428 {
 429         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 430 }
 431
 432 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 433                         int alen, u8 *buffer, int len)
 434 {
 435         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 436 }
 437
 438 /* dw_i2c_probe - Probe the i2c chip */
 439 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 440 {
 441         struct i2c_regs *i2c_base = i2c_get_base(adap);
 442         u32 tmp;
 443         int ret;
 444
 445         /*
 446          * Try to read the first location of the chip.
 447          */
 448         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 449         if (ret)
 450                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 451
 452         return ret;
 453 }
 454
 455 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 456                          dw_i2c_write, dw_i2c_set_bus_speed,
 457                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 458
 459 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 460 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 461                          dw_i2c_write, dw_i2c_set_bus_speed,
 462                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 463 #endif
 464
 465 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 466 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 467                          dw_i2c_write, dw_i2c_set_bus_speed,
 468                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 469 #endif
 470
 471 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 472 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 473                          dw_i2c_write, dw_i2c_set_bus_speed,
 474                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 475 #endif
 476
 477 #else /* CONFIG_DM_I2C */
 478 /* The DM I2C functions */
 479
 480 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 481                                int nmsgs)
 482 {
 483         struct dw_i2c *i2c = dev_get_priv(bus);
 484         int ret;
 485
 486         debug("i2c_xfer: %d messages\n", nmsgs);
 487         for (; nmsgs > 0; nmsgs--, msg++) {
 488                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 489                 if (msg->flags & I2C_M_RD) {
 490                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 491                                             msg->buf, msg->len);
 492                 } else {
 493                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 494                                              msg->buf, msg->len);
 495                 }
 496                 if (ret) {
 497                         debug("i2c_write: error sending\n");
 498                         return -EREMOTEIO;
 499                 }
 500         }
 501
 502         return 0;
 503 }
 504
 505 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 506 {
 507         struct dw_i2c *i2c = dev_get_priv(bus);
 508         ulong rate;
 509
 510 #if CONFIG_IS_ENABLED(CLK)
 511         rate = clk_get_rate(&i2c->clk);
 512         if (IS_ERR_VALUE(rate))
 513                 return -EINVAL;
 514
 515         /* Convert to MHz */
 516         rate /= 1000000;
 517 #else
 518         rate = IC_CLK;
 519 #endif
 520         return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed,
 521                                       rate);
 522 }
 523
 524 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 525                                      uint chip_flags)
 526 {
 527         struct dw_i2c *i2c = dev_get_priv(bus);
 528         struct i2c_regs *i2c_base = i2c->regs;
 529         u32 tmp;
 530         int ret;
 531
 532         /* Try to read the first location of the chip */
 533         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 534         if (ret)
 535                 __dw_i2c_init(i2c_base, 0, 0);
 536
 537         return ret;
 538 }
 539
 540 static int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 541 {
 542         struct dw_i2c *priv = dev_get_priv(bus);
 543
 544         priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 545
 546         return 0;
 547 }
 548
 549 int designware_i2c_probe(struct udevice *bus)
 550 {
 551         struct dw_i2c *priv = dev_get_priv(bus);
 552         int ret;
 553
 554         ret = reset_get_bulk(bus, &priv->resets);
 555         if (ret)
 556                 dev_warn(bus, "Can't get reset: %d\n", ret);
 557         else
 558                 reset_deassert_bulk(&priv->resets);
 559
 560 #if CONFIG_IS_ENABLED(CLK)
 561         ret = clk_get_by_index(bus, 0, &priv->clk);
 562         if (ret)
 563                 return ret;
 564
 565         ret = clk_enable(&priv->clk);
 566         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 567                 clk_free(&priv->clk);
 568                 dev_err(bus, "failed to enable clock\n");
 569                 return ret;
 570         }
 571 #endif
 572
 573         return __dw_i2c_init(priv->regs, 0, 0);
 574 }
 575
 576 int designware_i2c_remove(struct udevice *dev)
 577 {
 578         struct dw_i2c *priv = dev_get_priv(dev);
 579
 580 #if CONFIG_IS_ENABLED(CLK)
 581         clk_disable(&priv->clk);
 582         clk_free(&priv->clk);
 583 #endif
 584
 585         return reset_release_bulk(&priv->resets);
 586 }
 587
 588 const struct dm_i2c_ops designware_i2c_ops = {
 589         .xfer           = designware_i2c_xfer,
 590         .probe_chip     = designware_i2c_probe_chip,
 591         .set_bus_speed  = designware_i2c_set_bus_speed,
 592 };
 593
 594 static const struct udevice_id designware_i2c_ids[] = {
 595         { .compatible = "snps,designware-i2c" },
 596         { }
 597 };
 598
 599 U_BOOT_DRIVER(i2c_designware) = {
 600         .name   = "i2c_designware",
 601         .id     = UCLASS_I2C,
 602         .of_match = designware_i2c_ids,
 603         .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
 604         .probe  = designware_i2c_probe,
 605         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 606         .remove = designware_i2c_remove,
 607         .flags  = DM_FLAG_OS_PREPARE,
 608         .ops    = &designware_i2c_ops,
 609 };
 610
 611 #endif /* CONFIG_DM_I2C */