1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
13 #include "designware_i2c.h"
15 struct dw_scl_sda_cfg {
24 /* BayTrail HCNT/LCNT/SDA hold time */
25 static struct dw_scl_sda_cfg byt_config = {
35 struct i2c_regs *regs;
36 struct dw_scl_sda_cfg *scl_sda_cfg;
37 struct reset_ctl_bulk resets;
40 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
41 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
43 u32 ena = enable ? IC_ENABLE_0B : 0;
45 writel(ena, &i2c_base->ic_enable);
50 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
52 u32 ena = enable ? IC_ENABLE_0B : 0;
56 writel(ena, &i2c_base->ic_enable);
57 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
61 * Wait 10 times the signaling period of the highest I2C
62 * transfer supported by the driver (for 400KHz this is
63 * 25us) as described in the DesignWare I2C databook.
67 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
74 * i2c_set_bus_speed - Set the i2c speed
75 * @speed: required i2c speed
79 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
80 struct dw_scl_sda_cfg *scl_sda_cfg,
84 unsigned int hcnt, lcnt;
88 if (speed >= I2C_MAX_SPEED)
89 i2c_spd = IC_SPEED_MODE_MAX;
90 else if (speed >= I2C_FAST_SPEED)
91 i2c_spd = IC_SPEED_MODE_FAST;
93 i2c_spd = IC_SPEED_MODE_STANDARD;
95 /* Get enable setting for restore later */
96 ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
98 /* to set speed cltr must be disabled */
99 dw_i2c_enable(i2c_base, false);
101 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
104 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
105 case IC_SPEED_MODE_MAX:
106 cntl |= IC_CON_SPD_SS;
108 hcnt = scl_sda_cfg->fs_hcnt;
109 lcnt = scl_sda_cfg->fs_lcnt;
111 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
112 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
114 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
115 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
119 case IC_SPEED_MODE_STANDARD:
120 cntl |= IC_CON_SPD_SS;
122 hcnt = scl_sda_cfg->ss_hcnt;
123 lcnt = scl_sda_cfg->ss_lcnt;
125 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
126 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
128 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
129 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
132 case IC_SPEED_MODE_FAST:
134 cntl |= IC_CON_SPD_FS;
136 hcnt = scl_sda_cfg->fs_hcnt;
137 lcnt = scl_sda_cfg->fs_lcnt;
139 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
140 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
142 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
143 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
147 writel(cntl, &i2c_base->ic_con);
149 /* Configure SDA Hold Time if required */
151 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
153 /* Restore back i2c now speed set */
154 if (ena == IC_ENABLE_0B)
155 dw_i2c_enable(i2c_base, true);
161 * i2c_setaddress - Sets the target slave address
162 * @i2c_addr: target i2c address
164 * Sets the target slave address.
166 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
169 dw_i2c_enable(i2c_base, false);
171 writel(i2c_addr, &i2c_base->ic_tar);
174 dw_i2c_enable(i2c_base, true);
178 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
180 * Flushes the i2c RX FIFO
182 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
184 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
185 readl(&i2c_base->ic_cmd_data);
189 * i2c_wait_for_bb - Waits for bus busy
193 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
195 unsigned long start_time_bb = get_timer(0);
197 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
198 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
200 /* Evaluate timeout */
201 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
208 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
211 if (i2c_wait_for_bb(i2c_base))
214 i2c_setaddress(i2c_base, chip);
217 /* high byte address going out first */
218 writel((addr >> (alen * 8)) & 0xff,
219 &i2c_base->ic_cmd_data);
224 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
226 ulong start_stop_det = get_timer(0);
229 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
230 readl(&i2c_base->ic_clr_stop_det);
232 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
237 if (i2c_wait_for_bb(i2c_base)) {
238 printf("Timed out waiting for bus\n");
242 i2c_flush_rxfifo(i2c_base);
248 * i2c_read - Read from i2c memory
249 * @chip: target i2c address
250 * @addr: address to read from
252 * @buffer: buffer for read data
253 * @len: no of bytes to be read
255 * Read from i2c memory.
257 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
258 int alen, u8 *buffer, int len)
260 unsigned long start_time_rx;
261 unsigned int active = 0;
263 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
265 * EEPROM chips that implement "address overflow" are ones
266 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
267 * address and the extra bits end up in the "chip address"
268 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
269 * four 256 byte chips.
271 * Note that we consider the length of the address field to
272 * still be one byte because the extra address bits are
273 * hidden in the chip address.
275 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
276 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
278 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
282 if (i2c_xfer_init(i2c_base, dev, addr, alen))
285 start_time_rx = get_timer(0);
289 * Avoid writing to ic_cmd_data multiple times
290 * in case this loop spins too quickly and the
291 * ic_status RFNE bit isn't set after the first
292 * write. Subsequent writes to ic_cmd_data can
293 * trigger spurious i2c transfer.
296 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
298 writel(IC_CMD, &i2c_base->ic_cmd_data);
302 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
303 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
305 start_time_rx = get_timer(0);
307 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
312 return i2c_xfer_finish(i2c_base);
316 * i2c_write - Write to i2c memory
317 * @chip: target i2c address
318 * @addr: address to read from
320 * @buffer: buffer for read data
321 * @len: no of bytes to be read
323 * Write to i2c memory.
325 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
326 int alen, u8 *buffer, int len)
329 unsigned long start_time_tx;
331 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
333 * EEPROM chips that implement "address overflow" are ones
334 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
335 * address and the extra bits end up in the "chip address"
336 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
337 * four 256 byte chips.
339 * Note that we consider the length of the address field to
340 * still be one byte because the extra address bits are
341 * hidden in the chip address.
343 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
344 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
346 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
350 if (i2c_xfer_init(i2c_base, dev, addr, alen))
353 start_time_tx = get_timer(0);
355 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
357 writel(*buffer | IC_STOP,
358 &i2c_base->ic_cmd_data);
360 writel(*buffer, &i2c_base->ic_cmd_data);
363 start_time_tx = get_timer(0);
365 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
366 printf("Timed out. i2c write Failed\n");
371 return i2c_xfer_finish(i2c_base);
375 * __dw_i2c_init - Init function
376 * @speed: required i2c speed
377 * @slaveaddr: slave address for the device
379 * Initialization function.
381 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
386 ret = dw_i2c_enable(i2c_base, false);
390 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
392 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
393 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
394 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
395 #ifndef CONFIG_DM_I2C
396 __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
397 writel(slaveaddr, &i2c_base->ic_sar);
401 ret = dw_i2c_enable(i2c_base, true);
408 #ifndef CONFIG_DM_I2C
410 * The legacy I2C functions. These need to get removed once
411 * all users of this driver are converted to DM.
413 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
415 switch (adap->hwadapnr) {
416 #if CONFIG_SYS_I2C_BUS_MAX >= 4
418 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
420 #if CONFIG_SYS_I2C_BUS_MAX >= 3
422 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
424 #if CONFIG_SYS_I2C_BUS_MAX >= 2
426 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
429 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
431 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
437 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
441 return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
444 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
446 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
449 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
450 int alen, u8 *buffer, int len)
452 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
455 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
456 int alen, u8 *buffer, int len)
458 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
461 /* dw_i2c_probe - Probe the i2c chip */
462 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
464 struct i2c_regs *i2c_base = i2c_get_base(adap);
469 * Try to read the first location of the chip.
471 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
473 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
478 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
479 dw_i2c_write, dw_i2c_set_bus_speed,
480 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
482 #if CONFIG_SYS_I2C_BUS_MAX >= 2
483 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
484 dw_i2c_write, dw_i2c_set_bus_speed,
485 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
488 #if CONFIG_SYS_I2C_BUS_MAX >= 3
489 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
490 dw_i2c_write, dw_i2c_set_bus_speed,
491 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
494 #if CONFIG_SYS_I2C_BUS_MAX >= 4
495 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
496 dw_i2c_write, dw_i2c_set_bus_speed,
497 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
500 #else /* CONFIG_DM_I2C */
501 /* The DM I2C functions */
503 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
506 struct dw_i2c *i2c = dev_get_priv(bus);
509 debug("i2c_xfer: %d messages\n", nmsgs);
510 for (; nmsgs > 0; nmsgs--, msg++) {
511 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
512 if (msg->flags & I2C_M_RD) {
513 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
516 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
520 debug("i2c_write: error sending\n");
528 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
530 struct dw_i2c *i2c = dev_get_priv(bus);
532 return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
535 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
538 struct dw_i2c *i2c = dev_get_priv(bus);
539 struct i2c_regs *i2c_base = i2c->regs;
543 /* Try to read the first location of the chip */
544 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
546 __dw_i2c_init(i2c_base, 0, 0);
551 static int designware_i2c_probe(struct udevice *bus)
553 struct dw_i2c *priv = dev_get_priv(bus);
556 if (device_is_on_pci_bus(bus)) {
558 /* Save base address from PCI BAR */
559 priv->regs = (struct i2c_regs *)
560 dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
562 /* Use BayTrail specific timing values */
563 priv->scl_sda_cfg = &byt_config;
567 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
570 ret = reset_get_bulk(bus, &priv->resets);
572 dev_warn(bus, "Can't get reset: %d\n", ret);
574 reset_deassert_bulk(&priv->resets);
576 return __dw_i2c_init(priv->regs, 0, 0);
579 static int designware_i2c_remove(struct udevice *dev)
581 struct dw_i2c *priv = dev_get_priv(dev);
583 return reset_release_bulk(&priv->resets);
586 static int designware_i2c_bind(struct udevice *dev)
588 static int num_cards;
591 /* Create a unique device name for PCI type devices */
592 if (device_is_on_pci_bus(dev)) {
595 * Setting req_seq in the driver is probably not recommended.
596 * But without a DT alias the number is not configured. And
597 * using this driver is impossible for PCIe I2C devices.
598 * This can be removed, once a better (correct) way for this
599 * is found and implemented.
601 dev->req_seq = num_cards;
602 sprintf(name, "i2c_designware#%u", num_cards++);
603 device_set_name(dev, name);
609 static const struct dm_i2c_ops designware_i2c_ops = {
610 .xfer = designware_i2c_xfer,
611 .probe_chip = designware_i2c_probe_chip,
612 .set_bus_speed = designware_i2c_set_bus_speed,
615 static const struct udevice_id designware_i2c_ids[] = {
616 { .compatible = "snps,designware-i2c" },
620 U_BOOT_DRIVER(i2c_designware) = {
621 .name = "i2c_designware",
623 .of_match = designware_i2c_ids,
624 .bind = designware_i2c_bind,
625 .probe = designware_i2c_probe,
626 .priv_auto_alloc_size = sizeof(struct dw_i2c),
627 .remove = designware_i2c_remove,
628 .flags = DM_FLAG_OS_PREPARE,
629 .ops = &designware_i2c_ops,
633 static struct pci_device_id designware_pci_supported[] = {
634 /* Intel BayTrail has 7 I2C controller located on the PCI bus */
635 { PCI_VDEVICE(INTEL, 0x0f41) },
636 { PCI_VDEVICE(INTEL, 0x0f42) },
637 { PCI_VDEVICE(INTEL, 0x0f43) },
638 { PCI_VDEVICE(INTEL, 0x0f44) },
639 { PCI_VDEVICE(INTEL, 0x0f45) },
640 { PCI_VDEVICE(INTEL, 0x0f46) },
641 { PCI_VDEVICE(INTEL, 0x0f47) },
645 U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
648 #endif /* CONFIG_DM_I2C */