1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
14 #include "designware_i2c.h"
16 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
17 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
19 u32 ena = enable ? IC_ENABLE_0B : 0;
21 writel(ena, &i2c_base->ic_enable);
26 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
28 u32 ena = enable ? IC_ENABLE_0B : 0;
32 writel(ena, &i2c_base->ic_enable);
33 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
37 * Wait 10 times the signaling period of the highest I2C
38 * transfer supported by the driver (for 400KHz this is
39 * 25us) as described in the DesignWare I2C databook.
43 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
50 * i2c_set_bus_speed - Set the i2c speed
51 * @speed: required i2c speed
55 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
56 struct dw_scl_sda_cfg *scl_sda_cfg,
61 unsigned int hcnt, lcnt;
65 /* Allow max speed if there is no config, or the config allows it */
66 if (speed >= I2C_MAX_SPEED &&
67 (!scl_sda_cfg || scl_sda_cfg->has_max_speed))
68 i2c_spd = IC_SPEED_MODE_MAX;
69 else if (speed >= I2C_FAST_SPEED)
70 i2c_spd = IC_SPEED_MODE_FAST;
72 i2c_spd = IC_SPEED_MODE_STANDARD;
74 /* Get enable setting for restore later */
75 ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
77 /* to set speed cltr must be disabled */
78 dw_i2c_enable(i2c_base, false);
80 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
83 case IC_SPEED_MODE_MAX:
84 cntl |= IC_CON_SPD_SS;
86 hcnt = scl_sda_cfg->fs_hcnt;
87 lcnt = scl_sda_cfg->fs_lcnt;
89 hcnt = (bus_mhz * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
90 lcnt = (bus_mhz * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
92 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
93 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
96 case IC_SPEED_MODE_STANDARD:
97 cntl |= IC_CON_SPD_SS;
99 hcnt = scl_sda_cfg->ss_hcnt;
100 lcnt = scl_sda_cfg->ss_lcnt;
102 hcnt = (bus_mhz * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
103 lcnt = (bus_mhz * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
105 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
106 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
109 case IC_SPEED_MODE_FAST:
111 cntl |= IC_CON_SPD_FS;
113 hcnt = scl_sda_cfg->fs_hcnt;
114 lcnt = scl_sda_cfg->fs_lcnt;
116 hcnt = (bus_mhz * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
117 lcnt = (bus_mhz * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
119 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
120 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
124 writel(cntl, &i2c_base->ic_con);
126 /* Configure SDA Hold Time if required */
128 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
130 /* Restore back i2c now speed set */
131 if (ena == IC_ENABLE_0B)
132 dw_i2c_enable(i2c_base, true);
138 * i2c_setaddress - Sets the target slave address
139 * @i2c_addr: target i2c address
141 * Sets the target slave address.
143 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
146 dw_i2c_enable(i2c_base, false);
148 writel(i2c_addr, &i2c_base->ic_tar);
151 dw_i2c_enable(i2c_base, true);
155 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
157 * Flushes the i2c RX FIFO
159 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
161 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
162 readl(&i2c_base->ic_cmd_data);
166 * i2c_wait_for_bb - Waits for bus busy
170 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
172 unsigned long start_time_bb = get_timer(0);
174 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
175 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
177 /* Evaluate timeout */
178 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
185 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
188 if (i2c_wait_for_bb(i2c_base))
191 i2c_setaddress(i2c_base, chip);
194 /* high byte address going out first */
195 writel((addr >> (alen * 8)) & 0xff,
196 &i2c_base->ic_cmd_data);
201 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
203 ulong start_stop_det = get_timer(0);
206 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
207 readl(&i2c_base->ic_clr_stop_det);
209 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
214 if (i2c_wait_for_bb(i2c_base)) {
215 printf("Timed out waiting for bus\n");
219 i2c_flush_rxfifo(i2c_base);
225 * i2c_read - Read from i2c memory
226 * @chip: target i2c address
227 * @addr: address to read from
229 * @buffer: buffer for read data
230 * @len: no of bytes to be read
232 * Read from i2c memory.
234 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
235 int alen, u8 *buffer, int len)
237 unsigned long start_time_rx;
238 unsigned int active = 0;
240 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
242 * EEPROM chips that implement "address overflow" are ones
243 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
244 * address and the extra bits end up in the "chip address"
245 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
246 * four 256 byte chips.
248 * Note that we consider the length of the address field to
249 * still be one byte because the extra address bits are
250 * hidden in the chip address.
252 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
253 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
255 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
259 if (i2c_xfer_init(i2c_base, dev, addr, alen))
262 start_time_rx = get_timer(0);
266 * Avoid writing to ic_cmd_data multiple times
267 * in case this loop spins too quickly and the
268 * ic_status RFNE bit isn't set after the first
269 * write. Subsequent writes to ic_cmd_data can
270 * trigger spurious i2c transfer.
273 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
275 writel(IC_CMD, &i2c_base->ic_cmd_data);
279 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
280 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
282 start_time_rx = get_timer(0);
284 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
289 return i2c_xfer_finish(i2c_base);
293 * i2c_write - Write to i2c memory
294 * @chip: target i2c address
295 * @addr: address to read from
297 * @buffer: buffer for read data
298 * @len: no of bytes to be read
300 * Write to i2c memory.
302 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
303 int alen, u8 *buffer, int len)
306 unsigned long start_time_tx;
308 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
310 * EEPROM chips that implement "address overflow" are ones
311 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
312 * address and the extra bits end up in the "chip address"
313 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
314 * four 256 byte chips.
316 * Note that we consider the length of the address field to
317 * still be one byte because the extra address bits are
318 * hidden in the chip address.
320 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
321 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
323 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
327 if (i2c_xfer_init(i2c_base, dev, addr, alen))
330 start_time_tx = get_timer(0);
332 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
334 writel(*buffer | IC_STOP,
335 &i2c_base->ic_cmd_data);
337 writel(*buffer, &i2c_base->ic_cmd_data);
340 start_time_tx = get_timer(0);
342 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
343 printf("Timed out. i2c write Failed\n");
348 return i2c_xfer_finish(i2c_base);
352 * __dw_i2c_init - Init function
353 * @speed: required i2c speed
354 * @slaveaddr: slave address for the device
356 * Initialization function.
358 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
363 ret = dw_i2c_enable(i2c_base, false);
367 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
369 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
370 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
371 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
372 #ifndef CONFIG_DM_I2C
373 __dw_i2c_set_bus_speed(i2c_base, NULL, speed, IC_CLK);
374 writel(slaveaddr, &i2c_base->ic_sar);
378 ret = dw_i2c_enable(i2c_base, true);
385 #ifndef CONFIG_DM_I2C
387 * The legacy I2C functions. These need to get removed once
388 * all users of this driver are converted to DM.
390 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
392 switch (adap->hwadapnr) {
393 #if CONFIG_SYS_I2C_BUS_MAX >= 4
395 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
397 #if CONFIG_SYS_I2C_BUS_MAX >= 3
399 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
401 #if CONFIG_SYS_I2C_BUS_MAX >= 2
403 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
406 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
408 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
414 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
418 return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed, IC_CLK);
421 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
423 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
426 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
427 int alen, u8 *buffer, int len)
429 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
432 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
433 int alen, u8 *buffer, int len)
435 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
438 /* dw_i2c_probe - Probe the i2c chip */
439 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
441 struct i2c_regs *i2c_base = i2c_get_base(adap);
446 * Try to read the first location of the chip.
448 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
450 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
455 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
456 dw_i2c_write, dw_i2c_set_bus_speed,
457 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
459 #if CONFIG_SYS_I2C_BUS_MAX >= 2
460 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
461 dw_i2c_write, dw_i2c_set_bus_speed,
462 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
465 #if CONFIG_SYS_I2C_BUS_MAX >= 3
466 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
467 dw_i2c_write, dw_i2c_set_bus_speed,
468 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
471 #if CONFIG_SYS_I2C_BUS_MAX >= 4
472 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
473 dw_i2c_write, dw_i2c_set_bus_speed,
474 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
477 #else /* CONFIG_DM_I2C */
478 /* The DM I2C functions */
480 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
483 struct dw_i2c *i2c = dev_get_priv(bus);
486 debug("i2c_xfer: %d messages\n", nmsgs);
487 for (; nmsgs > 0; nmsgs--, msg++) {
488 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
489 if (msg->flags & I2C_M_RD) {
490 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
493 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
497 debug("i2c_write: error sending\n");
505 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
507 struct dw_i2c *i2c = dev_get_priv(bus);
510 #if CONFIG_IS_ENABLED(CLK)
511 rate = clk_get_rate(&i2c->clk);
512 if (IS_ERR_VALUE(rate))
520 return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed,
524 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
527 struct dw_i2c *i2c = dev_get_priv(bus);
528 struct i2c_regs *i2c_base = i2c->regs;
532 /* Try to read the first location of the chip */
533 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
535 __dw_i2c_init(i2c_base, 0, 0);
540 static int designware_i2c_ofdata_to_platdata(struct udevice *bus)
542 struct dw_i2c *priv = dev_get_priv(bus);
544 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
549 int designware_i2c_probe(struct udevice *bus)
551 struct dw_i2c *priv = dev_get_priv(bus);
554 ret = reset_get_bulk(bus, &priv->resets);
556 dev_warn(bus, "Can't get reset: %d\n", ret);
558 reset_deassert_bulk(&priv->resets);
560 #if CONFIG_IS_ENABLED(CLK)
561 ret = clk_get_by_index(bus, 0, &priv->clk);
565 ret = clk_enable(&priv->clk);
566 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
567 clk_free(&priv->clk);
568 dev_err(bus, "failed to enable clock\n");
573 return __dw_i2c_init(priv->regs, 0, 0);
576 int designware_i2c_remove(struct udevice *dev)
578 struct dw_i2c *priv = dev_get_priv(dev);
580 #if CONFIG_IS_ENABLED(CLK)
581 clk_disable(&priv->clk);
582 clk_free(&priv->clk);
585 return reset_release_bulk(&priv->resets);
588 const struct dm_i2c_ops designware_i2c_ops = {
589 .xfer = designware_i2c_xfer,
590 .probe_chip = designware_i2c_probe_chip,
591 .set_bus_speed = designware_i2c_set_bus_speed,
594 static const struct udevice_id designware_i2c_ids[] = {
595 { .compatible = "snps,designware-i2c" },
599 U_BOOT_DRIVER(i2c_designware) = {
600 .name = "i2c_designware",
602 .of_match = designware_i2c_ids,
603 .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
604 .probe = designware_i2c_probe,
605 .priv_auto_alloc_size = sizeof(struct dw_i2c),
606 .remove = designware_i2c_remove,
607 .flags = DM_FLAG_OS_PREPARE,
608 .ops = &designware_i2c_ops,
611 #endif /* CONFIG_DM_I2C */