drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <clk.h>
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <pci.h>
  12 #include <reset.h>
  13 #include <asm/io.h>
  14 #include "designware_i2c.h"
  15
  16 struct dw_scl_sda_cfg {
  17         u32 ss_hcnt;
  18         u32 fs_hcnt;
  19         u32 ss_lcnt;
  20         u32 fs_lcnt;
  21         u32 sda_hold;
  22 };
  23
  24 #ifdef CONFIG_X86
  25 /* BayTrail HCNT/LCNT/SDA hold time */
  26 static struct dw_scl_sda_cfg byt_config = {
  27         .ss_hcnt = 0x200,
  28         .fs_hcnt = 0x55,
  29         .ss_lcnt = 0x200,
  30         .fs_lcnt = 0x99,
  31         .sda_hold = 0x6,
  32 };
  33 #endif
  34
  35 struct dw_i2c {
  36         struct i2c_regs *regs;
  37         struct dw_scl_sda_cfg *scl_sda_cfg;
  38         struct reset_ctl_bulk resets;
  39 #if CONFIG_IS_ENABLED(CLK)
  40         struct clk clk;
  41 #endif
  42 };
  43
  44 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  45 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  46 {
  47         u32 ena = enable ? IC_ENABLE_0B : 0;
  48
  49         writel(ena, &i2c_base->ic_enable);
  50
  51         return 0;
  52 }
  53 #else
  54 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  55 {
  56         u32 ena = enable ? IC_ENABLE_0B : 0;
  57         int timeout = 100;
  58
  59         do {
  60                 writel(ena, &i2c_base->ic_enable);
  61                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  62                         return 0;
  63
  64                 /*
  65                  * Wait 10 times the signaling period of the highest I2C
  66                  * transfer supported by the driver (for 400KHz this is
  67                  * 25us) as described in the DesignWare I2C databook.
  68                  */
  69                 udelay(25);
  70         } while (timeout--);
  71         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  72
  73         return -ETIMEDOUT;
  74 }
  75 #endif
  76
  77 /*
  78  * i2c_set_bus_speed - Set the i2c speed
  79  * @speed:      required i2c speed
  80  *
  81  * Set the i2c speed.
  82  */
  83 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
  84                                            struct dw_scl_sda_cfg *scl_sda_cfg,
  85                                            unsigned int speed,
  86                                            unsigned int bus_mhz)
  87 {
  88         unsigned int cntl;
  89         unsigned int hcnt, lcnt;
  90         unsigned int ena;
  91         int i2c_spd;
  92
  93         if (speed >= I2C_MAX_SPEED)
  94                 i2c_spd = IC_SPEED_MODE_MAX;
  95         else if (speed >= I2C_FAST_SPEED)
  96                 i2c_spd = IC_SPEED_MODE_FAST;
  97         else
  98                 i2c_spd = IC_SPEED_MODE_STANDARD;
  99
 100         /* Get enable setting for restore later */
 101         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
 102
 103         /* to set speed cltr must be disabled */
 104         dw_i2c_enable(i2c_base, false);
 105
 106         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 107
 108         switch (i2c_spd) {
 109 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
 110         case IC_SPEED_MODE_MAX:
 111                 cntl |= IC_CON_SPD_SS;
 112                 if (scl_sda_cfg) {
 113                         hcnt = scl_sda_cfg->fs_hcnt;
 114                         lcnt = scl_sda_cfg->fs_lcnt;
 115                 } else {
 116                         hcnt = (bus_mhz * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
 117                         lcnt = (bus_mhz * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
 118                 }
 119                 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
 120                 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
 121                 break;
 122 #endif
 123
 124         case IC_SPEED_MODE_STANDARD:
 125                 cntl |= IC_CON_SPD_SS;
 126                 if (scl_sda_cfg) {
 127                         hcnt = scl_sda_cfg->ss_hcnt;
 128                         lcnt = scl_sda_cfg->ss_lcnt;
 129                 } else {
 130                         hcnt = (bus_mhz * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
 131                         lcnt = (bus_mhz * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
 132                 }
 133                 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
 134                 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
 135                 break;
 136
 137         case IC_SPEED_MODE_FAST:
 138         default:
 139                 cntl |= IC_CON_SPD_FS;
 140                 if (scl_sda_cfg) {
 141                         hcnt = scl_sda_cfg->fs_hcnt;
 142                         lcnt = scl_sda_cfg->fs_lcnt;
 143                 } else {
 144                         hcnt = (bus_mhz * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
 145                         lcnt = (bus_mhz * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
 146                 }
 147                 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
 148                 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
 149                 break;
 150         }
 151
 152         writel(cntl, &i2c_base->ic_con);
 153
 154         /* Configure SDA Hold Time if required */
 155         if (scl_sda_cfg)
 156                 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
 157
 158         /* Restore back i2c now speed set */
 159         if (ena == IC_ENABLE_0B)
 160                 dw_i2c_enable(i2c_base, true);
 161
 162         return 0;
 163 }
 164
 165 /*
 166  * i2c_setaddress - Sets the target slave address
 167  * @i2c_addr:   target i2c address
 168  *
 169  * Sets the target slave address.
 170  */
 171 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 172 {
 173         /* Disable i2c */
 174         dw_i2c_enable(i2c_base, false);
 175
 176         writel(i2c_addr, &i2c_base->ic_tar);
 177
 178         /* Enable i2c */
 179         dw_i2c_enable(i2c_base, true);
 180 }
 181
 182 /*
 183  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 184  *
 185  * Flushes the i2c RX FIFO
 186  */
 187 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 188 {
 189         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 190                 readl(&i2c_base->ic_cmd_data);
 191 }
 192
 193 /*
 194  * i2c_wait_for_bb - Waits for bus busy
 195  *
 196  * Waits for bus busy
 197  */
 198 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 199 {
 200         unsigned long start_time_bb = get_timer(0);
 201
 202         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 203                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 204
 205                 /* Evaluate timeout */
 206                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 207                         return 1;
 208         }
 209
 210         return 0;
 211 }
 212
 213 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 214                          int alen)
 215 {
 216         if (i2c_wait_for_bb(i2c_base))
 217                 return 1;
 218
 219         i2c_setaddress(i2c_base, chip);
 220         while (alen) {
 221                 alen--;
 222                 /* high byte address going out first */
 223                 writel((addr >> (alen * 8)) & 0xff,
 224                        &i2c_base->ic_cmd_data);
 225         }
 226         return 0;
 227 }
 228
 229 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 230 {
 231         ulong start_stop_det = get_timer(0);
 232
 233         while (1) {
 234                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 235                         readl(&i2c_base->ic_clr_stop_det);
 236                         break;
 237                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 238                         break;
 239                 }
 240         }
 241
 242         if (i2c_wait_for_bb(i2c_base)) {
 243                 printf("Timed out waiting for bus\n");
 244                 return 1;
 245         }
 246
 247         i2c_flush_rxfifo(i2c_base);
 248
 249         return 0;
 250 }
 251
 252 /*
 253  * i2c_read - Read from i2c memory
 254  * @chip:       target i2c address
 255  * @addr:       address to read from
 256  * @alen:
 257  * @buffer:     buffer for read data
 258  * @len:        no of bytes to be read
 259  *
 260  * Read from i2c memory.
 261  */
 262 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 263                          int alen, u8 *buffer, int len)
 264 {
 265         unsigned long start_time_rx;
 266         unsigned int active = 0;
 267
 268 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 269         /*
 270          * EEPROM chips that implement "address overflow" are ones
 271          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 272          * address and the extra bits end up in the "chip address"
 273          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 274          * four 256 byte chips.
 275          *
 276          * Note that we consider the length of the address field to
 277          * still be one byte because the extra address bits are
 278          * hidden in the chip address.
 279          */
 280         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 281         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 282
 283         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 284               addr);
 285 #endif
 286
 287         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 288                 return 1;
 289
 290         start_time_rx = get_timer(0);
 291         while (len) {
 292                 if (!active) {
 293                         /*
 294                          * Avoid writing to ic_cmd_data multiple times
 295                          * in case this loop spins too quickly and the
 296                          * ic_status RFNE bit isn't set after the first
 297                          * write. Subsequent writes to ic_cmd_data can
 298                          * trigger spurious i2c transfer.
 299                          */
 300                         if (len == 1)
 301                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 302                         else
 303                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 304                         active = 1;
 305                 }
 306
 307                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 308                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 309                         len--;
 310                         start_time_rx = get_timer(0);
 311                         active = 0;
 312                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 313                         return 1;
 314                 }
 315         }
 316
 317         return i2c_xfer_finish(i2c_base);
 318 }
 319
 320 /*
 321  * i2c_write - Write to i2c memory
 322  * @chip:       target i2c address
 323  * @addr:       address to read from
 324  * @alen:
 325  * @buffer:     buffer for read data
 326  * @len:        no of bytes to be read
 327  *
 328  * Write to i2c memory.
 329  */
 330 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 331                           int alen, u8 *buffer, int len)
 332 {
 333         int nb = len;
 334         unsigned long start_time_tx;
 335
 336 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 337         /*
 338          * EEPROM chips that implement "address overflow" are ones
 339          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 340          * address and the extra bits end up in the "chip address"
 341          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 342          * four 256 byte chips.
 343          *
 344          * Note that we consider the length of the address field to
 345          * still be one byte because the extra address bits are
 346          * hidden in the chip address.
 347          */
 348         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 349         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 350
 351         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 352               addr);
 353 #endif
 354
 355         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 356                 return 1;
 357
 358         start_time_tx = get_timer(0);
 359         while (len) {
 360                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 361                         if (--len == 0) {
 362                                 writel(*buffer | IC_STOP,
 363                                        &i2c_base->ic_cmd_data);
 364                         } else {
 365                                 writel(*buffer, &i2c_base->ic_cmd_data);
 366                         }
 367                         buffer++;
 368                         start_time_tx = get_timer(0);
 369
 370                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 371                                 printf("Timed out. i2c write Failed\n");
 372                                 return 1;
 373                 }
 374         }
 375
 376         return i2c_xfer_finish(i2c_base);
 377 }
 378
 379 /*
 380  * __dw_i2c_init - Init function
 381  * @speed:      required i2c speed
 382  * @slaveaddr:  slave address for the device
 383  *
 384  * Initialization function.
 385  */
 386 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 387 {
 388         int ret;
 389
 390         /* Disable i2c */
 391         ret = dw_i2c_enable(i2c_base, false);
 392         if (ret)
 393                 return ret;
 394
 395         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 396                &i2c_base->ic_con);
 397         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 398         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 399         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 400 #ifndef CONFIG_DM_I2C
 401         __dw_i2c_set_bus_speed(i2c_base, NULL, speed, IC_CLK);
 402         writel(slaveaddr, &i2c_base->ic_sar);
 403 #endif
 404
 405         /* Enable i2c */
 406         ret = dw_i2c_enable(i2c_base, true);
 407         if (ret)
 408                 return ret;
 409
 410         return 0;
 411 }
 412
 413 #ifndef CONFIG_DM_I2C
 414 /*
 415  * The legacy I2C functions. These need to get removed once
 416  * all users of this driver are converted to DM.
 417  */
 418 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 419 {
 420         switch (adap->hwadapnr) {
 421 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 422         case 3:
 423                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 424 #endif
 425 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 426         case 2:
 427                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 428 #endif
 429 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 430         case 1:
 431                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 432 #endif
 433         case 0:
 434                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 435         default:
 436                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 437         }
 438
 439         return NULL;
 440 }
 441
 442 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 443                                          unsigned int speed)
 444 {
 445         adap->speed = speed;
 446         return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed, IC_CLK);
 447 }
 448
 449 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 450 {
 451         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 452 }
 453
 454 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 455                        int alen, u8 *buffer, int len)
 456 {
 457         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 458 }
 459
 460 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 461                         int alen, u8 *buffer, int len)
 462 {
 463         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 464 }
 465
 466 /* dw_i2c_probe - Probe the i2c chip */
 467 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 468 {
 469         struct i2c_regs *i2c_base = i2c_get_base(adap);
 470         u32 tmp;
 471         int ret;
 472
 473         /*
 474          * Try to read the first location of the chip.
 475          */
 476         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 477         if (ret)
 478                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 479
 480         return ret;
 481 }
 482
 483 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 484                          dw_i2c_write, dw_i2c_set_bus_speed,
 485                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 486
 487 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 488 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 489                          dw_i2c_write, dw_i2c_set_bus_speed,
 490                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 491 #endif
 492
 493 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 494 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 495                          dw_i2c_write, dw_i2c_set_bus_speed,
 496                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 497 #endif
 498
 499 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 500 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 501                          dw_i2c_write, dw_i2c_set_bus_speed,
 502                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 503 #endif
 504
 505 #else /* CONFIG_DM_I2C */
 506 /* The DM I2C functions */
 507
 508 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 509                                int nmsgs)
 510 {
 511         struct dw_i2c *i2c = dev_get_priv(bus);
 512         int ret;
 513
 514         debug("i2c_xfer: %d messages\n", nmsgs);
 515         for (; nmsgs > 0; nmsgs--, msg++) {
 516                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 517                 if (msg->flags & I2C_M_RD) {
 518                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 519                                             msg->buf, msg->len);
 520                 } else {
 521                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 522                                              msg->buf, msg->len);
 523                 }
 524                 if (ret) {
 525                         debug("i2c_write: error sending\n");
 526                         return -EREMOTEIO;
 527                 }
 528         }
 529
 530         return 0;
 531 }
 532
 533 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 534 {
 535         struct dw_i2c *i2c = dev_get_priv(bus);
 536         ulong rate;
 537
 538 #if CONFIG_IS_ENABLED(CLK)
 539         rate = clk_get_rate(&i2c->clk);
 540         if (IS_ERR_VALUE(rate))
 541                 return -EINVAL;
 542
 543         /* Convert to MHz */
 544         rate /= 1000000;
 545 #else
 546         rate = IC_CLK;
 547 #endif
 548         return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed,
 549                                       rate);
 550 }
 551
 552 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 553                                      uint chip_flags)
 554 {
 555         struct dw_i2c *i2c = dev_get_priv(bus);
 556         struct i2c_regs *i2c_base = i2c->regs;
 557         u32 tmp;
 558         int ret;
 559
 560         /* Try to read the first location of the chip */
 561         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 562         if (ret)
 563                 __dw_i2c_init(i2c_base, 0, 0);
 564
 565         return ret;
 566 }
 567
 568 static int designware_i2c_probe(struct udevice *bus)
 569 {
 570         struct dw_i2c *priv = dev_get_priv(bus);
 571         int ret;
 572
 573         if (device_is_on_pci_bus(bus)) {
 574 #ifdef CONFIG_DM_PCI
 575                 /* Save base address from PCI BAR */
 576                 priv->regs = (struct i2c_regs *)
 577                         dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 578 #ifdef CONFIG_X86
 579                 /* Use BayTrail specific timing values */
 580                 priv->scl_sda_cfg = &byt_config;
 581 #endif
 582 #endif
 583         } else {
 584                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 585         }
 586
 587         ret = reset_get_bulk(bus, &priv->resets);
 588         if (ret)
 589                 dev_warn(bus, "Can't get reset: %d\n", ret);
 590         else
 591                 reset_deassert_bulk(&priv->resets);
 592
 593 #if CONFIG_IS_ENABLED(CLK)
 594         ret = clk_get_by_index(bus, 0, &priv->clk);
 595         if (ret)
 596                 return ret;
 597
 598         ret = clk_enable(&priv->clk);
 599         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 600                 clk_free(&priv->clk);
 601                 dev_err(bus, "failed to enable clock\n");
 602                 return ret;
 603         }
 604 #endif
 605
 606         return __dw_i2c_init(priv->regs, 0, 0);
 607 }
 608
 609 static int designware_i2c_remove(struct udevice *dev)
 610 {
 611         struct dw_i2c *priv = dev_get_priv(dev);
 612
 613 #if CONFIG_IS_ENABLED(CLK)
 614         clk_disable(&priv->clk);
 615         clk_free(&priv->clk);
 616 #endif
 617
 618         return reset_release_bulk(&priv->resets);
 619 }
 620
 621 static int designware_i2c_bind(struct udevice *dev)
 622 {
 623         static int num_cards;
 624         char name[20];
 625
 626         /* Create a unique device name for PCI type devices */
 627         if (device_is_on_pci_bus(dev)) {
 628                 /*
 629                  * ToDo:
 630                  * Setting req_seq in the driver is probably not recommended.
 631                  * But without a DT alias the number is not configured. And
 632                  * using this driver is impossible for PCIe I2C devices.
 633                  * This can be removed, once a better (correct) way for this
 634                  * is found and implemented.
 635                  */
 636                 dev->req_seq = num_cards;
 637                 sprintf(name, "i2c_designware#%u", num_cards++);
 638                 device_set_name(dev, name);
 639         }
 640
 641         return 0;
 642 }
 643
 644 static const struct dm_i2c_ops designware_i2c_ops = {
 645         .xfer           = designware_i2c_xfer,
 646         .probe_chip     = designware_i2c_probe_chip,
 647         .set_bus_speed  = designware_i2c_set_bus_speed,
 648 };
 649
 650 static const struct udevice_id designware_i2c_ids[] = {
 651         { .compatible = "snps,designware-i2c" },
 652         { }
 653 };
 654
 655 U_BOOT_DRIVER(i2c_designware) = {
 656         .name   = "i2c_designware",
 657         .id     = UCLASS_I2C,
 658         .of_match = designware_i2c_ids,
 659         .bind   = designware_i2c_bind,
 660         .probe  = designware_i2c_probe,
 661         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 662         .remove = designware_i2c_remove,
 663         .flags = DM_FLAG_OS_PREPARE,
 664         .ops    = &designware_i2c_ops,
 665 };
 666
 667 #ifdef CONFIG_X86
 668 static struct pci_device_id designware_pci_supported[] = {
 669         /* Intel BayTrail has 7 I2C controller located on the PCI bus */
 670         { PCI_VDEVICE(INTEL, 0x0f41) },
 671         { PCI_VDEVICE(INTEL, 0x0f42) },
 672         { PCI_VDEVICE(INTEL, 0x0f43) },
 673         { PCI_VDEVICE(INTEL, 0x0f44) },
 674         { PCI_VDEVICE(INTEL, 0x0f45) },
 675         { PCI_VDEVICE(INTEL, 0x0f46) },
 676         { PCI_VDEVICE(INTEL, 0x0f47) },
 677         {},
 678 };
 679
 680 U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
 681 #endif
 682
 683 #endif /* CONFIG_DM_I2C */