drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <i2c.h>
  10 #include <pci.h>
  11 #include <reset.h>
  12 #include <asm/io.h>
  13 #include "designware_i2c.h"
  14
  15 struct dw_scl_sda_cfg {
  16         u32 ss_hcnt;
  17         u32 fs_hcnt;
  18         u32 ss_lcnt;
  19         u32 fs_lcnt;
  20         u32 sda_hold;
  21 };
  22
  23 #ifdef CONFIG_X86
  24 /* BayTrail HCNT/LCNT/SDA hold time */
  25 static struct dw_scl_sda_cfg byt_config = {
  26         .ss_hcnt = 0x200,
  27         .fs_hcnt = 0x55,
  28         .ss_lcnt = 0x200,
  29         .fs_lcnt = 0x99,
  30         .sda_hold = 0x6,
  31 };
  32 #endif
  33
  34 struct dw_i2c {
  35         struct i2c_regs *regs;
  36         struct dw_scl_sda_cfg *scl_sda_cfg;
  37         struct reset_ctl reset_ctl;
  38 };
  39
  40 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  41 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  42 {
  43         u32 ena = enable ? IC_ENABLE_0B : 0;
  44
  45         writel(ena, &i2c_base->ic_enable);
  46
  47         return 0;
  48 }
  49 #else
  50 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  51 {
  52         u32 ena = enable ? IC_ENABLE_0B : 0;
  53         int timeout = 100;
  54
  55         do {
  56                 writel(ena, &i2c_base->ic_enable);
  57                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  58                         return 0;
  59
  60                 /*
  61                  * Wait 10 times the signaling period of the highest I2C
  62                  * transfer supported by the driver (for 400KHz this is
  63                  * 25us) as described in the DesignWare I2C databook.
  64                  */
  65                 udelay(25);
  66         } while (timeout--);
  67         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  68
  69         return -ETIMEDOUT;
  70 }
  71 #endif
  72
  73 /*
  74  * i2c_set_bus_speed - Set the i2c speed
  75  * @speed:      required i2c speed
  76  *
  77  * Set the i2c speed.
  78  */
  79 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
  80                                            struct dw_scl_sda_cfg *scl_sda_cfg,
  81                                            unsigned int speed)
  82 {
  83         unsigned int cntl;
  84         unsigned int hcnt, lcnt;
  85         int i2c_spd;
  86
  87         if (speed >= I2C_MAX_SPEED)
  88                 i2c_spd = IC_SPEED_MODE_MAX;
  89         else if (speed >= I2C_FAST_SPEED)
  90                 i2c_spd = IC_SPEED_MODE_FAST;
  91         else
  92                 i2c_spd = IC_SPEED_MODE_STANDARD;
  93
  94         /* to set speed cltr must be disabled */
  95         dw_i2c_enable(i2c_base, false);
  96
  97         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
  98
  99         switch (i2c_spd) {
 100 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
 101         case IC_SPEED_MODE_MAX:
 102                 cntl |= IC_CON_SPD_SS;
 103                 if (scl_sda_cfg) {
 104                         hcnt = scl_sda_cfg->fs_hcnt;
 105                         lcnt = scl_sda_cfg->fs_lcnt;
 106                 } else {
 107                         hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
 108                         lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
 109                 }
 110                 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
 111                 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
 112                 break;
 113 #endif
 114
 115         case IC_SPEED_MODE_STANDARD:
 116                 cntl |= IC_CON_SPD_SS;
 117                 if (scl_sda_cfg) {
 118                         hcnt = scl_sda_cfg->ss_hcnt;
 119                         lcnt = scl_sda_cfg->ss_lcnt;
 120                 } else {
 121                         hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
 122                         lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
 123                 }
 124                 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
 125                 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
 126                 break;
 127
 128         case IC_SPEED_MODE_FAST:
 129         default:
 130                 cntl |= IC_CON_SPD_FS;
 131                 if (scl_sda_cfg) {
 132                         hcnt = scl_sda_cfg->fs_hcnt;
 133                         lcnt = scl_sda_cfg->fs_lcnt;
 134                 } else {
 135                         hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
 136                         lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
 137                 }
 138                 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
 139                 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
 140                 break;
 141         }
 142
 143         writel(cntl, &i2c_base->ic_con);
 144
 145         /* Configure SDA Hold Time if required */
 146         if (scl_sda_cfg)
 147                 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
 148
 149         /* Enable back i2c now speed set */
 150         dw_i2c_enable(i2c_base, true);
 151
 152         return 0;
 153 }
 154
 155 /*
 156  * i2c_setaddress - Sets the target slave address
 157  * @i2c_addr:   target i2c address
 158  *
 159  * Sets the target slave address.
 160  */
 161 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 162 {
 163         /* Disable i2c */
 164         dw_i2c_enable(i2c_base, false);
 165
 166         writel(i2c_addr, &i2c_base->ic_tar);
 167
 168         /* Enable i2c */
 169         dw_i2c_enable(i2c_base, true);
 170 }
 171
 172 /*
 173  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 174  *
 175  * Flushes the i2c RX FIFO
 176  */
 177 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 178 {
 179         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 180                 readl(&i2c_base->ic_cmd_data);
 181 }
 182
 183 /*
 184  * i2c_wait_for_bb - Waits for bus busy
 185  *
 186  * Waits for bus busy
 187  */
 188 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 189 {
 190         unsigned long start_time_bb = get_timer(0);
 191
 192         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 193                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 194
 195                 /* Evaluate timeout */
 196                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 197                         return 1;
 198         }
 199
 200         return 0;
 201 }
 202
 203 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 204                          int alen)
 205 {
 206         if (i2c_wait_for_bb(i2c_base))
 207                 return 1;
 208
 209         i2c_setaddress(i2c_base, chip);
 210         while (alen) {
 211                 alen--;
 212                 /* high byte address going out first */
 213                 writel((addr >> (alen * 8)) & 0xff,
 214                        &i2c_base->ic_cmd_data);
 215         }
 216         return 0;
 217 }
 218
 219 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 220 {
 221         ulong start_stop_det = get_timer(0);
 222
 223         while (1) {
 224                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 225                         readl(&i2c_base->ic_clr_stop_det);
 226                         break;
 227                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 228                         break;
 229                 }
 230         }
 231
 232         if (i2c_wait_for_bb(i2c_base)) {
 233                 printf("Timed out waiting for bus\n");
 234                 return 1;
 235         }
 236
 237         i2c_flush_rxfifo(i2c_base);
 238
 239         return 0;
 240 }
 241
 242 /*
 243  * i2c_read - Read from i2c memory
 244  * @chip:       target i2c address
 245  * @addr:       address to read from
 246  * @alen:
 247  * @buffer:     buffer for read data
 248  * @len:        no of bytes to be read
 249  *
 250  * Read from i2c memory.
 251  */
 252 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 253                          int alen, u8 *buffer, int len)
 254 {
 255         unsigned long start_time_rx;
 256         unsigned int active = 0;
 257
 258 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 259         /*
 260          * EEPROM chips that implement "address overflow" are ones
 261          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 262          * address and the extra bits end up in the "chip address"
 263          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 264          * four 256 byte chips.
 265          *
 266          * Note that we consider the length of the address field to
 267          * still be one byte because the extra address bits are
 268          * hidden in the chip address.
 269          */
 270         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 271         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 272
 273         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 274               addr);
 275 #endif
 276
 277         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 278                 return 1;
 279
 280         start_time_rx = get_timer(0);
 281         while (len) {
 282                 if (!active) {
 283                         /*
 284                          * Avoid writing to ic_cmd_data multiple times
 285                          * in case this loop spins too quickly and the
 286                          * ic_status RFNE bit isn't set after the first
 287                          * write. Subsequent writes to ic_cmd_data can
 288                          * trigger spurious i2c transfer.
 289                          */
 290                         if (len == 1)
 291                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 292                         else
 293                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 294                         active = 1;
 295                 }
 296
 297                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 298                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 299                         len--;
 300                         start_time_rx = get_timer(0);
 301                         active = 0;
 302                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 303                         return 1;
 304                 }
 305         }
 306
 307         return i2c_xfer_finish(i2c_base);
 308 }
 309
 310 /*
 311  * i2c_write - Write to i2c memory
 312  * @chip:       target i2c address
 313  * @addr:       address to read from
 314  * @alen:
 315  * @buffer:     buffer for read data
 316  * @len:        no of bytes to be read
 317  *
 318  * Write to i2c memory.
 319  */
 320 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 321                           int alen, u8 *buffer, int len)
 322 {
 323         int nb = len;
 324         unsigned long start_time_tx;
 325
 326 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 327         /*
 328          * EEPROM chips that implement "address overflow" are ones
 329          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 330          * address and the extra bits end up in the "chip address"
 331          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 332          * four 256 byte chips.
 333          *
 334          * Note that we consider the length of the address field to
 335          * still be one byte because the extra address bits are
 336          * hidden in the chip address.
 337          */
 338         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 339         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 340
 341         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 342               addr);
 343 #endif
 344
 345         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 346                 return 1;
 347
 348         start_time_tx = get_timer(0);
 349         while (len) {
 350                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 351                         if (--len == 0) {
 352                                 writel(*buffer | IC_STOP,
 353                                        &i2c_base->ic_cmd_data);
 354                         } else {
 355                                 writel(*buffer, &i2c_base->ic_cmd_data);
 356                         }
 357                         buffer++;
 358                         start_time_tx = get_timer(0);
 359
 360                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 361                                 printf("Timed out. i2c write Failed\n");
 362                                 return 1;
 363                 }
 364         }
 365
 366         return i2c_xfer_finish(i2c_base);
 367 }
 368
 369 /*
 370  * __dw_i2c_init - Init function
 371  * @speed:      required i2c speed
 372  * @slaveaddr:  slave address for the device
 373  *
 374  * Initialization function.
 375  */
 376 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 377 {
 378         int ret;
 379
 380         /* Disable i2c */
 381         ret = dw_i2c_enable(i2c_base, false);
 382         if (ret)
 383                 return ret;
 384
 385         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 386                &i2c_base->ic_con);
 387         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 388         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 389         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 390 #ifndef CONFIG_DM_I2C
 391         __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
 392         writel(slaveaddr, &i2c_base->ic_sar);
 393 #endif
 394
 395         /* Enable i2c */
 396         ret = dw_i2c_enable(i2c_base, true);
 397         if (ret)
 398                 return ret;
 399
 400         return 0;
 401 }
 402
 403 #ifndef CONFIG_DM_I2C
 404 /*
 405  * The legacy I2C functions. These need to get removed once
 406  * all users of this driver are converted to DM.
 407  */
 408 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 409 {
 410         switch (adap->hwadapnr) {
 411 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 412         case 3:
 413                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 414 #endif
 415 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 416         case 2:
 417                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 418 #endif
 419 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 420         case 1:
 421                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 422 #endif
 423         case 0:
 424                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 425         default:
 426                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 427         }
 428
 429         return NULL;
 430 }
 431
 432 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 433                                          unsigned int speed)
 434 {
 435         adap->speed = speed;
 436         return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
 437 }
 438
 439 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 440 {
 441         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 442 }
 443
 444 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 445                        int alen, u8 *buffer, int len)
 446 {
 447         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 448 }
 449
 450 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 451                         int alen, u8 *buffer, int len)
 452 {
 453         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 454 }
 455
 456 /* dw_i2c_probe - Probe the i2c chip */
 457 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 458 {
 459         struct i2c_regs *i2c_base = i2c_get_base(adap);
 460         u32 tmp;
 461         int ret;
 462
 463         /*
 464          * Try to read the first location of the chip.
 465          */
 466         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 467         if (ret)
 468                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 469
 470         return ret;
 471 }
 472
 473 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 474                          dw_i2c_write, dw_i2c_set_bus_speed,
 475                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 476
 477 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 478 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 479                          dw_i2c_write, dw_i2c_set_bus_speed,
 480                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 481 #endif
 482
 483 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 484 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 485                          dw_i2c_write, dw_i2c_set_bus_speed,
 486                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 487 #endif
 488
 489 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 490 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 491                          dw_i2c_write, dw_i2c_set_bus_speed,
 492                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 493 #endif
 494
 495 #else /* CONFIG_DM_I2C */
 496 /* The DM I2C functions */
 497
 498 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 499                                int nmsgs)
 500 {
 501         struct dw_i2c *i2c = dev_get_priv(bus);
 502         int ret;
 503
 504         debug("i2c_xfer: %d messages\n", nmsgs);
 505         for (; nmsgs > 0; nmsgs--, msg++) {
 506                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 507                 if (msg->flags & I2C_M_RD) {
 508                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 509                                             msg->buf, msg->len);
 510                 } else {
 511                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 512                                              msg->buf, msg->len);
 513                 }
 514                 if (ret) {
 515                         debug("i2c_write: error sending\n");
 516                         return -EREMOTEIO;
 517                 }
 518         }
 519
 520         return 0;
 521 }
 522
 523 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 524 {
 525         struct dw_i2c *i2c = dev_get_priv(bus);
 526
 527         return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
 528 }
 529
 530 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 531                                      uint chip_flags)
 532 {
 533         struct dw_i2c *i2c = dev_get_priv(bus);
 534         struct i2c_regs *i2c_base = i2c->regs;
 535         u32 tmp;
 536         int ret;
 537
 538         /* Try to read the first location of the chip */
 539         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 540         if (ret)
 541                 __dw_i2c_init(i2c_base, 0, 0);
 542
 543         return ret;
 544 }
 545
 546 static int designware_i2c_probe(struct udevice *bus)
 547 {
 548         struct dw_i2c *priv = dev_get_priv(bus);
 549         int ret;
 550
 551         if (device_is_on_pci_bus(bus)) {
 552 #ifdef CONFIG_DM_PCI
 553                 /* Save base address from PCI BAR */
 554                 priv->regs = (struct i2c_regs *)
 555                         dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 556 #ifdef CONFIG_X86
 557                 /* Use BayTrail specific timing values */
 558                 priv->scl_sda_cfg = &byt_config;
 559 #endif
 560 #endif
 561         } else {
 562                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 563         }
 564
 565         ret = reset_get_by_name(bus, "i2c", &priv->reset_ctl);
 566         if (ret)
 567                 pr_info("reset_get_by_name() failed: %d\n", ret);
 568
 569         if (&priv->reset_ctl)
 570                 reset_deassert(&priv->reset_ctl);
 571
 572         return __dw_i2c_init(priv->regs, 0, 0);
 573 }
 574
 575 static int designware_i2c_bind(struct udevice *dev)
 576 {
 577         static int num_cards;
 578         char name[20];
 579
 580         /* Create a unique device name for PCI type devices */
 581         if (device_is_on_pci_bus(dev)) {
 582                 /*
 583                  * ToDo:
 584                  * Setting req_seq in the driver is probably not recommended.
 585                  * But without a DT alias the number is not configured. And
 586                  * using this driver is impossible for PCIe I2C devices.
 587                  * This can be removed, once a better (correct) way for this
 588                  * is found and implemented.
 589                  */
 590                 dev->req_seq = num_cards;
 591                 sprintf(name, "i2c_designware#%u", num_cards++);
 592                 device_set_name(dev, name);
 593         }
 594
 595         return 0;
 596 }
 597
 598 static const struct dm_i2c_ops designware_i2c_ops = {
 599         .xfer           = designware_i2c_xfer,
 600         .probe_chip     = designware_i2c_probe_chip,
 601         .set_bus_speed  = designware_i2c_set_bus_speed,
 602 };
 603
 604 static const struct udevice_id designware_i2c_ids[] = {
 605         { .compatible = "snps,designware-i2c" },
 606         { }
 607 };
 608
 609 U_BOOT_DRIVER(i2c_designware) = {
 610         .name   = "i2c_designware",
 611         .id     = UCLASS_I2C,
 612         .of_match = designware_i2c_ids,
 613         .bind   = designware_i2c_bind,
 614         .probe  = designware_i2c_probe,
 615         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 616         .ops    = &designware_i2c_ops,
 617 };
 618
 619 #ifdef CONFIG_X86
 620 static struct pci_device_id designware_pci_supported[] = {
 621         /* Intel BayTrail has 7 I2C controller located on the PCI bus */
 622         { PCI_VDEVICE(INTEL, 0x0f41) },
 623         { PCI_VDEVICE(INTEL, 0x0f42) },
 624         { PCI_VDEVICE(INTEL, 0x0f43) },
 625         { PCI_VDEVICE(INTEL, 0x0f44) },
 626         { PCI_VDEVICE(INTEL, 0x0f45) },
 627         { PCI_VDEVICE(INTEL, 0x0f46) },
 628         { PCI_VDEVICE(INTEL, 0x0f47) },
 629         {},
 630 };
 631
 632 U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
 633 #endif
 634
 635 #endif /* CONFIG_DM_I2C */