drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <pci.h>
  12 #include <reset.h>
  13 #include <asm/io.h>
  14 #include "designware_i2c.h"
  15
  16 /**
  17  * struct dw_i2c_speed_config - timings to use for a particular speed
  18  *
  19  * This holds calculated values to be written to the I2C controller. Each value
  20  * is represented as a number of IC clock cycles.
  21  *
  22  * @scl_lcnt: Low count value for SCL
  23  * @scl_hcnt: High count value for SCL
  24  * @sda_hold: Data hold count
  25  */
  26 struct dw_i2c_speed_config {
  27         /* SCL high and low period count */
  28         uint scl_lcnt;
  29         uint scl_hcnt;
  30         uint sda_hold;
  31 };
  32
  33 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  34 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  35 {
  36         u32 ena = enable ? IC_ENABLE_0B : 0;
  37
  38         writel(ena, &i2c_base->ic_enable);
  39
  40         return 0;
  41 }
  42 #else
  43 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  44 {
  45         u32 ena = enable ? IC_ENABLE_0B : 0;
  46         int timeout = 100;
  47
  48         do {
  49                 writel(ena, &i2c_base->ic_enable);
  50                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  51                         return 0;
  52
  53                 /*
  54                  * Wait 10 times the signaling period of the highest I2C
  55                  * transfer supported by the driver (for 400KHz this is
  56                  * 25us) as described in the DesignWare I2C databook.
  57                  */
  58                 udelay(25);
  59         } while (timeout--);
  60         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  61
  62         return -ETIMEDOUT;
  63 }
  64 #endif
  65
  66 /* High and low times in different speed modes (in ns) */
  67 enum {
  68         /* SDA Hold Time */
  69         DEFAULT_SDA_HOLD_TIME           = 300,
  70 };
  71
  72 /**
  73  * calc_counts() - Convert a period to a number of IC clk cycles
  74  *
  75  * @ic_clk: Input clock in Hz
  76  * @period_ns: Period to represent, in ns
  77  * @return calculated count
  78  */
  79 static uint calc_counts(uint ic_clk, uint period_ns)
  80 {
  81         return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  82 }
  83
  84 /**
  85  * struct i2c_mode_info - Information about an I2C speed mode
  86  *
  87  * Each speed mode has its own characteristics. This struct holds these to aid
  88  * calculations in dw_i2c_calc_timing().
  89  *
  90  * @speed: Speed in Hz
  91  * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  92  * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  93  * @def_rise_time_ns: Default rise time in ns
  94  * @def_fall_time_ns: Default fall time in ns
  95  */
  96 struct i2c_mode_info {
  97         int speed;
  98         int min_scl_hightime_ns;
  99         int min_scl_lowtime_ns;
 100         int def_rise_time_ns;
 101         int def_fall_time_ns;
 102 };
 103
 104 static const struct i2c_mode_info info_for_mode[] = {
 105         [IC_SPEED_MODE_STANDARD] = {
 106                 I2C_STANDARD_SPEED,
 107                 MIN_SS_SCL_HIGHTIME,
 108                 MIN_SS_SCL_LOWTIME,
 109                 1000,
 110                 300,
 111         },
 112         [IC_SPEED_MODE_FAST] = {
 113                 I2C_FAST_SPEED,
 114                 MIN_FS_SCL_HIGHTIME,
 115                 MIN_FS_SCL_LOWTIME,
 116                 300,
 117                 300,
 118         },
 119         [IC_SPEED_MODE_HIGH] = {
 120                 I2C_HIGH_SPEED,
 121                 MIN_HS_SCL_HIGHTIME,
 122                 MIN_HS_SCL_LOWTIME,
 123                 120,
 124                 120,
 125         },
 126 };
 127
 128 /**
 129  * dw_i2c_calc_timing() - Calculate the timings to use for a bus
 130  *
 131  * @priv: Bus private information (NULL if not using driver model)
 132  * @mode: Speed mode to use
 133  * @ic_clk: IC clock speed in Hz
 134  * @spk_cnt: Spike-suppression count
 135  * @config: Returns value to use
 136  * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
 137  */
 138 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 139                               int ic_clk, int spk_cnt,
 140                               struct dw_i2c_speed_config *config)
 141 {
 142         int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
 143         int hcnt, lcnt, period_cnt, diff, tot;
 144         int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
 145         const struct i2c_mode_info *info;
 146
 147         /*
 148          * Find the period, rise, fall, min tlow, and min thigh in terms of
 149          * counts of the IC clock
 150          */
 151         info = &info_for_mode[mode];
 152         period_cnt = ic_clk / info->speed;
 153         scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
 154                  priv->scl_rise_time_ns : info->def_rise_time_ns;
 155         scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
 156                  priv->scl_fall_time_ns : info->def_fall_time_ns;
 157         rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
 158         fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
 159         min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
 160         min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
 161
 162         debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
 163               period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
 164               spk_cnt);
 165
 166         /*
 167          * Back-solve for hcnt and lcnt according to the following equations:
 168          * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
 169          * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
 170          */
 171         hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
 172         lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
 173
 174         if (hcnt < 0 || lcnt < 0) {
 175                 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
 176                 return -EINVAL;
 177         }
 178
 179         /*
 180          * Now add things back up to ensure the period is hit. If it is off,
 181          * split the difference and bias to lcnt for remainder
 182          */
 183         tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 184
 185         if (tot < period_cnt) {
 186                 diff = (period_cnt - tot) / 2;
 187                 hcnt += diff;
 188                 lcnt += diff;
 189                 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 190                 lcnt += period_cnt - tot;
 191         }
 192
 193         config->scl_lcnt = lcnt;
 194         config->scl_hcnt = hcnt;
 195
 196         /* Use internal default unless other value is specified */
 197         sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
 198                  priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
 199         config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
 200
 201         debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
 202               config->sda_hold);
 203
 204         return 0;
 205 }
 206
 207 /*
 208  * i2c_set_bus_speed - Set the i2c speed
 209  * @speed:      required i2c speed
 210  *
 211  * Set the i2c speed.
 212  */
 213 static unsigned int __dw_i2c_set_bus_speed(struct dw_i2c *priv,
 214                                            struct i2c_regs *i2c_base,
 215                                            unsigned int speed,
 216                                            unsigned int bus_clk)
 217 {
 218         const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
 219         struct dw_i2c_speed_config config;
 220         enum i2c_speed_mode i2c_spd;
 221         unsigned int cntl;
 222         unsigned int ena;
 223         int spk_cnt;
 224         int ret;
 225
 226         if (priv)
 227                 scl_sda_cfg = priv->scl_sda_cfg;
 228         /* Allow high speed if there is no config, or the config allows it */
 229         if (speed >= I2C_HIGH_SPEED &&
 230             (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
 231                 i2c_spd = IC_SPEED_MODE_HIGH;
 232         else if (speed >= I2C_FAST_SPEED)
 233                 i2c_spd = IC_SPEED_MODE_FAST;
 234         else
 235                 i2c_spd = IC_SPEED_MODE_STANDARD;
 236
 237         /* Get enable setting for restore later */
 238         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
 239
 240         /* to set speed cltr must be disabled */
 241         dw_i2c_enable(i2c_base, false);
 242
 243         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 244
 245         /* Get the proper spike-suppression count based on target speed */
 246         if (!priv || !priv->has_spk_cnt)
 247                 spk_cnt = 0;
 248         else if (i2c_spd >= IC_SPEED_MODE_HIGH)
 249                 spk_cnt = readl(&i2c_base->hs_spklen);
 250         else
 251                 spk_cnt = readl(&i2c_base->fs_spklen);
 252         if (scl_sda_cfg) {
 253                 config.sda_hold = scl_sda_cfg->sda_hold;
 254                 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
 255                         config.scl_hcnt = scl_sda_cfg->ss_hcnt;
 256                         config.scl_lcnt = scl_sda_cfg->ss_lcnt;
 257                 } else {
 258                         config.scl_hcnt = scl_sda_cfg->fs_hcnt;
 259                         config.scl_lcnt = scl_sda_cfg->fs_lcnt;
 260                 }
 261         } else {
 262                 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
 263                                          &config);
 264                 if (ret)
 265                         return log_msg_ret("gen_confg", ret);
 266         }
 267
 268         switch (i2c_spd) {
 269         case IC_SPEED_MODE_HIGH:
 270                 cntl |= IC_CON_SPD_SS;
 271                 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
 272                 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
 273                 break;
 274
 275         case IC_SPEED_MODE_STANDARD:
 276                 cntl |= IC_CON_SPD_SS;
 277                 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
 278                 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
 279                 break;
 280
 281         case IC_SPEED_MODE_FAST:
 282         default:
 283                 cntl |= IC_CON_SPD_FS;
 284                 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
 285                 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
 286                 break;
 287         }
 288
 289         writel(cntl, &i2c_base->ic_con);
 290
 291         /* Configure SDA Hold Time if required */
 292         if (config.sda_hold)
 293                 writel(config.sda_hold, &i2c_base->ic_sda_hold);
 294
 295         /* Restore back i2c now speed set */
 296         if (ena == IC_ENABLE_0B)
 297                 dw_i2c_enable(i2c_base, true);
 298
 299         return 0;
 300 }
 301
 302 /*
 303  * i2c_setaddress - Sets the target slave address
 304  * @i2c_addr:   target i2c address
 305  *
 306  * Sets the target slave address.
 307  */
 308 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 309 {
 310         /* Disable i2c */
 311         dw_i2c_enable(i2c_base, false);
 312
 313         writel(i2c_addr, &i2c_base->ic_tar);
 314
 315         /* Enable i2c */
 316         dw_i2c_enable(i2c_base, true);
 317 }
 318
 319 /*
 320  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 321  *
 322  * Flushes the i2c RX FIFO
 323  */
 324 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 325 {
 326         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 327                 readl(&i2c_base->ic_cmd_data);
 328 }
 329
 330 /*
 331  * i2c_wait_for_bb - Waits for bus busy
 332  *
 333  * Waits for bus busy
 334  */
 335 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 336 {
 337         unsigned long start_time_bb = get_timer(0);
 338
 339         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 340                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 341
 342                 /* Evaluate timeout */
 343                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 344                         return 1;
 345         }
 346
 347         return 0;
 348 }
 349
 350 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 351                          int alen)
 352 {
 353         if (i2c_wait_for_bb(i2c_base))
 354                 return 1;
 355
 356         i2c_setaddress(i2c_base, chip);
 357         while (alen) {
 358                 alen--;
 359                 /* high byte address going out first */
 360                 writel((addr >> (alen * 8)) & 0xff,
 361                        &i2c_base->ic_cmd_data);
 362         }
 363         return 0;
 364 }
 365
 366 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 367 {
 368         ulong start_stop_det = get_timer(0);
 369
 370         while (1) {
 371                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 372                         readl(&i2c_base->ic_clr_stop_det);
 373                         break;
 374                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 375                         break;
 376                 }
 377         }
 378
 379         if (i2c_wait_for_bb(i2c_base)) {
 380                 printf("Timed out waiting for bus\n");
 381                 return 1;
 382         }
 383
 384         i2c_flush_rxfifo(i2c_base);
 385
 386         return 0;
 387 }
 388
 389 /*
 390  * i2c_read - Read from i2c memory
 391  * @chip:       target i2c address
 392  * @addr:       address to read from
 393  * @alen:
 394  * @buffer:     buffer for read data
 395  * @len:        no of bytes to be read
 396  *
 397  * Read from i2c memory.
 398  */
 399 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 400                          int alen, u8 *buffer, int len)
 401 {
 402         unsigned long start_time_rx;
 403         unsigned int active = 0;
 404
 405 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 406         /*
 407          * EEPROM chips that implement "address overflow" are ones
 408          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 409          * address and the extra bits end up in the "chip address"
 410          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 411          * four 256 byte chips.
 412          *
 413          * Note that we consider the length of the address field to
 414          * still be one byte because the extra address bits are
 415          * hidden in the chip address.
 416          */
 417         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 418         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 419
 420         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 421               addr);
 422 #endif
 423
 424         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 425                 return 1;
 426
 427         start_time_rx = get_timer(0);
 428         while (len) {
 429                 if (!active) {
 430                         /*
 431                          * Avoid writing to ic_cmd_data multiple times
 432                          * in case this loop spins too quickly and the
 433                          * ic_status RFNE bit isn't set after the first
 434                          * write. Subsequent writes to ic_cmd_data can
 435                          * trigger spurious i2c transfer.
 436                          */
 437                         if (len == 1)
 438                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 439                         else
 440                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 441                         active = 1;
 442                 }
 443
 444                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 445                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 446                         len--;
 447                         start_time_rx = get_timer(0);
 448                         active = 0;
 449                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 450                         return 1;
 451                 }
 452         }
 453
 454         return i2c_xfer_finish(i2c_base);
 455 }
 456
 457 /*
 458  * i2c_write - Write to i2c memory
 459  * @chip:       target i2c address
 460  * @addr:       address to read from
 461  * @alen:
 462  * @buffer:     buffer for read data
 463  * @len:        no of bytes to be read
 464  *
 465  * Write to i2c memory.
 466  */
 467 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 468                           int alen, u8 *buffer, int len)
 469 {
 470         int nb = len;
 471         unsigned long start_time_tx;
 472
 473 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 474         /*
 475          * EEPROM chips that implement "address overflow" are ones
 476          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 477          * address and the extra bits end up in the "chip address"
 478          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 479          * four 256 byte chips.
 480          *
 481          * Note that we consider the length of the address field to
 482          * still be one byte because the extra address bits are
 483          * hidden in the chip address.
 484          */
 485         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 486         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 487
 488         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 489               addr);
 490 #endif
 491
 492         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 493                 return 1;
 494
 495         start_time_tx = get_timer(0);
 496         while (len) {
 497                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 498                         if (--len == 0) {
 499                                 writel(*buffer | IC_STOP,
 500                                        &i2c_base->ic_cmd_data);
 501                         } else {
 502                                 writel(*buffer, &i2c_base->ic_cmd_data);
 503                         }
 504                         buffer++;
 505                         start_time_tx = get_timer(0);
 506
 507                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 508                                 printf("Timed out. i2c write Failed\n");
 509                                 return 1;
 510                 }
 511         }
 512
 513         return i2c_xfer_finish(i2c_base);
 514 }
 515
 516 /*
 517  * __dw_i2c_init - Init function
 518  * @speed:      required i2c speed
 519  * @slaveaddr:  slave address for the device
 520  *
 521  * Initialization function.
 522  */
 523 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 524 {
 525         int ret;
 526
 527         /* Disable i2c */
 528         ret = dw_i2c_enable(i2c_base, false);
 529         if (ret)
 530                 return ret;
 531
 532         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 533                &i2c_base->ic_con);
 534         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 535         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 536         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 537 #ifndef CONFIG_DM_I2C
 538         __dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
 539         writel(slaveaddr, &i2c_base->ic_sar);
 540 #endif
 541
 542         /* Enable i2c */
 543         ret = dw_i2c_enable(i2c_base, true);
 544         if (ret)
 545                 return ret;
 546
 547         return 0;
 548 }
 549
 550 #ifndef CONFIG_DM_I2C
 551 /*
 552  * The legacy I2C functions. These need to get removed once
 553  * all users of this driver are converted to DM.
 554  */
 555 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 556 {
 557         switch (adap->hwadapnr) {
 558 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 559         case 3:
 560                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 561 #endif
 562 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 563         case 2:
 564                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 565 #endif
 566 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 567         case 1:
 568                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 569 #endif
 570         case 0:
 571                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 572         default:
 573                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 574         }
 575
 576         return NULL;
 577 }
 578
 579 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 580                                          unsigned int speed)
 581 {
 582         adap->speed = speed;
 583         return __dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
 584 }
 585
 586 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 587 {
 588         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 589 }
 590
 591 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 592                        int alen, u8 *buffer, int len)
 593 {
 594         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 595 }
 596
 597 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 598                         int alen, u8 *buffer, int len)
 599 {
 600         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 601 }
 602
 603 /* dw_i2c_probe - Probe the i2c chip */
 604 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 605 {
 606         struct i2c_regs *i2c_base = i2c_get_base(adap);
 607         u32 tmp;
 608         int ret;
 609
 610         /*
 611          * Try to read the first location of the chip.
 612          */
 613         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 614         if (ret)
 615                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 616
 617         return ret;
 618 }
 619
 620 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 621                          dw_i2c_write, dw_i2c_set_bus_speed,
 622                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 623
 624 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 625 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 626                          dw_i2c_write, dw_i2c_set_bus_speed,
 627                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 628 #endif
 629
 630 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 631 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 632                          dw_i2c_write, dw_i2c_set_bus_speed,
 633                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 634 #endif
 635
 636 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 637 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 638                          dw_i2c_write, dw_i2c_set_bus_speed,
 639                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 640 #endif
 641
 642 #else /* CONFIG_DM_I2C */
 643 /* The DM I2C functions */
 644
 645 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 646                                int nmsgs)
 647 {
 648         struct dw_i2c *i2c = dev_get_priv(bus);
 649         int ret;
 650
 651         debug("i2c_xfer: %d messages\n", nmsgs);
 652         for (; nmsgs > 0; nmsgs--, msg++) {
 653                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 654                 if (msg->flags & I2C_M_RD) {
 655                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 656                                             msg->buf, msg->len);
 657                 } else {
 658                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 659                                              msg->buf, msg->len);
 660                 }
 661                 if (ret) {
 662                         debug("i2c_write: error sending\n");
 663                         return -EREMOTEIO;
 664                 }
 665         }
 666
 667         return 0;
 668 }
 669
 670 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 671 {
 672         struct dw_i2c *i2c = dev_get_priv(bus);
 673         ulong rate;
 674
 675 #if CONFIG_IS_ENABLED(CLK)
 676         rate = clk_get_rate(&i2c->clk);
 677         if (IS_ERR_VALUE(rate))
 678                 return -EINVAL;
 679 #else
 680         rate = IC_CLK;
 681 #endif
 682         return __dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
 683 }
 684
 685 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 686                                      uint chip_flags)
 687 {
 688         struct dw_i2c *i2c = dev_get_priv(bus);
 689         struct i2c_regs *i2c_base = i2c->regs;
 690         u32 tmp;
 691         int ret;
 692
 693         /* Try to read the first location of the chip */
 694         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 695         if (ret)
 696                 __dw_i2c_init(i2c_base, 0, 0);
 697
 698         return ret;
 699 }
 700
 701 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 702 {
 703         struct dw_i2c *priv = dev_get_priv(bus);
 704
 705         if (!priv->regs)
 706                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 707         dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
 708         dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
 709         dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
 710
 711         return 0;
 712 }
 713
 714 int designware_i2c_probe(struct udevice *bus)
 715 {
 716         struct dw_i2c *priv = dev_get_priv(bus);
 717         int ret;
 718
 719         ret = reset_get_bulk(bus, &priv->resets);
 720         if (ret)
 721                 dev_warn(bus, "Can't get reset: %d\n", ret);
 722         else
 723                 reset_deassert_bulk(&priv->resets);
 724
 725 #if CONFIG_IS_ENABLED(CLK)
 726         ret = clk_get_by_index(bus, 0, &priv->clk);
 727         if (ret)
 728                 return ret;
 729
 730         ret = clk_enable(&priv->clk);
 731         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 732                 clk_free(&priv->clk);
 733                 dev_err(bus, "failed to enable clock\n");
 734                 return ret;
 735         }
 736 #endif
 737
 738         return __dw_i2c_init(priv->regs, 0, 0);
 739 }
 740
 741 int designware_i2c_remove(struct udevice *dev)
 742 {
 743         struct dw_i2c *priv = dev_get_priv(dev);
 744
 745 #if CONFIG_IS_ENABLED(CLK)
 746         clk_disable(&priv->clk);
 747         clk_free(&priv->clk);
 748 #endif
 749
 750         return reset_release_bulk(&priv->resets);
 751 }
 752
 753 const struct dm_i2c_ops designware_i2c_ops = {
 754         .xfer           = designware_i2c_xfer,
 755         .probe_chip     = designware_i2c_probe_chip,
 756         .set_bus_speed  = designware_i2c_set_bus_speed,
 757 };
 758
 759 static const struct udevice_id designware_i2c_ids[] = {
 760         { .compatible = "snps,designware-i2c" },
 761         { }
 762 };
 763
 764 U_BOOT_DRIVER(i2c_designware) = {
 765         .name   = "i2c_designware",
 766         .id     = UCLASS_I2C,
 767         .of_match = designware_i2c_ids,
 768         .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
 769         .probe  = designware_i2c_probe,
 770         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 771         .remove = designware_i2c_remove,
 772         .flags  = DM_FLAG_OS_PREPARE,
 773         .ops    = &designware_i2c_ops,
 774 };
 775
 776 #endif /* CONFIG_DM_I2C */