drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <pci.h>
  12 #include <reset.h>
  13 #include <asm/io.h>
  14 #include "designware_i2c.h"
  15
  16 /**
  17  * struct dw_i2c_speed_config - timings to use for a particular speed
  18  *
  19  * This holds calculated values to be written to the I2C controller. Each value
  20  * is represented as a number of IC clock cycles.
  21  *
  22  * @scl_lcnt: Low count value for SCL
  23  * @scl_hcnt: High count value for SCL
  24  * @sda_hold: Data hold count
  25  */
  26 struct dw_i2c_speed_config {
  27         /* SCL high and low period count */
  28         uint scl_lcnt;
  29         uint scl_hcnt;
  30         uint sda_hold;
  31 };
  32
  33 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  34 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  35 {
  36         u32 ena = enable ? IC_ENABLE_0B : 0;
  37
  38         writel(ena, &i2c_base->ic_enable);
  39
  40         return 0;
  41 }
  42 #else
  43 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  44 {
  45         u32 ena = enable ? IC_ENABLE_0B : 0;
  46         int timeout = 100;
  47
  48         do {
  49                 writel(ena, &i2c_base->ic_enable);
  50                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  51                         return 0;
  52
  53                 /*
  54                  * Wait 10 times the signaling period of the highest I2C
  55                  * transfer supported by the driver (for 400KHz this is
  56                  * 25us) as described in the DesignWare I2C databook.
  57                  */
  58                 udelay(25);
  59         } while (timeout--);
  60         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  61
  62         return -ETIMEDOUT;
  63 }
  64 #endif
  65
  66 /* High and low times in different speed modes (in ns) */
  67 enum {
  68         /* SDA Hold Time */
  69         DEFAULT_SDA_HOLD_TIME           = 300,
  70 };
  71
  72 /**
  73  * calc_counts() - Convert a period to a number of IC clk cycles
  74  *
  75  * @ic_clk: Input clock in Hz
  76  * @period_ns: Period to represent, in ns
  77  * @return calculated count
  78  */
  79 static uint calc_counts(uint ic_clk, uint period_ns)
  80 {
  81         return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  82 }
  83
  84 /**
  85  * struct i2c_mode_info - Information about an I2C speed mode
  86  *
  87  * Each speed mode has its own characteristics. This struct holds these to aid
  88  * calculations in dw_i2c_calc_timing().
  89  *
  90  * @speed: Speed in Hz
  91  * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  92  * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  93  * @def_rise_time_ns: Default rise time in ns
  94  * @def_fall_time_ns: Default fall time in ns
  95  */
  96 struct i2c_mode_info {
  97         int speed;
  98         int min_scl_hightime_ns;
  99         int min_scl_lowtime_ns;
 100         int def_rise_time_ns;
 101         int def_fall_time_ns;
 102 };
 103
 104 static const struct i2c_mode_info info_for_mode[] = {
 105         [IC_SPEED_MODE_STANDARD] = {
 106                 I2C_STANDARD_SPEED,
 107                 MIN_SS_SCL_HIGHTIME,
 108                 MIN_SS_SCL_LOWTIME,
 109                 1000,
 110                 300,
 111         },
 112         [IC_SPEED_MODE_FAST] = {
 113                 I2C_FAST_SPEED,
 114                 MIN_FS_SCL_HIGHTIME,
 115                 MIN_FS_SCL_LOWTIME,
 116                 300,
 117                 300,
 118         },
 119         [IC_SPEED_MODE_HIGH] = {
 120                 I2C_HIGH_SPEED,
 121                 MIN_HS_SCL_HIGHTIME,
 122                 MIN_HS_SCL_LOWTIME,
 123                 120,
 124                 120,
 125         },
 126 };
 127
 128 /**
 129  * dw_i2c_calc_timing() - Calculate the timings to use for a bus
 130  *
 131  * @priv: Bus private information (NULL if not using driver model)
 132  * @mode: Speed mode to use
 133  * @ic_clk: IC clock speed in Hz
 134  * @spk_cnt: Spike-suppression count
 135  * @config: Returns value to use
 136  * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
 137  */
 138 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 139                               int ic_clk, int spk_cnt,
 140                               struct dw_i2c_speed_config *config)
 141 {
 142         int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
 143         int hcnt, lcnt, period_cnt, diff, tot;
 144         int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
 145         const struct i2c_mode_info *info;
 146
 147         /*
 148          * Find the period, rise, fall, min tlow, and min thigh in terms of
 149          * counts of the IC clock
 150          */
 151         info = &info_for_mode[mode];
 152         period_cnt = ic_clk / info->speed;
 153         scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
 154                  priv->scl_rise_time_ns : info->def_rise_time_ns;
 155         scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
 156                  priv->scl_fall_time_ns : info->def_fall_time_ns;
 157         rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
 158         fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
 159         min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
 160         min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
 161
 162         debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
 163               period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
 164               spk_cnt);
 165
 166         /*
 167          * Back-solve for hcnt and lcnt according to the following equations:
 168          * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
 169          * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
 170          */
 171         hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
 172         lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
 173
 174         if (hcnt < 0 || lcnt < 0) {
 175                 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
 176                 return -EINVAL;
 177         }
 178
 179         /*
 180          * Now add things back up to ensure the period is hit. If it is off,
 181          * split the difference and bias to lcnt for remainder
 182          */
 183         tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 184
 185         if (tot < period_cnt) {
 186                 diff = (period_cnt - tot) / 2;
 187                 hcnt += diff;
 188                 lcnt += diff;
 189                 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 190                 lcnt += period_cnt - tot;
 191         }
 192
 193         config->scl_lcnt = lcnt;
 194         config->scl_hcnt = hcnt;
 195
 196         /* Use internal default unless other value is specified */
 197         sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
 198                  priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
 199         config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
 200
 201         debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
 202               config->sda_hold);
 203
 204         return 0;
 205 }
 206
 207 /*
 208  * i2c_set_bus_speed - Set the i2c speed
 209  * @speed:      required i2c speed
 210  *
 211  * Set the i2c speed.
 212  */
 213 static unsigned int __dw_i2c_set_bus_speed(struct dw_i2c *priv,
 214                                            struct i2c_regs *i2c_base,
 215                                            unsigned int speed,
 216                                            unsigned int bus_clk)
 217 {
 218         const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
 219         struct dw_i2c_speed_config config;
 220         enum i2c_speed_mode i2c_spd;
 221         unsigned int cntl;
 222         unsigned int ena;
 223         int ret;
 224
 225         if (priv)
 226                 scl_sda_cfg = priv->scl_sda_cfg;
 227         /* Allow high speed if there is no config, or the config allows it */
 228         if (speed >= I2C_HIGH_SPEED &&
 229             (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
 230                 i2c_spd = IC_SPEED_MODE_HIGH;
 231         else if (speed >= I2C_FAST_SPEED)
 232                 i2c_spd = IC_SPEED_MODE_FAST;
 233         else
 234                 i2c_spd = IC_SPEED_MODE_STANDARD;
 235
 236         /* Get enable setting for restore later */
 237         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
 238
 239         /* to set speed cltr must be disabled */
 240         dw_i2c_enable(i2c_base, false);
 241
 242         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 243
 244         if (scl_sda_cfg) {
 245                 config.sda_hold = scl_sda_cfg->sda_hold;
 246                 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
 247                         config.scl_hcnt = scl_sda_cfg->ss_hcnt;
 248                         config.scl_lcnt = scl_sda_cfg->ss_lcnt;
 249                 } else {
 250                         config.scl_hcnt = scl_sda_cfg->fs_hcnt;
 251                         config.scl_lcnt = scl_sda_cfg->fs_lcnt;
 252                 }
 253         } else {
 254                 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, 0,
 255                                          &config);
 256                 if (ret)
 257                         return log_msg_ret("gen_confg", ret);
 258         }
 259
 260         switch (i2c_spd) {
 261         case IC_SPEED_MODE_HIGH:
 262                 cntl |= IC_CON_SPD_SS;
 263                 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
 264                 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
 265                 break;
 266
 267         case IC_SPEED_MODE_STANDARD:
 268                 cntl |= IC_CON_SPD_SS;
 269                 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
 270                 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
 271                 break;
 272
 273         case IC_SPEED_MODE_FAST:
 274         default:
 275                 cntl |= IC_CON_SPD_FS;
 276                 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
 277                 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
 278                 break;
 279         }
 280
 281         writel(cntl, &i2c_base->ic_con);
 282
 283         /* Configure SDA Hold Time if required */
 284         if (config.sda_hold)
 285                 writel(config.sda_hold, &i2c_base->ic_sda_hold);
 286
 287         /* Restore back i2c now speed set */
 288         if (ena == IC_ENABLE_0B)
 289                 dw_i2c_enable(i2c_base, true);
 290
 291         return 0;
 292 }
 293
 294 /*
 295  * i2c_setaddress - Sets the target slave address
 296  * @i2c_addr:   target i2c address
 297  *
 298  * Sets the target slave address.
 299  */
 300 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 301 {
 302         /* Disable i2c */
 303         dw_i2c_enable(i2c_base, false);
 304
 305         writel(i2c_addr, &i2c_base->ic_tar);
 306
 307         /* Enable i2c */
 308         dw_i2c_enable(i2c_base, true);
 309 }
 310
 311 /*
 312  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 313  *
 314  * Flushes the i2c RX FIFO
 315  */
 316 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 317 {
 318         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 319                 readl(&i2c_base->ic_cmd_data);
 320 }
 321
 322 /*
 323  * i2c_wait_for_bb - Waits for bus busy
 324  *
 325  * Waits for bus busy
 326  */
 327 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 328 {
 329         unsigned long start_time_bb = get_timer(0);
 330
 331         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 332                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 333
 334                 /* Evaluate timeout */
 335                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 336                         return 1;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 343                          int alen)
 344 {
 345         if (i2c_wait_for_bb(i2c_base))
 346                 return 1;
 347
 348         i2c_setaddress(i2c_base, chip);
 349         while (alen) {
 350                 alen--;
 351                 /* high byte address going out first */
 352                 writel((addr >> (alen * 8)) & 0xff,
 353                        &i2c_base->ic_cmd_data);
 354         }
 355         return 0;
 356 }
 357
 358 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 359 {
 360         ulong start_stop_det = get_timer(0);
 361
 362         while (1) {
 363                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 364                         readl(&i2c_base->ic_clr_stop_det);
 365                         break;
 366                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 367                         break;
 368                 }
 369         }
 370
 371         if (i2c_wait_for_bb(i2c_base)) {
 372                 printf("Timed out waiting for bus\n");
 373                 return 1;
 374         }
 375
 376         i2c_flush_rxfifo(i2c_base);
 377
 378         return 0;
 379 }
 380
 381 /*
 382  * i2c_read - Read from i2c memory
 383  * @chip:       target i2c address
 384  * @addr:       address to read from
 385  * @alen:
 386  * @buffer:     buffer for read data
 387  * @len:        no of bytes to be read
 388  *
 389  * Read from i2c memory.
 390  */
 391 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 392                          int alen, u8 *buffer, int len)
 393 {
 394         unsigned long start_time_rx;
 395         unsigned int active = 0;
 396
 397 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 398         /*
 399          * EEPROM chips that implement "address overflow" are ones
 400          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 401          * address and the extra bits end up in the "chip address"
 402          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 403          * four 256 byte chips.
 404          *
 405          * Note that we consider the length of the address field to
 406          * still be one byte because the extra address bits are
 407          * hidden in the chip address.
 408          */
 409         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 410         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 411
 412         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 413               addr);
 414 #endif
 415
 416         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 417                 return 1;
 418
 419         start_time_rx = get_timer(0);
 420         while (len) {
 421                 if (!active) {
 422                         /*
 423                          * Avoid writing to ic_cmd_data multiple times
 424                          * in case this loop spins too quickly and the
 425                          * ic_status RFNE bit isn't set after the first
 426                          * write. Subsequent writes to ic_cmd_data can
 427                          * trigger spurious i2c transfer.
 428                          */
 429                         if (len == 1)
 430                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 431                         else
 432                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 433                         active = 1;
 434                 }
 435
 436                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 437                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 438                         len--;
 439                         start_time_rx = get_timer(0);
 440                         active = 0;
 441                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 442                         return 1;
 443                 }
 444         }
 445
 446         return i2c_xfer_finish(i2c_base);
 447 }
 448
 449 /*
 450  * i2c_write - Write to i2c memory
 451  * @chip:       target i2c address
 452  * @addr:       address to read from
 453  * @alen:
 454  * @buffer:     buffer for read data
 455  * @len:        no of bytes to be read
 456  *
 457  * Write to i2c memory.
 458  */
 459 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 460                           int alen, u8 *buffer, int len)
 461 {
 462         int nb = len;
 463         unsigned long start_time_tx;
 464
 465 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 466         /*
 467          * EEPROM chips that implement "address overflow" are ones
 468          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 469          * address and the extra bits end up in the "chip address"
 470          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 471          * four 256 byte chips.
 472          *
 473          * Note that we consider the length of the address field to
 474          * still be one byte because the extra address bits are
 475          * hidden in the chip address.
 476          */
 477         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 478         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 479
 480         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 481               addr);
 482 #endif
 483
 484         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 485                 return 1;
 486
 487         start_time_tx = get_timer(0);
 488         while (len) {
 489                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 490                         if (--len == 0) {
 491                                 writel(*buffer | IC_STOP,
 492                                        &i2c_base->ic_cmd_data);
 493                         } else {
 494                                 writel(*buffer, &i2c_base->ic_cmd_data);
 495                         }
 496                         buffer++;
 497                         start_time_tx = get_timer(0);
 498
 499                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 500                                 printf("Timed out. i2c write Failed\n");
 501                                 return 1;
 502                 }
 503         }
 504
 505         return i2c_xfer_finish(i2c_base);
 506 }
 507
 508 /*
 509  * __dw_i2c_init - Init function
 510  * @speed:      required i2c speed
 511  * @slaveaddr:  slave address for the device
 512  *
 513  * Initialization function.
 514  */
 515 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 516 {
 517         int ret;
 518
 519         /* Disable i2c */
 520         ret = dw_i2c_enable(i2c_base, false);
 521         if (ret)
 522                 return ret;
 523
 524         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 525                &i2c_base->ic_con);
 526         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 527         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 528         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 529 #ifndef CONFIG_DM_I2C
 530         __dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
 531         writel(slaveaddr, &i2c_base->ic_sar);
 532 #endif
 533
 534         /* Enable i2c */
 535         ret = dw_i2c_enable(i2c_base, true);
 536         if (ret)
 537                 return ret;
 538
 539         return 0;
 540 }
 541
 542 #ifndef CONFIG_DM_I2C
 543 /*
 544  * The legacy I2C functions. These need to get removed once
 545  * all users of this driver are converted to DM.
 546  */
 547 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 548 {
 549         switch (adap->hwadapnr) {
 550 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 551         case 3:
 552                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 553 #endif
 554 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 555         case 2:
 556                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 557 #endif
 558 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 559         case 1:
 560                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 561 #endif
 562         case 0:
 563                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 564         default:
 565                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 566         }
 567
 568         return NULL;
 569 }
 570
 571 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 572                                          unsigned int speed)
 573 {
 574         adap->speed = speed;
 575         return __dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
 576 }
 577
 578 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 579 {
 580         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 581 }
 582
 583 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 584                        int alen, u8 *buffer, int len)
 585 {
 586         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 587 }
 588
 589 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 590                         int alen, u8 *buffer, int len)
 591 {
 592         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 593 }
 594
 595 /* dw_i2c_probe - Probe the i2c chip */
 596 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 597 {
 598         struct i2c_regs *i2c_base = i2c_get_base(adap);
 599         u32 tmp;
 600         int ret;
 601
 602         /*
 603          * Try to read the first location of the chip.
 604          */
 605         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 606         if (ret)
 607                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 608
 609         return ret;
 610 }
 611
 612 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 613                          dw_i2c_write, dw_i2c_set_bus_speed,
 614                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 615
 616 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 617 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 618                          dw_i2c_write, dw_i2c_set_bus_speed,
 619                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 620 #endif
 621
 622 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 623 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 624                          dw_i2c_write, dw_i2c_set_bus_speed,
 625                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 626 #endif
 627
 628 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 629 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 630                          dw_i2c_write, dw_i2c_set_bus_speed,
 631                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 632 #endif
 633
 634 #else /* CONFIG_DM_I2C */
 635 /* The DM I2C functions */
 636
 637 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 638                                int nmsgs)
 639 {
 640         struct dw_i2c *i2c = dev_get_priv(bus);
 641         int ret;
 642
 643         debug("i2c_xfer: %d messages\n", nmsgs);
 644         for (; nmsgs > 0; nmsgs--, msg++) {
 645                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 646                 if (msg->flags & I2C_M_RD) {
 647                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 648                                             msg->buf, msg->len);
 649                 } else {
 650                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 651                                              msg->buf, msg->len);
 652                 }
 653                 if (ret) {
 654                         debug("i2c_write: error sending\n");
 655                         return -EREMOTEIO;
 656                 }
 657         }
 658
 659         return 0;
 660 }
 661
 662 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 663 {
 664         struct dw_i2c *i2c = dev_get_priv(bus);
 665         ulong rate;
 666
 667 #if CONFIG_IS_ENABLED(CLK)
 668         rate = clk_get_rate(&i2c->clk);
 669         if (IS_ERR_VALUE(rate))
 670                 return -EINVAL;
 671 #else
 672         rate = IC_CLK;
 673 #endif
 674         return __dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
 675 }
 676
 677 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 678                                      uint chip_flags)
 679 {
 680         struct dw_i2c *i2c = dev_get_priv(bus);
 681         struct i2c_regs *i2c_base = i2c->regs;
 682         u32 tmp;
 683         int ret;
 684
 685         /* Try to read the first location of the chip */
 686         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 687         if (ret)
 688                 __dw_i2c_init(i2c_base, 0, 0);
 689
 690         return ret;
 691 }
 692
 693 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 694 {
 695         struct dw_i2c *priv = dev_get_priv(bus);
 696
 697         if (!priv->regs)
 698                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 699         dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
 700         dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
 701         dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
 702
 703         return 0;
 704 }
 705
 706 int designware_i2c_probe(struct udevice *bus)
 707 {
 708         struct dw_i2c *priv = dev_get_priv(bus);
 709         int ret;
 710
 711         ret = reset_get_bulk(bus, &priv->resets);
 712         if (ret)
 713                 dev_warn(bus, "Can't get reset: %d\n", ret);
 714         else
 715                 reset_deassert_bulk(&priv->resets);
 716
 717 #if CONFIG_IS_ENABLED(CLK)
 718         ret = clk_get_by_index(bus, 0, &priv->clk);
 719         if (ret)
 720                 return ret;
 721
 722         ret = clk_enable(&priv->clk);
 723         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 724                 clk_free(&priv->clk);
 725                 dev_err(bus, "failed to enable clock\n");
 726                 return ret;
 727         }
 728 #endif
 729
 730         return __dw_i2c_init(priv->regs, 0, 0);
 731 }
 732
 733 int designware_i2c_remove(struct udevice *dev)
 734 {
 735         struct dw_i2c *priv = dev_get_priv(dev);
 736
 737 #if CONFIG_IS_ENABLED(CLK)
 738         clk_disable(&priv->clk);
 739         clk_free(&priv->clk);
 740 #endif
 741
 742         return reset_release_bulk(&priv->resets);
 743 }
 744
 745 const struct dm_i2c_ops designware_i2c_ops = {
 746         .xfer           = designware_i2c_xfer,
 747         .probe_chip     = designware_i2c_probe_chip,
 748         .set_bus_speed  = designware_i2c_set_bus_speed,
 749 };
 750
 751 static const struct udevice_id designware_i2c_ids[] = {
 752         { .compatible = "snps,designware-i2c" },
 753         { }
 754 };
 755
 756 U_BOOT_DRIVER(i2c_designware) = {
 757         .name   = "i2c_designware",
 758         .id     = UCLASS_I2C,
 759         .of_match = designware_i2c_ids,
 760         .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
 761         .probe  = designware_i2c_probe,
 762         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 763         .remove = designware_i2c_remove,
 764         .flags  = DM_FLAG_OS_PREPARE,
 765         .ops    = &designware_i2c_ops,
 766 };
 767
 768 #endif /* CONFIG_DM_I2C */