2 * Wondermedia I2C Master Mode Driver
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 * Derived from GPLv2+ licensed source:
7 * - Copyright (C) 2008 WonderMedia Technologies, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2, or
11 * (at your option) any later version. as published by the Free Software
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
21 #include <linux/module.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/platform_device.h>
35 #define REG_SLAVE_CR 0x10
36 #define REG_SLAVE_SR 0x12
37 #define REG_SLAVE_ISR 0x14
38 #define REG_SLAVE_IMR 0x16
39 #define REG_SLAVE_DR 0x18
40 #define REG_SLAVE_TR 0x1A
42 /* REG_CR Bit fields */
43 #define CR_TX_NEXT_ACK 0x0000
44 #define CR_ENABLE 0x0001
45 #define CR_TX_NEXT_NO_ACK 0x0002
46 #define CR_TX_END 0x0004
47 #define CR_CPU_RDY 0x0008
48 #define SLAV_MODE_SEL 0x8000
50 /* REG_TCR Bit fields */
51 #define TCR_STANDARD_MODE 0x0000
52 #define TCR_MASTER_WRITE 0x0000
53 #define TCR_HS_MODE 0x2000
54 #define TCR_MASTER_READ 0x4000
55 #define TCR_FAST_MODE 0x8000
56 #define TCR_SLAVE_ADDR_MASK 0x007F
58 /* REG_ISR Bit fields */
59 #define ISR_NACK_ADDR 0x0001
60 #define ISR_BYTE_END 0x0002
61 #define ISR_SCL_TIMEOUT 0x0004
62 #define ISR_WRITE_ALL 0x0007
64 /* REG_IMR Bit fields */
65 #define IMR_ENABLE_ALL 0x0007
67 /* REG_CSR Bit fields */
68 #define CSR_RCV_NOT_ACK 0x0001
69 #define CSR_RCV_ACK_MASK 0x0001
70 #define CSR_READY_MASK 0x0002
73 #define SCL_TIMEOUT(x) (((x) & 0xFF) << 8)
79 #define MCR_APB_166M 12
81 #define I2C_MODE_STANDARD 0
82 #define I2C_MODE_FAST 1
84 #define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000))
87 struct i2c_adapter adapter;
88 struct completion complete;
97 static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
99 unsigned long timeout;
101 timeout = jiffies + WMT_I2C_TIMEOUT;
102 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
103 if (time_after(jiffies, timeout)) {
104 dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
113 static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
117 if (i2c_dev->cmd_status & ISR_NACK_ADDR)
120 if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
126 static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
129 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
131 int ret, wait_result;
134 if (!(pmsg->flags & I2C_M_NOSTART)) {
135 ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
140 if (pmsg->len == 0) {
142 * We still need to run through the while (..) once, so
143 * start at -1 and break out early from the loop
146 writew(0, i2c_dev->base + REG_CDR);
148 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
151 if (!(pmsg->flags & I2C_M_NOSTART)) {
152 val = readw(i2c_dev->base + REG_CR);
154 writew(val, i2c_dev->base + REG_CR);
156 val = readw(i2c_dev->base + REG_CR);
158 writew(val, i2c_dev->base + REG_CR);
161 INIT_COMPLETION(i2c_dev->complete);
163 if (i2c_dev->mode == I2C_MODE_STANDARD)
164 tcr_val = TCR_STANDARD_MODE;
166 tcr_val = TCR_FAST_MODE;
168 tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
170 writew(tcr_val, i2c_dev->base + REG_TCR);
172 if (pmsg->flags & I2C_M_NOSTART) {
173 val = readw(i2c_dev->base + REG_CR);
175 writew(val, i2c_dev->base + REG_CR);
178 while (xfer_len < pmsg->len) {
179 wait_result = wait_for_completion_timeout(&i2c_dev->complete,
182 if (wait_result == 0)
185 ret = wmt_check_status(i2c_dev);
191 val = readw(i2c_dev->base + REG_CSR);
192 if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
193 dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
197 if (pmsg->len == 0) {
198 val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
199 writew(val, i2c_dev->base + REG_CR);
203 if (xfer_len == pmsg->len) {
205 writew(CR_ENABLE, i2c_dev->base + REG_CR);
207 writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
209 writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
216 static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
219 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
221 int ret, wait_result;
224 if (!(pmsg->flags & I2C_M_NOSTART)) {
225 ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
230 val = readw(i2c_dev->base + REG_CR);
232 writew(val, i2c_dev->base + REG_CR);
234 val = readw(i2c_dev->base + REG_CR);
235 val &= ~CR_TX_NEXT_NO_ACK;
236 writew(val, i2c_dev->base + REG_CR);
238 if (!(pmsg->flags & I2C_M_NOSTART)) {
239 val = readw(i2c_dev->base + REG_CR);
241 writew(val, i2c_dev->base + REG_CR);
244 if (pmsg->len == 1) {
245 val = readw(i2c_dev->base + REG_CR);
246 val |= CR_TX_NEXT_NO_ACK;
247 writew(val, i2c_dev->base + REG_CR);
250 INIT_COMPLETION(i2c_dev->complete);
252 if (i2c_dev->mode == I2C_MODE_STANDARD)
253 tcr_val = TCR_STANDARD_MODE;
255 tcr_val = TCR_FAST_MODE;
257 tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
259 writew(tcr_val, i2c_dev->base + REG_TCR);
261 if (pmsg->flags & I2C_M_NOSTART) {
262 val = readw(i2c_dev->base + REG_CR);
264 writew(val, i2c_dev->base + REG_CR);
267 while (xfer_len < pmsg->len) {
268 wait_result = wait_for_completion_timeout(&i2c_dev->complete,
274 ret = wmt_check_status(i2c_dev);
278 pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
281 if (xfer_len == pmsg->len - 1) {
282 val = readw(i2c_dev->base + REG_CR);
283 val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
284 writew(val, i2c_dev->base + REG_CR);
286 val = readw(i2c_dev->base + REG_CR);
288 writew(val, i2c_dev->base + REG_CR);
295 static int wmt_i2c_xfer(struct i2c_adapter *adap,
296 struct i2c_msg msgs[],
299 struct i2c_msg *pmsg;
303 for (i = 0; ret >= 0 && i < num; i++) {
304 is_last = ((i + 1) == num);
307 if (pmsg->flags & I2C_M_RD)
308 ret = wmt_i2c_read(adap, pmsg, is_last);
310 ret = wmt_i2c_write(adap, pmsg, is_last);
313 return (ret < 0) ? ret : i;
316 static u32 wmt_i2c_func(struct i2c_adapter *adap)
318 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
321 static const struct i2c_algorithm wmt_i2c_algo = {
322 .master_xfer = wmt_i2c_xfer,
323 .functionality = wmt_i2c_func,
326 static irqreturn_t wmt_i2c_isr(int irq, void *data)
328 struct wmt_i2c_dev *i2c_dev = data;
330 /* save the status and write-clear it */
331 i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
332 writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
334 complete(&i2c_dev->complete);
339 static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
343 err = clk_prepare_enable(i2c_dev->clk);
345 dev_err(i2c_dev->dev, "failed to enable clock\n");
349 err = clk_set_rate(i2c_dev->clk, 20000000);
351 dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
352 clk_disable_unprepare(i2c_dev->clk);
356 writew(0, i2c_dev->base + REG_CR);
357 writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
358 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
359 writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
360 writew(CR_ENABLE, i2c_dev->base + REG_CR);
361 readw(i2c_dev->base + REG_CSR); /* read clear */
362 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
364 if (i2c_dev->mode == I2C_MODE_STANDARD)
365 writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
367 writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);
372 static int wmt_i2c_probe(struct platform_device *pdev)
374 struct device_node *np = pdev->dev.of_node;
375 struct wmt_i2c_dev *i2c_dev;
376 struct i2c_adapter *adap;
377 struct resource *res;
381 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
383 dev_err(&pdev->dev, "device memory allocation failed\n");
387 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
388 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
389 if (IS_ERR(i2c_dev->base))
390 return PTR_ERR(i2c_dev->base);
392 i2c_dev->irq = irq_of_parse_and_map(np, 0);
394 dev_err(&pdev->dev, "irq missing or invalid\n");
398 i2c_dev->clk = of_clk_get(np, 0);
399 if (IS_ERR(i2c_dev->clk)) {
400 dev_err(&pdev->dev, "unable to request clock\n");
401 return PTR_ERR(i2c_dev->clk);
404 i2c_dev->mode = I2C_MODE_STANDARD;
405 err = of_property_read_u32(np, "clock-frequency", &clk_rate);
406 if ((!err) && (clk_rate == 400000))
407 i2c_dev->mode = I2C_MODE_FAST;
409 i2c_dev->dev = &pdev->dev;
411 err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
414 dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
418 adap = &i2c_dev->adapter;
419 i2c_set_adapdata(adap, i2c_dev);
420 strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
421 adap->owner = THIS_MODULE;
422 adap->algo = &wmt_i2c_algo;
423 adap->dev.parent = &pdev->dev;
424 adap->dev.of_node = pdev->dev.of_node;
426 init_completion(&i2c_dev->complete);
428 err = wmt_i2c_reset_hardware(i2c_dev);
430 dev_err(&pdev->dev, "error initializing hardware\n");
434 err = i2c_add_adapter(adap);
436 dev_err(&pdev->dev, "failed to add adapter\n");
440 platform_set_drvdata(pdev, i2c_dev);
445 static int wmt_i2c_remove(struct platform_device *pdev)
447 struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
449 /* Disable interrupts, clock and delete adapter */
450 writew(0, i2c_dev->base + REG_IMR);
451 clk_disable_unprepare(i2c_dev->clk);
452 i2c_del_adapter(&i2c_dev->adapter);
457 static struct of_device_id wmt_i2c_dt_ids[] = {
458 { .compatible = "wm,wm8505-i2c" },
462 static struct platform_driver wmt_i2c_driver = {
463 .probe = wmt_i2c_probe,
464 .remove = wmt_i2c_remove,
467 .owner = THIS_MODULE,
468 .of_match_table = wmt_i2c_dt_ids,
472 module_platform_driver(wmt_i2c_driver);
474 MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
475 MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
476 MODULE_LICENSE("GPL");
477 MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);