drivers/i2c/busses/i2c-stm32f7.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for STMicroelectronics STM32F7 I2C controller
   4  *
   5  * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
   6  * reference manual.
   7  * Please see below a link to the documentation:
   8  * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
   9  *
  10  * Copyright (C) M'boumba Cedric Madianga 2017
  11  * Copyright (C) STMicroelectronics 2017
  12  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
  13  *
  14  * This driver is based on i2c-stm32f4.c
  15  *
  16  */
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/reset.h>
  31 #include <linux/slab.h>
  32
  33 #include "i2c-stm32.h"
  34
  35 /* STM32F7 I2C registers */
  36 #define STM32F7_I2C_CR1                         0x00
  37 #define STM32F7_I2C_CR2                         0x04
  38 #define STM32F7_I2C_OAR1                        0x08
  39 #define STM32F7_I2C_OAR2                        0x0C
  40 #define STM32F7_I2C_PECR                        0x20
  41 #define STM32F7_I2C_TIMINGR                     0x10
  42 #define STM32F7_I2C_ISR                         0x18
  43 #define STM32F7_I2C_ICR                         0x1C
  44 #define STM32F7_I2C_RXDR                        0x24
  45 #define STM32F7_I2C_TXDR                        0x28
  46
  47 /* STM32F7 I2C control 1 */
  48 #define STM32F7_I2C_CR1_PECEN                   BIT(23)
  49 #define STM32F7_I2C_CR1_SBC                     BIT(16)
  50 #define STM32F7_I2C_CR1_RXDMAEN                 BIT(15)
  51 #define STM32F7_I2C_CR1_TXDMAEN                 BIT(14)
  52 #define STM32F7_I2C_CR1_ANFOFF                  BIT(12)
  53 #define STM32F7_I2C_CR1_ERRIE                   BIT(7)
  54 #define STM32F7_I2C_CR1_TCIE                    BIT(6)
  55 #define STM32F7_I2C_CR1_STOPIE                  BIT(5)
  56 #define STM32F7_I2C_CR1_NACKIE                  BIT(4)
  57 #define STM32F7_I2C_CR1_ADDRIE                  BIT(3)
  58 #define STM32F7_I2C_CR1_RXIE                    BIT(2)
  59 #define STM32F7_I2C_CR1_TXIE                    BIT(1)
  60 #define STM32F7_I2C_CR1_PE                      BIT(0)
  61 #define STM32F7_I2C_ALL_IRQ_MASK                (STM32F7_I2C_CR1_ERRIE \
  62                                                 | STM32F7_I2C_CR1_TCIE \
  63                                                 | STM32F7_I2C_CR1_STOPIE \
  64                                                 | STM32F7_I2C_CR1_NACKIE \
  65                                                 | STM32F7_I2C_CR1_RXIE \
  66                                                 | STM32F7_I2C_CR1_TXIE)
  67 #define STM32F7_I2C_XFER_IRQ_MASK               (STM32F7_I2C_CR1_TCIE \
  68                                                 | STM32F7_I2C_CR1_STOPIE \
  69                                                 | STM32F7_I2C_CR1_NACKIE \
  70                                                 | STM32F7_I2C_CR1_RXIE \
  71                                                 | STM32F7_I2C_CR1_TXIE)
  72
  73 /* STM32F7 I2C control 2 */
  74 #define STM32F7_I2C_CR2_PECBYTE                 BIT(26)
  75 #define STM32F7_I2C_CR2_RELOAD                  BIT(24)
  76 #define STM32F7_I2C_CR2_NBYTES_MASK             GENMASK(23, 16)
  77 #define STM32F7_I2C_CR2_NBYTES(n)               (((n) & 0xff) << 16)
  78 #define STM32F7_I2C_CR2_NACK                    BIT(15)
  79 #define STM32F7_I2C_CR2_STOP                    BIT(14)
  80 #define STM32F7_I2C_CR2_START                   BIT(13)
  81 #define STM32F7_I2C_CR2_HEAD10R                 BIT(12)
  82 #define STM32F7_I2C_CR2_ADD10                   BIT(11)
  83 #define STM32F7_I2C_CR2_RD_WRN                  BIT(10)
  84 #define STM32F7_I2C_CR2_SADD10_MASK             GENMASK(9, 0)
  85 #define STM32F7_I2C_CR2_SADD10(n)               (((n) & \
  86                                                 STM32F7_I2C_CR2_SADD10_MASK))
  87 #define STM32F7_I2C_CR2_SADD7_MASK              GENMASK(7, 1)
  88 #define STM32F7_I2C_CR2_SADD7(n)                (((n) & 0x7f) << 1)
  89
  90 /* STM32F7 I2C Own Address 1 */
  91 #define STM32F7_I2C_OAR1_OA1EN                  BIT(15)
  92 #define STM32F7_I2C_OAR1_OA1MODE                BIT(10)
  93 #define STM32F7_I2C_OAR1_OA1_10_MASK            GENMASK(9, 0)
  94 #define STM32F7_I2C_OAR1_OA1_10(n)              (((n) & \
  95                                                 STM32F7_I2C_OAR1_OA1_10_MASK))
  96 #define STM32F7_I2C_OAR1_OA1_7_MASK             GENMASK(7, 1)
  97 #define STM32F7_I2C_OAR1_OA1_7(n)               (((n) & 0x7f) << 1)
  98 #define STM32F7_I2C_OAR1_MASK                   (STM32F7_I2C_OAR1_OA1_7_MASK \
  99                                                 | STM32F7_I2C_OAR1_OA1_10_MASK \
 100                                                 | STM32F7_I2C_OAR1_OA1EN \
 101                                                 | STM32F7_I2C_OAR1_OA1MODE)
 102
 103 /* STM32F7 I2C Own Address 2 */
 104 #define STM32F7_I2C_OAR2_OA2EN                  BIT(15)
 105 #define STM32F7_I2C_OAR2_OA2MSK_MASK            GENMASK(10, 8)
 106 #define STM32F7_I2C_OAR2_OA2MSK(n)              (((n) & 0x7) << 8)
 107 #define STM32F7_I2C_OAR2_OA2_7_MASK             GENMASK(7, 1)
 108 #define STM32F7_I2C_OAR2_OA2_7(n)               (((n) & 0x7f) << 1)
 109 #define STM32F7_I2C_OAR2_MASK                   (STM32F7_I2C_OAR2_OA2MSK_MASK \
 110                                                 | STM32F7_I2C_OAR2_OA2_7_MASK \
 111                                                 | STM32F7_I2C_OAR2_OA2EN)
 112
 113 /* STM32F7 I2C Interrupt Status */
 114 #define STM32F7_I2C_ISR_ADDCODE_MASK            GENMASK(23, 17)
 115 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
 116                                 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
 117 #define STM32F7_I2C_ISR_DIR                     BIT(16)
 118 #define STM32F7_I2C_ISR_BUSY                    BIT(15)
 119 #define STM32F7_I2C_ISR_PECERR                  BIT(11)
 120 #define STM32F7_I2C_ISR_ARLO                    BIT(9)
 121 #define STM32F7_I2C_ISR_BERR                    BIT(8)
 122 #define STM32F7_I2C_ISR_TCR                     BIT(7)
 123 #define STM32F7_I2C_ISR_TC                      BIT(6)
 124 #define STM32F7_I2C_ISR_STOPF                   BIT(5)
 125 #define STM32F7_I2C_ISR_NACKF                   BIT(4)
 126 #define STM32F7_I2C_ISR_ADDR                    BIT(3)
 127 #define STM32F7_I2C_ISR_RXNE                    BIT(2)
 128 #define STM32F7_I2C_ISR_TXIS                    BIT(1)
 129 #define STM32F7_I2C_ISR_TXE                     BIT(0)
 130
 131 /* STM32F7 I2C Interrupt Clear */
 132 #define STM32F7_I2C_ICR_PECCF                   BIT(11)
 133 #define STM32F7_I2C_ICR_ARLOCF                  BIT(9)
 134 #define STM32F7_I2C_ICR_BERRCF                  BIT(8)
 135 #define STM32F7_I2C_ICR_STOPCF                  BIT(5)
 136 #define STM32F7_I2C_ICR_NACKCF                  BIT(4)
 137 #define STM32F7_I2C_ICR_ADDRCF                  BIT(3)
 138
 139 /* STM32F7 I2C Timing */
 140 #define STM32F7_I2C_TIMINGR_PRESC(n)            (((n) & 0xf) << 28)
 141 #define STM32F7_I2C_TIMINGR_SCLDEL(n)           (((n) & 0xf) << 20)
 142 #define STM32F7_I2C_TIMINGR_SDADEL(n)           (((n) & 0xf) << 16)
 143 #define STM32F7_I2C_TIMINGR_SCLH(n)             (((n) & 0xff) << 8)
 144 #define STM32F7_I2C_TIMINGR_SCLL(n)             ((n) & 0xff)
 145
 146 #define STM32F7_I2C_MAX_LEN                     0xff
 147 #define STM32F7_I2C_DMA_LEN_MIN                 0x16
 148 #define STM32F7_I2C_MAX_SLAVE                   0x2
 149
 150 #define STM32F7_I2C_DNF_DEFAULT                 0
 151 #define STM32F7_I2C_DNF_MAX                     16
 152
 153 #define STM32F7_I2C_ANALOG_FILTER_ENABLE        1
 154 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN     50      /* ns */
 155 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX     260     /* ns */
 156
 157 #define STM32F7_I2C_RISE_TIME_DEFAULT           25      /* ns */
 158 #define STM32F7_I2C_FALL_TIME_DEFAULT           10      /* ns */
 159
 160 #define STM32F7_PRESC_MAX                       BIT(4)
 161 #define STM32F7_SCLDEL_MAX                      BIT(4)
 162 #define STM32F7_SDADEL_MAX                      BIT(4)
 163 #define STM32F7_SCLH_MAX                        BIT(8)
 164 #define STM32F7_SCLL_MAX                        BIT(8)
 165
 166 /**
 167  * struct stm32f7_i2c_spec - private i2c specification timing
 168  * @rate: I2C bus speed (Hz)
 169  * @rate_min: 80% of I2C bus speed (Hz)
 170  * @rate_max: 100% of I2C bus speed (Hz)
 171  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 172  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 173  * @hddat_min: Min data hold time (ns)
 174  * @vddat_max: Max data valid time (ns)
 175  * @sudat_min: Min data setup time (ns)
 176  * @l_min: Min low period of the SCL clock (ns)
 177  * @h_min: Min high period of the SCL clock (ns)
 178  */
 179 struct stm32f7_i2c_spec {
 180         u32 rate;
 181         u32 rate_min;
 182         u32 rate_max;
 183         u32 fall_max;
 184         u32 rise_max;
 185         u32 hddat_min;
 186         u32 vddat_max;
 187         u32 sudat_min;
 188         u32 l_min;
 189         u32 h_min;
 190 };
 191
 192 /**
 193  * struct stm32f7_i2c_setup - private I2C timing setup parameters
 194  * @speed: I2C speed mode (standard, Fast Plus)
 195  * @speed_freq: I2C speed frequency  (Hz)
 196  * @clock_src: I2C clock source frequency (Hz)
 197  * @rise_time: Rise time (ns)
 198  * @fall_time: Fall time (ns)
 199  * @dnf: Digital filter coefficient (0-16)
 200  * @analog_filter: Analog filter delay (On/Off)
 201  */
 202 struct stm32f7_i2c_setup {
 203         enum stm32_i2c_speed speed;
 204         u32 speed_freq;
 205         u32 clock_src;
 206         u32 rise_time;
 207         u32 fall_time;
 208         u8 dnf;
 209         bool analog_filter;
 210 };
 211
 212 /**
 213  * struct stm32f7_i2c_timings - private I2C output parameters
 214  * @node: List entry
 215  * @presc: Prescaler value
 216  * @scldel: Data setup time
 217  * @sdadel: Data hold time
 218  * @sclh: SCL high period (master mode)
 219  * @scll: SCL low period (master mode)
 220  */
 221 struct stm32f7_i2c_timings {
 222         struct list_head node;
 223         u8 presc;
 224         u8 scldel;
 225         u8 sdadel;
 226         u8 sclh;
 227         u8 scll;
 228 };
 229
 230 /**
 231  * struct stm32f7_i2c_msg - client specific data
 232  * @addr: 8-bit or 10-bit slave addr, including r/w bit
 233  * @count: number of bytes to be transferred
 234  * @buf: data buffer
 235  * @result: result of the transfer
 236  * @stop: last I2C msg to be sent, i.e. STOP to be generated
 237  * @smbus: boolean to know if the I2C IP is used in SMBus mode
 238  * @size: type of SMBus protocol
 239  * @read_write: direction of SMBus protocol
 240  * SMBus block read and SMBus block write - block read process call protocols
 241  * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
 242  * contain a maximum of 32 bytes of data + byte command + byte count + PEC
 243  * This buffer has to be 32-bit aligned to be compliant with memory address
 244  * register in DMA mode.
 245  */
 246 struct stm32f7_i2c_msg {
 247         u16 addr;
 248         u32 count;
 249         u8 *buf;
 250         int result;
 251         bool stop;
 252         bool smbus;
 253         int size;
 254         char read_write;
 255         u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
 256 };
 257
 258 /**
 259  * struct stm32f7_i2c_dev - private data of the controller
 260  * @adap: I2C adapter for this controller
 261  * @dev: device for this controller
 262  * @base: virtual memory area
 263  * @complete: completion of I2C message
 264  * @clk: hw i2c clock
 265  * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
 266  * @msg: Pointer to data to be written
 267  * @msg_num: number of I2C messages to be executed
 268  * @msg_id: message identifiant
 269  * @f7_msg: customized i2c msg for driver usage
 270  * @setup: I2C timing input setup
 271  * @timing: I2C computed timings
 272  * @slave: list of slave devices registered on the I2C bus
 273  * @slave_running: slave device currently used
 274  * @slave_dir: transfer direction for the current slave device
 275  * @master_mode: boolean to know in which mode the I2C is running (master or
 276  * slave)
 277  * @dma: dma data
 278  * @use_dma: boolean to know if dma is used in the current transfer
 279  */
 280 struct stm32f7_i2c_dev {
 281         struct i2c_adapter adap;
 282         struct device *dev;
 283         void __iomem *base;
 284         struct completion complete;
 285         struct clk *clk;
 286         int speed;
 287         struct i2c_msg *msg;
 288         unsigned int msg_num;
 289         unsigned int msg_id;
 290         struct stm32f7_i2c_msg f7_msg;
 291         struct stm32f7_i2c_setup setup;
 292         struct stm32f7_i2c_timings timing;
 293         struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
 294         struct i2c_client *slave_running;
 295         u32 slave_dir;
 296         bool master_mode;
 297         struct stm32_i2c_dma *dma;
 298         bool use_dma;
 299 };
 300
 301 /**
 302  * All these values are coming from I2C Specification, Version 6.0, 4th of
 303  * April 2014.
 304  *
 305  * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
 306  * and Fast-mode Plus I2C-bus devices
 307  */
 308 static struct stm32f7_i2c_spec i2c_specs[] = {
 309         [STM32_I2C_SPEED_STANDARD] = {
 310                 .rate = 100000,
 311                 .rate_min = 80000,
 312                 .rate_max = 100000,
 313                 .fall_max = 300,
 314                 .rise_max = 1000,
 315                 .hddat_min = 0,
 316                 .vddat_max = 3450,
 317                 .sudat_min = 250,
 318                 .l_min = 4700,
 319                 .h_min = 4000,
 320         },
 321         [STM32_I2C_SPEED_FAST] = {
 322                 .rate = 400000,
 323                 .rate_min = 320000,
 324                 .rate_max = 400000,
 325                 .fall_max = 300,
 326                 .rise_max = 300,
 327                 .hddat_min = 0,
 328                 .vddat_max = 900,
 329                 .sudat_min = 100,
 330                 .l_min = 1300,
 331                 .h_min = 600,
 332         },
 333         [STM32_I2C_SPEED_FAST_PLUS] = {
 334                 .rate = 1000000,
 335                 .rate_min = 800000,
 336                 .rate_max = 1000000,
 337                 .fall_max = 100,
 338                 .rise_max = 120,
 339                 .hddat_min = 0,
 340                 .vddat_max = 450,
 341                 .sudat_min = 50,
 342                 .l_min = 500,
 343                 .h_min = 260,
 344         },
 345 };
 346
 347 static const struct stm32f7_i2c_setup stm32f7_setup = {
 348         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 349         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 350         .dnf = STM32F7_I2C_DNF_DEFAULT,
 351         .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
 352 };
 353
 354 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
 355 {
 356         writel_relaxed(readl_relaxed(reg) | mask, reg);
 357 }
 358
 359 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
 360 {
 361         writel_relaxed(readl_relaxed(reg) & ~mask, reg);
 362 }
 363
 364 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
 365 {
 366         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
 367 }
 368
 369 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
 370                                       struct stm32f7_i2c_setup *setup,
 371                                       struct stm32f7_i2c_timings *output)
 372 {
 373         u32 p_prev = STM32F7_PRESC_MAX;
 374         u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 375                                        setup->clock_src);
 376         u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 377                                        setup->speed_freq);
 378         u32 clk_error_prev = i2cbus;
 379         u32 tsync;
 380         u32 af_delay_min, af_delay_max;
 381         u32 dnf_delay;
 382         u32 clk_min, clk_max;
 383         int sdadel_min, sdadel_max;
 384         int scldel_min;
 385         struct stm32f7_i2c_timings *v, *_v, *s;
 386         struct list_head solutions;
 387         u16 p, l, a, h;
 388         int ret = 0;
 389
 390         if (setup->speed >= STM32_I2C_SPEED_END) {
 391                 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
 392                         setup->speed, STM32_I2C_SPEED_END - 1);
 393                 return -EINVAL;
 394         }
 395
 396         if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
 397             (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
 398                 dev_err(i2c_dev->dev,
 399                         "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 400                         setup->rise_time, i2c_specs[setup->speed].rise_max,
 401                         setup->fall_time, i2c_specs[setup->speed].fall_max);
 402                 return -EINVAL;
 403         }
 404
 405         if (setup->dnf > STM32F7_I2C_DNF_MAX) {
 406                 dev_err(i2c_dev->dev,
 407                         "DNF out of bound %d/%d\n",
 408                         setup->dnf, STM32F7_I2C_DNF_MAX);
 409                 return -EINVAL;
 410         }
 411
 412         if (setup->speed_freq > i2c_specs[setup->speed].rate) {
 413                 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
 414                         setup->speed_freq, i2c_specs[setup->speed].rate);
 415                 return -EINVAL;
 416         }
 417
 418         /*  Analog and Digital Filters */
 419         af_delay_min =
 420                 (setup->analog_filter ?
 421                  STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
 422         af_delay_max =
 423                 (setup->analog_filter ?
 424                  STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
 425         dnf_delay = setup->dnf * i2cclk;
 426
 427         sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
 428                 af_delay_min - (setup->dnf + 3) * i2cclk;
 429
 430         sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
 431                 af_delay_max - (setup->dnf + 4) * i2cclk;
 432
 433         scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
 434
 435         if (sdadel_min < 0)
 436                 sdadel_min = 0;
 437         if (sdadel_max < 0)
 438                 sdadel_max = 0;
 439
 440         dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 441                 sdadel_min, sdadel_max, scldel_min);
 442
 443         INIT_LIST_HEAD(&solutions);
 444         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 445         for (p = 0; p < STM32F7_PRESC_MAX; p++) {
 446                 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
 447                         u32 scldel = (l + 1) * (p + 1) * i2cclk;
 448
 449                         if (scldel < scldel_min)
 450                                 continue;
 451
 452                         for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
 453                                 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
 454
 455                                 if (((sdadel >= sdadel_min) &&
 456                                      (sdadel <= sdadel_max)) &&
 457                                     (p != p_prev)) {
 458                                         v = kmalloc(sizeof(*v), GFP_KERNEL);
 459                                         if (!v) {
 460                                                 ret = -ENOMEM;
 461                                                 goto exit;
 462                                         }
 463
 464                                         v->presc = p;
 465                                         v->scldel = l;
 466                                         v->sdadel = a;
 467                                         p_prev = p;
 468
 469                                         list_add_tail(&v->node,
 470                                                       &solutions);
 471                                 }
 472                         }
 473                 }
 474         }
 475
 476         if (list_empty(&solutions)) {
 477                 dev_err(i2c_dev->dev, "no Prescaler solution\n");
 478                 ret = -EPERM;
 479                 goto exit;
 480         }
 481
 482         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 483         s = NULL;
 484         clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
 485         clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
 486
 487         /*
 488          * Among Prescaler possibilities discovered above figures out SCL Low
 489          * and High Period. Provided:
 490          * - SCL Low Period has to be higher than SCL Clock Low Period
 491          *   defined by I2C Specification. I2C Clock has to be lower than
 492          *   (SCL Low Period - Analog/Digital filters) / 4.
 493          * - SCL High Period has to be lower than SCL Clock High Period
 494          *   defined by I2C Specification
 495          * - I2C Clock has to be lower than SCL High Period
 496          */
 497         list_for_each_entry(v, &solutions, node) {
 498                 u32 prescaler = (v->presc + 1) * i2cclk;
 499
 500                 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
 501                         u32 tscl_l = (l + 1) * prescaler + tsync;
 502
 503                         if ((tscl_l < i2c_specs[setup->speed].l_min) ||
 504                             (i2cclk >=
 505                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 506                                 continue;
 507                         }
 508
 509                         for (h = 0; h < STM32F7_SCLH_MAX; h++) {
 510                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 511                                 u32 tscl = tscl_l + tscl_h +
 512                                         setup->rise_time + setup->fall_time;
 513
 514                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 515                                     (tscl_h >= i2c_specs[setup->speed].h_min) &&
 516                                     (i2cclk < tscl_h)) {
 517                                         int clk_error = tscl - i2cbus;
 518
 519                                         if (clk_error < 0)
 520                                                 clk_error = -clk_error;
 521
 522                                         if (clk_error < clk_error_prev) {
 523                                                 clk_error_prev = clk_error;
 524                                                 v->scll = l;
 525                                                 v->sclh = h;
 526                                                 s = v;
 527                                         }
 528                                 }
 529                         }
 530                 }
 531         }
 532
 533         if (!s) {
 534                 dev_err(i2c_dev->dev, "no solution at all\n");
 535                 ret = -EPERM;
 536                 goto exit;
 537         }
 538
 539         output->presc = s->presc;
 540         output->scldel = s->scldel;
 541         output->sdadel = s->sdadel;
 542         output->scll = s->scll;
 543         output->sclh = s->sclh;
 544
 545         dev_dbg(i2c_dev->dev,
 546                 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 547                 output->presc,
 548                 output->scldel, output->sdadel,
 549                 output->scll, output->sclh);
 550
 551 exit:
 552         /* Release list and memory */
 553         list_for_each_entry_safe(v, _v, &solutions, node) {
 554                 list_del(&v->node);
 555                 kfree(v);
 556         }
 557
 558         return ret;
 559 }
 560
 561 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
 562                                     struct stm32f7_i2c_setup *setup)
 563 {
 564         int ret = 0;
 565
 566         setup->speed = i2c_dev->speed;
 567         setup->speed_freq = i2c_specs[setup->speed].rate;
 568         setup->clock_src = clk_get_rate(i2c_dev->clk);
 569
 570         if (!setup->clock_src) {
 571                 dev_err(i2c_dev->dev, "clock rate is 0\n");
 572                 return -EINVAL;
 573         }
 574
 575         do {
 576                 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
 577                                                  &i2c_dev->timing);
 578                 if (ret) {
 579                         dev_err(i2c_dev->dev,
 580                                 "failed to compute I2C timings.\n");
 581                         if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
 582                                 i2c_dev->speed--;
 583                                 setup->speed = i2c_dev->speed;
 584                                 setup->speed_freq =
 585                                         i2c_specs[setup->speed].rate;
 586                                 dev_warn(i2c_dev->dev,
 587                                          "downgrade I2C Speed Freq to (%i)\n",
 588                                          i2c_specs[setup->speed].rate);
 589                         } else {
 590                                 break;
 591                         }
 592                 }
 593         } while (ret);
 594
 595         if (ret) {
 596                 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
 597                 return ret;
 598         }
 599
 600         dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
 601                 setup->speed, setup->speed_freq, setup->clock_src);
 602         dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
 603                 setup->rise_time, setup->fall_time);
 604         dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
 605                 (setup->analog_filter ? "On" : "Off"), setup->dnf);
 606
 607         return 0;
 608 }
 609
 610 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
 611 {
 612         void __iomem *base = i2c_dev->base;
 613         u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
 614
 615         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
 616 }
 617
 618 static void stm32f7_i2c_dma_callback(void *arg)
 619 {
 620         struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
 621         struct stm32_i2c_dma *dma = i2c_dev->dma;
 622         struct device *dev = dma->chan_using->device->dev;
 623
 624         stm32f7_i2c_disable_dma_req(i2c_dev);
 625         dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
 626         complete(&dma->dma_complete);
 627 }
 628
 629 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
 630 {
 631         struct stm32f7_i2c_timings *t = &i2c_dev->timing;
 632         u32 timing = 0;
 633
 634         /* Timing settings */
 635         timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
 636         timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
 637         timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
 638         timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
 639         timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
 640         writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
 641
 642         /* Enable I2C */
 643         if (i2c_dev->setup.analog_filter)
 644                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 645                                      STM32F7_I2C_CR1_ANFOFF);
 646         else
 647                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 648                                      STM32F7_I2C_CR1_ANFOFF);
 649         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 650                              STM32F7_I2C_CR1_PE);
 651 }
 652
 653 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
 654 {
 655         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 656         void __iomem *base = i2c_dev->base;
 657
 658         if (f7_msg->count) {
 659                 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
 660                 f7_msg->count--;
 661         }
 662 }
 663
 664 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
 665 {
 666         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 667         void __iomem *base = i2c_dev->base;
 668
 669         if (f7_msg->count) {
 670                 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
 671                 f7_msg->count--;
 672         } else {
 673                 /* Flush RX buffer has no data is expected */
 674                 readb_relaxed(base + STM32F7_I2C_RXDR);
 675         }
 676 }
 677
 678 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
 679 {
 680         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 681         u32 cr2;
 682
 683         if (i2c_dev->use_dma)
 684                 f7_msg->count -= STM32F7_I2C_MAX_LEN;
 685
 686         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 687
 688         cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
 689         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 690                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 691         } else {
 692                 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
 693                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 694         }
 695
 696         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 697 }
 698
 699 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
 700 {
 701         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 702         u32 cr2;
 703         u8 *val;
 704
 705         /*
 706          * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
 707          * data received inform us how many data will follow.
 708          */
 709         stm32f7_i2c_read_rx_data(i2c_dev);
 710
 711         /*
 712          * Update NBYTES with the value read to continue the transfer
 713          */
 714         val = f7_msg->buf - sizeof(u8);
 715         f7_msg->count = *val;
 716         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 717         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 718         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 719         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 720 }
 721
 722 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
 723 {
 724         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 725
 726         dev_info(i2c_dev->dev, "Trying to recover bus\n");
 727
 728         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 729                              STM32F7_I2C_CR1_PE);
 730
 731         stm32f7_i2c_hw_config(i2c_dev);
 732
 733         return 0;
 734 }
 735
 736 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
 737 {
 738         u32 status;
 739         int ret;
 740
 741         ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
 742                                          status,
 743                                          !(status & STM32F7_I2C_ISR_BUSY),
 744                                          10, 1000);
 745         if (!ret)
 746                 return 0;
 747
 748         dev_info(i2c_dev->dev, "bus busy\n");
 749
 750         ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
 751         if (ret) {
 752                 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
 753                 return ret;
 754         }
 755
 756         return -EBUSY;
 757 }
 758
 759 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 760                                  struct i2c_msg *msg)
 761 {
 762         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 763         void __iomem *base = i2c_dev->base;
 764         u32 cr1, cr2;
 765         int ret;
 766
 767         f7_msg->addr = msg->addr;
 768         f7_msg->buf = msg->buf;
 769         f7_msg->count = msg->len;
 770         f7_msg->result = 0;
 771         f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
 772
 773         reinit_completion(&i2c_dev->complete);
 774
 775         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 776         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 777
 778         /* Set transfer direction */
 779         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 780         if (msg->flags & I2C_M_RD)
 781                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 782
 783         /* Set slave address */
 784         cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
 785         if (msg->flags & I2C_M_TEN) {
 786                 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
 787                 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
 788                 cr2 |= STM32F7_I2C_CR2_ADD10;
 789         } else {
 790                 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
 791                 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 792         }
 793
 794         /* Set nb bytes to transfer and reload if needed */
 795         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 796         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 797                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 798                 cr2 |= STM32F7_I2C_CR2_RELOAD;
 799         } else {
 800                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 801         }
 802
 803         /* Enable NACK, STOP, error and transfer complete interrupts */
 804         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 805                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 806
 807         /* Clear DMA req and TX/RX interrupt */
 808         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 809                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 810
 811         /* Configure DMA or enable RX/TX interrupt */
 812         i2c_dev->use_dma = false;
 813         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
 814                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 815                                               msg->flags & I2C_M_RD,
 816                                               f7_msg->count, f7_msg->buf,
 817                                               stm32f7_i2c_dma_callback,
 818                                               i2c_dev);
 819                 if (!ret)
 820                         i2c_dev->use_dma = true;
 821                 else
 822                         dev_warn(i2c_dev->dev, "can't use DMA\n");
 823         }
 824
 825         if (!i2c_dev->use_dma) {
 826                 if (msg->flags & I2C_M_RD)
 827                         cr1 |= STM32F7_I2C_CR1_RXIE;
 828                 else
 829                         cr1 |= STM32F7_I2C_CR1_TXIE;
 830         } else {
 831                 if (msg->flags & I2C_M_RD)
 832                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
 833                 else
 834                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
 835         }
 836
 837         /* Configure Start/Repeated Start */
 838         cr2 |= STM32F7_I2C_CR2_START;
 839
 840         i2c_dev->master_mode = true;
 841
 842         /* Write configurations registers */
 843         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
 844         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
 845 }
 846
 847 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 848                                       unsigned short flags, u8 command,
 849                                       union i2c_smbus_data *data)
 850 {
 851         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 852         struct device *dev = i2c_dev->dev;
 853         void __iomem *base = i2c_dev->base;
 854         u32 cr1, cr2;
 855         int i, ret;
 856
 857         f7_msg->result = 0;
 858         reinit_completion(&i2c_dev->complete);
 859
 860         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 861         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 862
 863         /* Set transfer direction */
 864         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 865         if (f7_msg->read_write)
 866                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 867
 868         /* Set slave address */
 869         cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
 870         cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 871
 872         f7_msg->smbus_buf[0] = command;
 873         switch (f7_msg->size) {
 874         case I2C_SMBUS_QUICK:
 875                 f7_msg->stop = true;
 876                 f7_msg->count = 0;
 877                 break;
 878         case I2C_SMBUS_BYTE:
 879                 f7_msg->stop = true;
 880                 f7_msg->count = 1;
 881                 break;
 882         case I2C_SMBUS_BYTE_DATA:
 883                 if (f7_msg->read_write) {
 884                         f7_msg->stop = false;
 885                         f7_msg->count = 1;
 886                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 887                 } else {
 888                         f7_msg->stop = true;
 889                         f7_msg->count = 2;
 890                         f7_msg->smbus_buf[1] = data->byte;
 891                 }
 892                 break;
 893         case I2C_SMBUS_WORD_DATA:
 894                 if (f7_msg->read_write) {
 895                         f7_msg->stop = false;
 896                         f7_msg->count = 1;
 897                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 898                 } else {
 899                         f7_msg->stop = true;
 900                         f7_msg->count = 3;
 901                         f7_msg->smbus_buf[1] = data->word & 0xff;
 902                         f7_msg->smbus_buf[2] = data->word >> 8;
 903                 }
 904                 break;
 905         case I2C_SMBUS_BLOCK_DATA:
 906                 if (f7_msg->read_write) {
 907                         f7_msg->stop = false;
 908                         f7_msg->count = 1;
 909                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 910                 } else {
 911                         f7_msg->stop = true;
 912                         if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
 913                             !data->block[0]) {
 914                                 dev_err(dev, "Invalid block write size %d\n",
 915                                         data->block[0]);
 916                                 return -EINVAL;
 917                         }
 918                         f7_msg->count = data->block[0] + 2;
 919                         for (i = 1; i < f7_msg->count; i++)
 920                                 f7_msg->smbus_buf[i] = data->block[i - 1];
 921                 }
 922                 break;
 923         case I2C_SMBUS_PROC_CALL:
 924                 f7_msg->stop = false;
 925                 f7_msg->count = 3;
 926                 f7_msg->smbus_buf[1] = data->word & 0xff;
 927                 f7_msg->smbus_buf[2] = data->word >> 8;
 928                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 929                 f7_msg->read_write = I2C_SMBUS_READ;
 930                 break;
 931         case I2C_SMBUS_BLOCK_PROC_CALL:
 932                 f7_msg->stop = false;
 933                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
 934                         dev_err(dev, "Invalid block write size %d\n",
 935                                 data->block[0]);
 936                         return -EINVAL;
 937                 }
 938                 f7_msg->count = data->block[0] + 2;
 939                 for (i = 1; i < f7_msg->count; i++)
 940                         f7_msg->smbus_buf[i] = data->block[i - 1];
 941                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 942                 f7_msg->read_write = I2C_SMBUS_READ;
 943                 break;
 944         default:
 945                 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
 946                 return -EOPNOTSUPP;
 947         }
 948
 949         f7_msg->buf = f7_msg->smbus_buf;
 950
 951         /* Configure PEC */
 952         if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
 953                 cr1 |= STM32F7_I2C_CR1_PECEN;
 954                 cr2 |= STM32F7_I2C_CR2_PECBYTE;
 955                 if (!f7_msg->read_write)
 956                         f7_msg->count++;
 957         } else {
 958                 cr1 &= ~STM32F7_I2C_CR1_PECEN;
 959                 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
 960         }
 961
 962         /* Set number of bytes to be transferred */
 963         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 964         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 965
 966         /* Enable NACK, STOP, error and transfer complete interrupts */
 967         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 968                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 969
 970         /* Clear DMA req and TX/RX interrupt */
 971         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 972                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 973
 974         /* Configure DMA or enable RX/TX interrupt */
 975         i2c_dev->use_dma = false;
 976         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
 977                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 978                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
 979                                               f7_msg->count, f7_msg->buf,
 980                                               stm32f7_i2c_dma_callback,
 981                                               i2c_dev);
 982                 if (!ret)
 983                         i2c_dev->use_dma = true;
 984                 else
 985                         dev_warn(i2c_dev->dev, "can't use DMA\n");
 986         }
 987
 988         if (!i2c_dev->use_dma) {
 989                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
 990                         cr1 |= STM32F7_I2C_CR1_RXIE;
 991                 else
 992                         cr1 |= STM32F7_I2C_CR1_TXIE;
 993         } else {
 994                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
 995                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
 996                 else
 997                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
 998         }
 999
1000         /* Set Start bit */
1001         cr2 |= STM32F7_I2C_CR2_START;
1002
1003         i2c_dev->master_mode = true;
1004
1005         /* Write configurations registers */
1006         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1007         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1008
1009         return 0;
1010 }
1011
1012 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1013 {
1014         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1015         void __iomem *base = i2c_dev->base;
1016         u32 cr1, cr2;
1017         int ret;
1018
1019         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1020         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1021
1022         /* Set transfer direction */
1023         cr2 |= STM32F7_I2C_CR2_RD_WRN;
1024
1025         switch (f7_msg->size) {
1026         case I2C_SMBUS_BYTE_DATA:
1027                 f7_msg->count = 1;
1028                 break;
1029         case I2C_SMBUS_WORD_DATA:
1030         case I2C_SMBUS_PROC_CALL:
1031                 f7_msg->count = 2;
1032                 break;
1033         case I2C_SMBUS_BLOCK_DATA:
1034         case I2C_SMBUS_BLOCK_PROC_CALL:
1035                 f7_msg->count = 1;
1036                 cr2 |= STM32F7_I2C_CR2_RELOAD;
1037                 break;
1038         }
1039
1040         f7_msg->buf = f7_msg->smbus_buf;
1041         f7_msg->stop = true;
1042
1043         /* Add one byte for PEC if needed */
1044         if (cr1 & STM32F7_I2C_CR1_PECEN)
1045                 f7_msg->count++;
1046
1047         /* Set number of bytes to be transferred */
1048         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1049         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1050
1051         /*
1052          * Configure RX/TX interrupt:
1053          */
1054         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1055         cr1 |= STM32F7_I2C_CR1_RXIE;
1056
1057         /*
1058          * Configure DMA or enable RX/TX interrupt:
1059          * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1060          * dma as we don't know in advance how many data will be received
1061          */
1062         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1063                  STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1064
1065         i2c_dev->use_dma = false;
1066         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1067             f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1068             f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1069                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1070                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1071                                               f7_msg->count, f7_msg->buf,
1072                                               stm32f7_i2c_dma_callback,
1073                                               i2c_dev);
1074
1075                 if (!ret)
1076                         i2c_dev->use_dma = true;
1077                 else
1078                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1079         }
1080
1081         if (!i2c_dev->use_dma)
1082                 cr1 |= STM32F7_I2C_CR1_RXIE;
1083         else
1084                 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1085
1086         /* Configure Repeated Start */
1087         cr2 |= STM32F7_I2C_CR2_START;
1088
1089         /* Write configurations registers */
1090         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1091         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1092 }
1093
1094 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1095 {
1096         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1097         u8 count, internal_pec, received_pec;
1098
1099         internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1100
1101         switch (f7_msg->size) {
1102         case I2C_SMBUS_BYTE:
1103         case I2C_SMBUS_BYTE_DATA:
1104                 received_pec = f7_msg->smbus_buf[1];
1105                 break;
1106         case I2C_SMBUS_WORD_DATA:
1107         case I2C_SMBUS_PROC_CALL:
1108                 received_pec = f7_msg->smbus_buf[2];
1109                 break;
1110         case I2C_SMBUS_BLOCK_DATA:
1111         case I2C_SMBUS_BLOCK_PROC_CALL:
1112                 count = f7_msg->smbus_buf[0];
1113                 received_pec = f7_msg->smbus_buf[count];
1114                 break;
1115         default:
1116                 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1117                 return -EINVAL;
1118         }
1119
1120         if (internal_pec != received_pec) {
1121                 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1122                         internal_pec, received_pec);
1123                 return -EBADMSG;
1124         }
1125
1126         return 0;
1127 }
1128
1129 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1130 {
1131         u32 addr;
1132
1133         if (!slave)
1134                 return false;
1135
1136         if (slave->flags & I2C_CLIENT_TEN) {
1137                 /*
1138                  * For 10-bit addr, addcode = 11110XY with
1139                  * X = Bit 9 of slave address
1140                  * Y = Bit 8 of slave address
1141                  */
1142                 addr = slave->addr >> 8;
1143                 addr |= 0x78;
1144                 if (addr == addcode)
1145                         return true;
1146         } else {
1147                 addr = slave->addr & 0x7f;
1148                 if (addr == addcode)
1149                         return true;
1150         }
1151
1152         return false;
1153 }
1154
1155 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1156 {
1157         struct i2c_client *slave = i2c_dev->slave_running;
1158         void __iomem *base = i2c_dev->base;
1159         u32 mask;
1160         u8 value = 0;
1161
1162         if (i2c_dev->slave_dir) {
1163                 /* Notify i2c slave that new read transfer is starting */
1164                 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1165
1166                 /*
1167                  * Disable slave TX config in case of I2C combined message
1168                  * (I2C Write followed by I2C Read)
1169                  */
1170                 mask = STM32F7_I2C_CR2_RELOAD;
1171                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1172                 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1173                        STM32F7_I2C_CR1_TCIE;
1174                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1175
1176                 /* Enable TX empty, STOP, NACK interrupts */
1177                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1178                         STM32F7_I2C_CR1_TXIE;
1179                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1180
1181         } else {
1182                 /* Notify i2c slave that new write transfer is starting */
1183                 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1184
1185                 /* Set reload mode to be able to ACK/NACK each received byte */
1186                 mask = STM32F7_I2C_CR2_RELOAD;
1187                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1188
1189                 /*
1190                  * Set STOP, NACK, RX empty and transfer complete interrupts.*
1191                  * Set Slave Byte Control to be able to ACK/NACK each data
1192                  * byte received
1193                  */
1194                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1195                         STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1196                         STM32F7_I2C_CR1_TCIE;
1197                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1198         }
1199 }
1200
1201 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1202 {
1203         void __iomem *base = i2c_dev->base;
1204         u32 isr, addcode, dir, mask;
1205         int i;
1206
1207         isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1208         addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1209         dir = isr & STM32F7_I2C_ISR_DIR;
1210
1211         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1212                 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1213                         i2c_dev->slave_running = i2c_dev->slave[i];
1214                         i2c_dev->slave_dir = dir;
1215
1216                         /* Start I2C slave processing */
1217                         stm32f7_i2c_slave_start(i2c_dev);
1218
1219                         /* Clear ADDR flag */
1220                         mask = STM32F7_I2C_ICR_ADDRCF;
1221                         writel_relaxed(mask, base + STM32F7_I2C_ICR);
1222                         break;
1223                 }
1224         }
1225 }
1226
1227 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1228                                     struct i2c_client *slave, int *id)
1229 {
1230         int i;
1231
1232         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1233                 if (i2c_dev->slave[i] == slave) {
1234                         *id = i;
1235                         return 0;
1236                 }
1237         }
1238
1239         dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1240
1241         return -ENODEV;
1242 }
1243
1244 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1245                                          struct i2c_client *slave, int *id)
1246 {
1247         struct device *dev = i2c_dev->dev;
1248         int i;
1249
1250         /*
1251          * slave[0] supports 7-bit and 10-bit slave address
1252          * slave[1] supports 7-bit slave address only
1253          */
1254         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1255                 if (i == 1 && (slave->flags & I2C_CLIENT_PEC))
1256                         continue;
1257                 if (!i2c_dev->slave[i]) {
1258                         *id = i;
1259                         return 0;
1260                 }
1261         }
1262
1263         dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1264
1265         return -EINVAL;
1266 }
1267
1268 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1269 {
1270         int i;
1271
1272         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1273                 if (i2c_dev->slave[i])
1274                         return true;
1275         }
1276
1277         return false;
1278 }
1279
1280 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1281 {
1282         int i, busy;
1283
1284         busy = 0;
1285         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1286                 if (i2c_dev->slave[i])
1287                         busy++;
1288         }
1289
1290         return i == busy;
1291 }
1292
1293 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1294 {
1295         void __iomem *base = i2c_dev->base;
1296         u32 cr2, status, mask;
1297         u8 val;
1298         int ret;
1299
1300         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1301
1302         /* Slave transmitter mode */
1303         if (status & STM32F7_I2C_ISR_TXIS) {
1304                 i2c_slave_event(i2c_dev->slave_running,
1305                                 I2C_SLAVE_READ_PROCESSED,
1306                                 &val);
1307
1308                 /* Write data byte */
1309                 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1310         }
1311
1312         /* Transfer Complete Reload for Slave receiver mode */
1313         if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1314                 /*
1315                  * Read data byte then set NBYTES to receive next byte or NACK
1316                  * the current received byte
1317                  */
1318                 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1319                 ret = i2c_slave_event(i2c_dev->slave_running,
1320                                       I2C_SLAVE_WRITE_RECEIVED,
1321                                       &val);
1322                 if (!ret) {
1323                         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1324                         cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1325                         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1326                 } else {
1327                         mask = STM32F7_I2C_CR2_NACK;
1328                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1329                 }
1330         }
1331
1332         /* NACK received */
1333         if (status & STM32F7_I2C_ISR_NACKF) {
1334                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1335                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1336         }
1337
1338         /* STOP received */
1339         if (status & STM32F7_I2C_ISR_STOPF) {
1340                 /* Disable interrupts */
1341                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1342
1343                 if (i2c_dev->slave_dir) {
1344                         /*
1345                          * Flush TX buffer in order to not used the byte in
1346                          * TXDR for the next transfer
1347                          */
1348                         mask = STM32F7_I2C_ISR_TXE;
1349                         stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1350                 }
1351
1352                 /* Clear STOP flag */
1353                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1354
1355                 /* Notify i2c slave that a STOP flag has been detected */
1356                 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1357
1358                 i2c_dev->slave_running = NULL;
1359         }
1360
1361         /* Address match received */
1362         if (status & STM32F7_I2C_ISR_ADDR)
1363                 stm32f7_i2c_slave_addr(i2c_dev);
1364
1365         return IRQ_HANDLED;
1366 }
1367
1368 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1369 {
1370         struct stm32f7_i2c_dev *i2c_dev = data;
1371         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1372         void __iomem *base = i2c_dev->base;
1373         u32 status, mask;
1374         int ret = IRQ_HANDLED;
1375
1376         /* Check if the interrupt if for a slave device */
1377         if (!i2c_dev->master_mode) {
1378                 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1379                 return ret;
1380         }
1381
1382         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1383
1384         /* Tx empty */
1385         if (status & STM32F7_I2C_ISR_TXIS)
1386                 stm32f7_i2c_write_tx_data(i2c_dev);
1387
1388         /* RX not empty */
1389         if (status & STM32F7_I2C_ISR_RXNE)
1390                 stm32f7_i2c_read_rx_data(i2c_dev);
1391
1392         /* NACK received */
1393         if (status & STM32F7_I2C_ISR_NACKF) {
1394                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1395                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1396                 f7_msg->result = -ENXIO;
1397         }
1398
1399         /* STOP detection flag */
1400         if (status & STM32F7_I2C_ISR_STOPF) {
1401                 /* Disable interrupts */
1402                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1403                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1404                 else
1405                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1406                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1407
1408                 /* Clear STOP flag */
1409                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1410
1411                 if (i2c_dev->use_dma) {
1412                         ret = IRQ_WAKE_THREAD;
1413                 } else {
1414                         i2c_dev->master_mode = false;
1415                         complete(&i2c_dev->complete);
1416                 }
1417         }
1418
1419         /* Transfer complete */
1420         if (status & STM32F7_I2C_ISR_TC) {
1421                 if (f7_msg->stop) {
1422                         mask = STM32F7_I2C_CR2_STOP;
1423                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1424                 } else if (i2c_dev->use_dma) {
1425                         ret = IRQ_WAKE_THREAD;
1426                 } else if (f7_msg->smbus) {
1427                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1428                 } else {
1429                         i2c_dev->msg_id++;
1430                         i2c_dev->msg++;
1431                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1432                 }
1433         }
1434
1435         if (status & STM32F7_I2C_ISR_TCR) {
1436                 if (f7_msg->smbus)
1437                         stm32f7_i2c_smbus_reload(i2c_dev);
1438                 else
1439                         stm32f7_i2c_reload(i2c_dev);
1440         }
1441
1442         return ret;
1443 }
1444
1445 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1446 {
1447         struct stm32f7_i2c_dev *i2c_dev = data;
1448         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1449         struct stm32_i2c_dma *dma = i2c_dev->dma;
1450         u32 status;
1451         int ret;
1452
1453         /*
1454          * Wait for dma transfer completion before sending next message or
1455          * notity the end of xfer to the client
1456          */
1457         ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1458         if (!ret) {
1459                 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1460                 stm32f7_i2c_disable_dma_req(i2c_dev);
1461                 dmaengine_terminate_all(dma->chan_using);
1462                 f7_msg->result = -ETIMEDOUT;
1463         }
1464
1465         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1466
1467         if (status & STM32F7_I2C_ISR_TC) {
1468                 if (f7_msg->smbus) {
1469                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1470                 } else {
1471                         i2c_dev->msg_id++;
1472                         i2c_dev->msg++;
1473                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1474                 }
1475         } else {
1476                 i2c_dev->master_mode = false;
1477                 complete(&i2c_dev->complete);
1478         }
1479
1480         return IRQ_HANDLED;
1481 }
1482
1483 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1484 {
1485         struct stm32f7_i2c_dev *i2c_dev = data;
1486         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1487         void __iomem *base = i2c_dev->base;
1488         struct device *dev = i2c_dev->dev;
1489         struct stm32_i2c_dma *dma = i2c_dev->dma;
1490         u32 mask, status;
1491
1492         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1493
1494         /* Bus error */
1495         if (status & STM32F7_I2C_ISR_BERR) {
1496                 dev_err(dev, "<%s>: Bus error\n", __func__);
1497                 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1498                 stm32f7_i2c_release_bus(&i2c_dev->adap);
1499                 f7_msg->result = -EIO;
1500         }
1501
1502         /* Arbitration loss */
1503         if (status & STM32F7_I2C_ISR_ARLO) {
1504                 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1505                 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1506                 f7_msg->result = -EAGAIN;
1507         }
1508
1509         if (status & STM32F7_I2C_ISR_PECERR) {
1510                 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1511                 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1512                 f7_msg->result = -EINVAL;
1513         }
1514
1515         /* Disable interrupts */
1516         if (stm32f7_i2c_is_slave_registered(i2c_dev))
1517                 mask = STM32F7_I2C_XFER_IRQ_MASK;
1518         else
1519                 mask = STM32F7_I2C_ALL_IRQ_MASK;
1520         stm32f7_i2c_disable_irq(i2c_dev, mask);
1521
1522         /* Disable dma */
1523         if (i2c_dev->use_dma) {
1524                 stm32f7_i2c_disable_dma_req(i2c_dev);
1525                 dmaengine_terminate_all(dma->chan_using);
1526         }
1527
1528         i2c_dev->master_mode = false;
1529         complete(&i2c_dev->complete);
1530
1531         return IRQ_HANDLED;
1532 }
1533
1534 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1535                             struct i2c_msg msgs[], int num)
1536 {
1537         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1538         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1539         struct stm32_i2c_dma *dma = i2c_dev->dma;
1540         unsigned long time_left;
1541         int ret;
1542
1543         i2c_dev->msg = msgs;
1544         i2c_dev->msg_num = num;
1545         i2c_dev->msg_id = 0;
1546         f7_msg->smbus = false;
1547
1548         ret = clk_enable(i2c_dev->clk);
1549         if (ret) {
1550                 dev_err(i2c_dev->dev, "Failed to enable clock\n");
1551                 return ret;
1552         }
1553
1554         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1555         if (ret)
1556                 goto clk_free;
1557
1558         stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1559
1560         time_left = wait_for_completion_timeout(&i2c_dev->complete,
1561                                                 i2c_dev->adap.timeout);
1562         ret = f7_msg->result;
1563
1564         if (!time_left) {
1565                 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1566                         i2c_dev->msg->addr);
1567                 if (i2c_dev->use_dma)
1568                         dmaengine_terminate_all(dma->chan_using);
1569                 ret = -ETIMEDOUT;
1570         }
1571
1572 clk_free:
1573         clk_disable(i2c_dev->clk);
1574
1575         return (ret < 0) ? ret : num;
1576 }
1577
1578 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1579                                   unsigned short flags, char read_write,
1580                                   u8 command, int size,
1581                                   union i2c_smbus_data *data)
1582 {
1583         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1584         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1585         struct stm32_i2c_dma *dma = i2c_dev->dma;
1586         struct device *dev = i2c_dev->dev;
1587         unsigned long timeout;
1588         int i, ret;
1589
1590         f7_msg->addr = addr;
1591         f7_msg->size = size;
1592         f7_msg->read_write = read_write;
1593         f7_msg->smbus = true;
1594
1595         ret = clk_enable(i2c_dev->clk);
1596         if (ret) {
1597                 dev_err(i2c_dev->dev, "Failed to enable clock\n");
1598                 return ret;
1599         }
1600
1601         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1602         if (ret)
1603                 goto clk_free;
1604
1605         ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1606         if (ret)
1607                 goto clk_free;
1608
1609         timeout = wait_for_completion_timeout(&i2c_dev->complete,
1610                                               i2c_dev->adap.timeout);
1611         ret = f7_msg->result;
1612         if (ret)
1613                 goto clk_free;
1614
1615         if (!timeout) {
1616                 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1617                 if (i2c_dev->use_dma)
1618                         dmaengine_terminate_all(dma->chan_using);
1619                 ret = -ETIMEDOUT;
1620                 goto clk_free;
1621         }
1622
1623         /* Check PEC */
1624         if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1625                 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1626                 if (ret)
1627                         goto clk_free;
1628         }
1629
1630         if (read_write && size != I2C_SMBUS_QUICK) {
1631                 switch (size) {
1632                 case I2C_SMBUS_BYTE:
1633                 case I2C_SMBUS_BYTE_DATA:
1634                         data->byte = f7_msg->smbus_buf[0];
1635                 break;
1636                 case I2C_SMBUS_WORD_DATA:
1637                 case I2C_SMBUS_PROC_CALL:
1638                         data->word = f7_msg->smbus_buf[0] |
1639                                 (f7_msg->smbus_buf[1] << 8);
1640                 break;
1641                 case I2C_SMBUS_BLOCK_DATA:
1642                 case I2C_SMBUS_BLOCK_PROC_CALL:
1643                 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1644                         data->block[i] = f7_msg->smbus_buf[i];
1645                 break;
1646                 default:
1647                         dev_err(dev, "Unsupported smbus transaction\n");
1648                         ret = -EINVAL;
1649                 }
1650         }
1651
1652 clk_free:
1653         clk_disable(i2c_dev->clk);
1654         return ret;
1655 }
1656
1657 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1658 {
1659         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1660         void __iomem *base = i2c_dev->base;
1661         struct device *dev = i2c_dev->dev;
1662         u32 oar1, oar2, mask;
1663         int id, ret;
1664
1665         if (slave->flags & I2C_CLIENT_PEC) {
1666                 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1667                 return -EINVAL;
1668         }
1669
1670         if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1671                 dev_err(dev, "Too much slave registered\n");
1672                 return -EBUSY;
1673         }
1674
1675         ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1676         if (ret)
1677                 return ret;
1678
1679         if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1680                 ret = clk_enable(i2c_dev->clk);
1681                 if (ret) {
1682                         dev_err(dev, "Failed to enable clock\n");
1683                         return ret;
1684                 }
1685         }
1686
1687         if (id == 0) {
1688                 /* Configure Own Address 1 */
1689                 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1690                 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1691                 if (slave->flags & I2C_CLIENT_TEN) {
1692                         oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1693                         oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1694                 } else {
1695                         oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1696                 }
1697                 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1698                 i2c_dev->slave[id] = slave;
1699                 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1700         } else if (id == 1) {
1701                 /* Configure Own Address 2 */
1702                 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1703                 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1704                 if (slave->flags & I2C_CLIENT_TEN) {
1705                         ret = -EOPNOTSUPP;
1706                         goto exit;
1707                 }
1708
1709                 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1710                 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1711                 i2c_dev->slave[id] = slave;
1712                 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1713         } else {
1714                 ret = -ENODEV;
1715                 goto exit;
1716         }
1717
1718         /* Enable ACK */
1719         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1720
1721         /* Enable Address match interrupt, error interrupt and enable I2C  */
1722         mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1723                 STM32F7_I2C_CR1_PE;
1724         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1725
1726         return 0;
1727
1728 exit:
1729         if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1730                 clk_disable(i2c_dev->clk);
1731
1732         return ret;
1733 }
1734
1735 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1736 {
1737         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1738         void __iomem *base = i2c_dev->base;
1739         u32 mask;
1740         int id, ret;
1741
1742         ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1743         if (ret)
1744                 return ret;
1745
1746         WARN_ON(!i2c_dev->slave[id]);
1747
1748         if (id == 0) {
1749                 mask = STM32F7_I2C_OAR1_OA1EN;
1750                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1751         } else {
1752                 mask = STM32F7_I2C_OAR2_OA2EN;
1753                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1754         }
1755
1756         i2c_dev->slave[id] = NULL;
1757
1758         if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1759                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1760                 clk_disable(i2c_dev->clk);
1761         }
1762
1763         return 0;
1764 }
1765
1766 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1767 {
1768         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1769                 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1770                 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1771                 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1772                 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC;
1773 }
1774
1775 static struct i2c_algorithm stm32f7_i2c_algo = {
1776         .master_xfer = stm32f7_i2c_xfer,
1777         .smbus_xfer = stm32f7_i2c_smbus_xfer,
1778         .functionality = stm32f7_i2c_func,
1779         .reg_slave = stm32f7_i2c_reg_slave,
1780         .unreg_slave = stm32f7_i2c_unreg_slave,
1781 };
1782
1783 static int stm32f7_i2c_probe(struct platform_device *pdev)
1784 {
1785         struct device_node *np = pdev->dev.of_node;
1786         struct stm32f7_i2c_dev *i2c_dev;
1787         const struct stm32f7_i2c_setup *setup;
1788         struct resource *res;
1789         u32 irq_error, irq_event, clk_rate, rise_time, fall_time;
1790         struct i2c_adapter *adap;
1791         struct reset_control *rst;
1792         dma_addr_t phy_addr;
1793         int ret;
1794
1795         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1796         if (!i2c_dev)
1797                 return -ENOMEM;
1798
1799         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1800         i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1801         if (IS_ERR(i2c_dev->base))
1802                 return PTR_ERR(i2c_dev->base);
1803         phy_addr = (dma_addr_t)res->start;
1804
1805         irq_event = irq_of_parse_and_map(np, 0);
1806         if (!irq_event) {
1807                 dev_err(&pdev->dev, "IRQ event missing or invalid\n");
1808                 return -EINVAL;
1809         }
1810
1811         irq_error = irq_of_parse_and_map(np, 1);
1812         if (!irq_error) {
1813                 dev_err(&pdev->dev, "IRQ error missing or invalid\n");
1814                 return -EINVAL;
1815         }
1816
1817         i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1818         if (IS_ERR(i2c_dev->clk)) {
1819                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1820                 return PTR_ERR(i2c_dev->clk);
1821         }
1822         ret = clk_prepare_enable(i2c_dev->clk);
1823         if (ret) {
1824                 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
1825                 return ret;
1826         }
1827
1828         i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1829         ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1830                                        &clk_rate);
1831         if (!ret && clk_rate >= 1000000)
1832                 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
1833         else if (!ret && clk_rate >= 400000)
1834                 i2c_dev->speed = STM32_I2C_SPEED_FAST;
1835         else if (!ret && clk_rate >= 100000)
1836                 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1837
1838         rst = devm_reset_control_get(&pdev->dev, NULL);
1839         if (IS_ERR(rst)) {
1840                 dev_err(&pdev->dev, "Error: Missing controller reset\n");
1841                 ret = PTR_ERR(rst);
1842                 goto clk_free;
1843         }
1844         reset_control_assert(rst);
1845         udelay(2);
1846         reset_control_deassert(rst);
1847
1848         i2c_dev->dev = &pdev->dev;
1849
1850         ret = devm_request_threaded_irq(&pdev->dev, irq_event,
1851                                         stm32f7_i2c_isr_event,
1852                                         stm32f7_i2c_isr_event_thread,
1853                                         IRQF_ONESHOT,
1854                                         pdev->name, i2c_dev);
1855         if (ret) {
1856                 dev_err(&pdev->dev, "Failed to request irq event %i\n",
1857                         irq_event);
1858                 goto clk_free;
1859         }
1860
1861         ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
1862                                pdev->name, i2c_dev);
1863         if (ret) {
1864                 dev_err(&pdev->dev, "Failed to request irq error %i\n",
1865                         irq_error);
1866                 goto clk_free;
1867         }
1868
1869         setup = of_device_get_match_data(&pdev->dev);
1870         if (!setup) {
1871                 dev_err(&pdev->dev, "Can't get device data\n");
1872                 ret = -ENODEV;
1873                 goto clk_free;
1874         }
1875         i2c_dev->setup = *setup;
1876
1877         ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
1878                                        &rise_time);
1879         if (!ret)
1880                 i2c_dev->setup.rise_time = rise_time;
1881
1882         ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
1883                                        &fall_time);
1884         if (!ret)
1885                 i2c_dev->setup.fall_time = fall_time;
1886
1887         ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
1888         if (ret)
1889                 goto clk_free;
1890
1891         stm32f7_i2c_hw_config(i2c_dev);
1892
1893         adap = &i2c_dev->adap;
1894         i2c_set_adapdata(adap, i2c_dev);
1895         snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
1896                  &res->start);
1897         adap->owner = THIS_MODULE;
1898         adap->timeout = 2 * HZ;
1899         adap->retries = 3;
1900         adap->algo = &stm32f7_i2c_algo;
1901         adap->dev.parent = &pdev->dev;
1902         adap->dev.of_node = pdev->dev.of_node;
1903
1904         init_completion(&i2c_dev->complete);
1905
1906         /* Init DMA config if supported */
1907         i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
1908                                              STM32F7_I2C_TXDR,
1909                                              STM32F7_I2C_RXDR);
1910
1911         ret = i2c_add_adapter(adap);
1912         if (ret)
1913                 goto clk_free;
1914
1915         platform_set_drvdata(pdev, i2c_dev);
1916
1917         clk_disable(i2c_dev->clk);
1918
1919         dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
1920
1921         return 0;
1922
1923 clk_free:
1924         clk_disable_unprepare(i2c_dev->clk);
1925
1926         return ret;
1927 }
1928
1929 static int stm32f7_i2c_remove(struct platform_device *pdev)
1930 {
1931         struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1932
1933         if (i2c_dev->dma) {
1934                 stm32_i2c_dma_free(i2c_dev->dma);
1935                 i2c_dev->dma = NULL;
1936         }
1937
1938         i2c_del_adapter(&i2c_dev->adap);
1939
1940         clk_unprepare(i2c_dev->clk);
1941
1942         return 0;
1943 }
1944
1945 static const struct of_device_id stm32f7_i2c_match[] = {
1946         { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
1947         {},
1948 };
1949 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
1950
1951 static struct platform_driver stm32f7_i2c_driver = {
1952         .driver = {
1953                 .name = "stm32f7-i2c",
1954                 .of_match_table = stm32f7_i2c_match,
1955         },
1956         .probe = stm32f7_i2c_probe,
1957         .remove = stm32f7_i2c_remove,
1958 };
1959
1960 module_platform_driver(stm32f7_i2c_driver);
1961
1962 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
1963 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
1964 MODULE_LICENSE("GPL v2");