1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
4 * Copyright (C) 2004,2005,2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
7 * S3C2410 I2C Controller
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/time.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/clk.h>
23 #include <linux/cpufreq.h>
24 #include <linux/slab.h>
27 #include <linux/gpio/consumer.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
36 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
38 #define S3C2410_IICCON 0x00
39 #define S3C2410_IICSTAT 0x04
40 #define S3C2410_IICADD 0x08
41 #define S3C2410_IICDS 0x0C
42 #define S3C2440_IICLC 0x10
44 #define S3C2410_IICCON_ACKEN (1 << 7)
45 #define S3C2410_IICCON_TXDIV_16 (0 << 6)
46 #define S3C2410_IICCON_TXDIV_512 (1 << 6)
47 #define S3C2410_IICCON_IRQEN (1 << 5)
48 #define S3C2410_IICCON_IRQPEND (1 << 4)
49 #define S3C2410_IICCON_SCALE(x) ((x) & 0xf)
50 #define S3C2410_IICCON_SCALEMASK (0xf)
52 #define S3C2410_IICSTAT_MASTER_RX (2 << 6)
53 #define S3C2410_IICSTAT_MASTER_TX (3 << 6)
54 #define S3C2410_IICSTAT_SLAVE_RX (0 << 6)
55 #define S3C2410_IICSTAT_SLAVE_TX (1 << 6)
56 #define S3C2410_IICSTAT_MODEMASK (3 << 6)
58 #define S3C2410_IICSTAT_START (1 << 5)
59 #define S3C2410_IICSTAT_BUSBUSY (1 << 5)
60 #define S3C2410_IICSTAT_TXRXEN (1 << 4)
61 #define S3C2410_IICSTAT_ARBITR (1 << 3)
62 #define S3C2410_IICSTAT_ASSLAVE (1 << 2)
63 #define S3C2410_IICSTAT_ADDR0 (1 << 1)
64 #define S3C2410_IICSTAT_LASTBIT (1 << 0)
66 #define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
67 #define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
68 #define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
69 #define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
70 #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
72 #define S3C2410_IICLC_FILTER_ON (1 << 2)
74 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
75 #define QUIRK_S3C2440 (1 << 0)
76 #define QUIRK_HDMIPHY (1 << 1)
77 #define QUIRK_NO_GPIO (1 << 2)
78 #define QUIRK_POLL (1 << 3)
80 /* Max time to wait for bus to become idle after a xfer (in us) */
81 #define S3C2410_IDLE_TIMEOUT 5000
83 /* Exynos5 Sysreg offset */
84 #define EXYNOS5_SYS_I2C_CFG 0x0234
86 /* i2c controller state */
87 enum s3c24xx_i2c_state {
96 wait_queue_head_t wait;
97 kernel_ulong_t quirks;
100 unsigned int msg_num;
101 unsigned int msg_idx;
102 unsigned int msg_ptr;
104 unsigned int tx_setup;
107 enum s3c24xx_i2c_state state;
108 unsigned long clkrate;
113 struct i2c_adapter adap;
115 struct s3c2410_platform_i2c *pdata;
116 struct gpio_desc *gpios[2];
117 struct pinctrl *pctrl;
118 struct regmap *sysreg;
119 unsigned int sys_i2c_cfg;
122 static const struct platform_device_id s3c24xx_driver_ids[] = {
124 .name = "s3c2410-i2c",
127 .name = "s3c2440-i2c",
128 .driver_data = QUIRK_S3C2440,
130 .name = "s3c2440-hdmiphy-i2c",
131 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
134 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
136 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
139 static const struct of_device_id s3c24xx_i2c_match[] = {
140 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
141 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
142 { .compatible = "samsung,s3c2440-hdmiphy-i2c",
143 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
144 { .compatible = "samsung,exynos5-sata-phy-i2c",
145 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
148 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
152 * Get controller type either from device tree or platform device variant.
154 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
156 if (pdev->dev.of_node)
157 return (kernel_ulong_t)of_device_get_match_data(&pdev->dev);
159 return platform_get_device_id(pdev)->driver_data;
163 * Complete the message and wake up the caller, using the given return code,
164 * or zero to mean ok.
166 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
168 dev_dbg(i2c->dev, "master_complete %d\n", ret);
177 if (!(i2c->quirks & QUIRK_POLL))
181 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
185 tmp = readl(i2c->regs + S3C2410_IICCON);
186 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
189 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
193 tmp = readl(i2c->regs + S3C2410_IICCON);
194 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
197 /* irq enable/disable functions */
198 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
202 tmp = readl(i2c->regs + S3C2410_IICCON);
203 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
206 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
210 tmp = readl(i2c->regs + S3C2410_IICCON);
211 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
214 static bool is_ack(struct s3c24xx_i2c *i2c)
218 for (tries = 50; tries; --tries) {
219 unsigned long tmp = readl(i2c->regs + S3C2410_IICCON);
221 if (!(tmp & S3C2410_IICCON_ACKEN)) {
223 * Wait a bit for the bus to stabilize,
224 * delay estimated experimentally.
226 usleep_range(100, 200);
229 if (tmp & S3C2410_IICCON_IRQPEND) {
230 if (!(readl(i2c->regs + S3C2410_IICSTAT)
231 & S3C2410_IICSTAT_LASTBIT))
234 usleep_range(1000, 2000);
236 dev_err(i2c->dev, "ack was not received\n");
241 * put the start of a message onto the bus
243 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
246 unsigned int addr = (msg->addr & 0x7f) << 1;
248 unsigned long iiccon;
251 stat |= S3C2410_IICSTAT_TXRXEN;
253 if (msg->flags & I2C_M_RD) {
254 stat |= S3C2410_IICSTAT_MASTER_RX;
257 stat |= S3C2410_IICSTAT_MASTER_TX;
259 if (msg->flags & I2C_M_REV_DIR_ADDR)
262 /* todo - check for whether ack wanted or not */
263 s3c24xx_i2c_enable_ack(i2c);
265 iiccon = readl(i2c->regs + S3C2410_IICCON);
266 writel(stat, i2c->regs + S3C2410_IICSTAT);
268 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
269 writeb(addr, i2c->regs + S3C2410_IICDS);
272 * delay here to ensure the data byte has gotten onto the bus
273 * before the transaction is started
275 ndelay(i2c->tx_setup);
277 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
278 writel(iiccon, i2c->regs + S3C2410_IICCON);
280 stat |= S3C2410_IICSTAT_START;
281 writel(stat, i2c->regs + S3C2410_IICSTAT);
283 if (i2c->quirks & QUIRK_POLL) {
284 while ((i2c->msg_num != 0) && is_ack(i2c)) {
285 i2c_s3c_irq_nextbyte(i2c, stat);
286 stat = readl(i2c->regs + S3C2410_IICSTAT);
288 if (stat & S3C2410_IICSTAT_ARBITR)
289 dev_err(i2c->dev, "deal with arbitration loss\n");
294 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
296 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
298 dev_dbg(i2c->dev, "STOP\n");
301 * The datasheet says that the STOP sequence should be:
302 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
303 * 2) I2CCON.4 = 0 - Clear IRQPEND
304 * 3) Wait until the stop condition takes effect.
305 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN
307 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
309 * However, after much experimentation, it appears that:
310 * a) normal buses automatically clear BUSY and transition from
311 * Master->Slave when they complete generating a STOP condition.
312 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4
313 * after starting the STOP generation here.
314 * b) HDMIPHY bus does neither, so there is no way to do step 3.
315 * There is no indication when this bus has finished generating
318 * In fact, we have found that as soon as the IRQPEND bit is cleared in
319 * step 2, the HDMIPHY bus generates the STOP condition, and then
320 * immediately starts transferring another data byte, even though the
321 * bus is supposedly stopped. This is presumably because the bus is
322 * still in "Master" mode, and its BUSY bit is still set.
324 * To avoid these extra post-STOP transactions on HDMI phy devices, we
325 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
326 * instead of first generating a proper STOP condition. This should
327 * float SDA & SCK terminating the transfer. Subsequent transfers
328 * start with a proper START condition, and proceed normally.
330 * The HDMIPHY bus is an internal bus that always has exactly two
331 * devices, the host as Master and the HDMIPHY device as the slave.
332 * Skipping the STOP condition has been tested on this bus and works.
334 if (i2c->quirks & QUIRK_HDMIPHY) {
335 /* Stop driving the I2C pins */
336 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
338 /* stop the transfer */
339 iicstat &= ~S3C2410_IICSTAT_START;
341 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
343 i2c->state = STATE_STOP;
345 s3c24xx_i2c_master_complete(i2c, ret);
346 s3c24xx_i2c_disable_irq(i2c);
350 * helper functions to determine the current state in the set of
351 * messages we are sending
355 * returns TRUE if the current message is the last in the set
357 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
359 return i2c->msg_idx >= (i2c->msg_num - 1);
363 * returns TRUE if we this is the last byte in the current message
365 static inline int is_msglast(struct s3c24xx_i2c *i2c)
368 * msg->len is always 1 for the first byte of smbus block read.
369 * Actual length will be read from slave. More bytes will be
370 * read according to the length then.
372 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
375 return i2c->msg_ptr == i2c->msg->len-1;
379 * returns TRUE if we reached the end of the current message
381 static inline int is_msgend(struct s3c24xx_i2c *i2c)
383 return i2c->msg_ptr >= i2c->msg->len;
387 * process an interrupt and work out what to do
389 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
395 switch (i2c->state) {
398 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
402 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
403 s3c24xx_i2c_disable_irq(i2c);
408 * last thing we did was send a start condition on the
409 * bus, or started a new i2c message
411 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
412 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
413 /* ack was not received... */
414 dev_dbg(i2c->dev, "ack was not received\n");
415 s3c24xx_i2c_stop(i2c, -ENXIO);
419 if (i2c->msg->flags & I2C_M_RD)
420 i2c->state = STATE_READ;
422 i2c->state = STATE_WRITE;
425 * Terminate the transfer if there is nothing to do
426 * as this is used by the i2c probe to find devices.
428 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
429 s3c24xx_i2c_stop(i2c, 0);
433 if (i2c->state == STATE_READ)
437 * fall through to the write state, as we will need to
438 * send a byte as well
443 * we are writing data to the device... check for the
444 * end of the message, and if so, work out what to do
446 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
447 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
448 dev_dbg(i2c->dev, "WRITE: No Ack\n");
450 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
457 if (!is_msgend(i2c)) {
458 byte = i2c->msg->buf[i2c->msg_ptr++];
459 writeb(byte, i2c->regs + S3C2410_IICDS);
462 * delay after writing the byte to allow the
463 * data setup time on the bus, as writing the
464 * data to the register causes the first bit
465 * to appear on SDA, and SCL will change as
466 * soon as the interrupt is acknowledged
468 ndelay(i2c->tx_setup);
470 } else if (!is_lastmsg(i2c)) {
471 /* we need to go to the next i2c message */
473 dev_dbg(i2c->dev, "WRITE: Next Message\n");
479 /* check to see if we need to do another message */
480 if (i2c->msg->flags & I2C_M_NOSTART) {
482 if (i2c->msg->flags & I2C_M_RD) {
484 * cannot do this, the controller
485 * forces us to send a new START
486 * when we change direction
489 "missing START before write->read\n");
490 s3c24xx_i2c_stop(i2c, -EINVAL);
496 /* send the new start */
497 s3c24xx_i2c_message_start(i2c, i2c->msg);
498 i2c->state = STATE_START;
503 s3c24xx_i2c_stop(i2c, 0);
509 * we have a byte of data in the data register, do
510 * something with it, and then work out whether we are
511 * going to do any more read/write
513 byte = readb(i2c->regs + S3C2410_IICDS);
514 i2c->msg->buf[i2c->msg_ptr++] = byte;
516 /* Add actual length to read for smbus block read */
517 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
518 i2c->msg->len += byte;
520 if (is_msglast(i2c)) {
521 /* last byte of buffer */
524 s3c24xx_i2c_disable_ack(i2c);
526 } else if (is_msgend(i2c)) {
528 * ok, we've read the entire buffer, see if there
529 * is anything else we need to do
531 if (is_lastmsg(i2c)) {
532 /* last message, send stop and complete */
533 dev_dbg(i2c->dev, "READ: Send Stop\n");
535 s3c24xx_i2c_stop(i2c, 0);
537 /* go to the next transfer */
538 dev_dbg(i2c->dev, "READ: Next Transfer\n");
549 /* acknowlegde the IRQ and get back on with the work */
552 tmp = readl(i2c->regs + S3C2410_IICCON);
553 tmp &= ~S3C2410_IICCON_IRQPEND;
554 writel(tmp, i2c->regs + S3C2410_IICCON);
560 * top level IRQ servicing routine
562 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
564 struct s3c24xx_i2c *i2c = dev_id;
565 unsigned long status;
568 status = readl(i2c->regs + S3C2410_IICSTAT);
570 if (status & S3C2410_IICSTAT_ARBITR) {
571 /* deal with arbitration loss */
572 dev_err(i2c->dev, "deal with arbitration loss\n");
575 if (i2c->state == STATE_IDLE) {
576 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
578 tmp = readl(i2c->regs + S3C2410_IICCON);
579 tmp &= ~S3C2410_IICCON_IRQPEND;
580 writel(tmp, i2c->regs + S3C2410_IICCON);
585 * pretty much this leaves us with the fact that we've
586 * transmitted or received whatever byte we last sent
588 i2c_s3c_irq_nextbyte(i2c, status);
595 * Disable the bus so that we won't get any interrupts from now on, or try
596 * to drive any lines. This is the default state when we don't have
597 * anything to send/receive.
599 * If there is an event on the bus, or we have a pre-existing event at
600 * kernel boot time, we may not notice the event and the I2C controller
601 * will lock the bus with the I2C clock line low indefinitely.
603 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
607 /* Stop driving the I2C pins */
608 tmp = readl(i2c->regs + S3C2410_IICSTAT);
609 tmp &= ~S3C2410_IICSTAT_TXRXEN;
610 writel(tmp, i2c->regs + S3C2410_IICSTAT);
612 /* We don't expect any interrupts now, and don't want send acks */
613 tmp = readl(i2c->regs + S3C2410_IICCON);
614 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
615 S3C2410_IICCON_ACKEN);
616 writel(tmp, i2c->regs + S3C2410_IICCON);
621 * get the i2c bus for a master transaction
623 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
625 unsigned long iicstat;
628 while (timeout-- > 0) {
629 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
631 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
641 * wait for the i2c bus to become idle.
643 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
645 unsigned long iicstat;
650 /* ensure the stop has been through the bus */
652 dev_dbg(i2c->dev, "waiting for bus idle\n");
654 start = now = ktime_get();
657 * Most of the time, the bus is already idle within a few usec of the
658 * end of a transaction. However, really slow i2c devices can stretch
659 * the clock, delaying STOP generation.
661 * On slower SoCs this typically happens within a very small number of
662 * instructions so busy wait briefly to avoid scheduling overhead.
665 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
666 while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
668 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
672 * If we do get an appreciable delay as a compromise between idle
673 * detection latency for the normal, fast case, and system load in the
674 * slow device case, use an exponential back off in the polling loop,
675 * up to 1/10th of the total timeout, then continue to poll at a
676 * constant rate up to the timeout.
679 while ((iicstat & S3C2410_IICSTAT_START) &&
680 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
681 usleep_range(delay, 2 * delay);
682 if (delay < S3C2410_IDLE_TIMEOUT / 10)
685 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
688 if (iicstat & S3C2410_IICSTAT_START)
689 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
693 * this starts an i2c transfer
695 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
696 struct i2c_msg *msgs, int num)
698 unsigned long timeout;
701 ret = s3c24xx_i2c_set_master(i2c);
703 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
712 i2c->state = STATE_START;
714 s3c24xx_i2c_enable_irq(i2c);
715 s3c24xx_i2c_message_start(i2c, msgs);
717 if (i2c->quirks & QUIRK_POLL) {
721 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
726 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
731 * Having these next two as dev_err() makes life very
732 * noisy when doing an i2cdetect
735 dev_dbg(i2c->dev, "timeout\n");
737 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
739 /* For QUIRK_HDMIPHY, bus is already disabled */
740 if (i2c->quirks & QUIRK_HDMIPHY)
743 s3c24xx_i2c_wait_idle(i2c);
745 s3c24xx_i2c_disable_bus(i2c);
748 i2c->state = STATE_IDLE;
754 * first port of call from the i2c bus code when an message needs
755 * transferring across the i2c bus.
757 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
758 struct i2c_msg *msgs, int num)
760 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
764 ret = clk_enable(i2c->clk);
768 for (retry = 0; retry < adap->retries; retry++) {
770 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
772 if (ret != -EAGAIN) {
773 clk_disable(i2c->clk);
777 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
782 clk_disable(i2c->clk);
786 /* declare our i2c functionality */
787 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
789 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL_ALL | I2C_FUNC_NOSTART |
790 I2C_FUNC_PROTOCOL_MANGLING;
793 /* i2c bus registration info */
794 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
795 .master_xfer = s3c24xx_i2c_xfer,
796 .functionality = s3c24xx_i2c_func,
800 * return the divisor settings for a given frequency
802 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
803 unsigned int *div1, unsigned int *divs)
805 unsigned int calc_divs = clkin / wanted;
806 unsigned int calc_div1;
808 if (calc_divs > (16*16))
813 calc_divs += calc_div1-1;
814 calc_divs /= calc_div1;
824 return clkin / (calc_divs * calc_div1);
828 * work out a divisor for the user requested frequency setting,
829 * either by the requested frequency, or scanning the acceptable
830 * range of frequencies until something is found
832 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
834 struct s3c2410_platform_i2c *pdata = i2c->pdata;
835 unsigned long clkin = clk_get_rate(i2c->clk);
836 unsigned int divs, div1;
837 unsigned long target_frequency;
841 i2c->clkrate = clkin;
842 clkin /= 1000; /* clkin now in KHz */
844 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
846 target_frequency = pdata->frequency ?: I2C_MAX_STANDARD_MODE_FREQ;
848 target_frequency /= 1000; /* Target frequency now in KHz */
850 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
852 if (freq > target_frequency) {
854 "Unable to achieve desired frequency %luKHz." \
855 " Lowest achievable %dKHz\n", target_frequency, freq);
861 iiccon = readl(i2c->regs + S3C2410_IICCON);
862 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
866 iiccon |= S3C2410_IICCON_TXDIV_512;
868 if (i2c->quirks & QUIRK_POLL)
869 iiccon |= S3C2410_IICCON_SCALE(2);
871 writel(iiccon, i2c->regs + S3C2410_IICCON);
873 if (i2c->quirks & QUIRK_S3C2440) {
874 unsigned long sda_delay;
876 if (pdata->sda_delay) {
877 sda_delay = clkin * pdata->sda_delay;
878 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
879 sda_delay = DIV_ROUND_UP(sda_delay, 5);
882 sda_delay |= S3C2410_IICLC_FILTER_ON;
886 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
887 writel(sda_delay, i2c->regs + S3C2440_IICLC);
894 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
898 if (i2c->quirks & QUIRK_NO_GPIO)
901 for (i = 0; i < 2; i++) {
902 i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL,
904 if (IS_ERR(i2c->gpios[i])) {
905 dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i);
913 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
920 * initialise the controller, set the IO lines and frequency
922 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
924 struct s3c2410_platform_i2c *pdata;
927 /* get the plafrom data */
931 /* write slave address */
933 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
935 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
937 writel(0, i2c->regs + S3C2410_IICCON);
938 writel(0, i2c->regs + S3C2410_IICSTAT);
940 /* we need to work out the divisors for the clock... */
942 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
943 dev_err(i2c->dev, "cannot meet bus frequency required\n");
947 /* todo - check that the i2c lines aren't being dragged anywhere */
949 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
950 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
951 readl(i2c->regs + S3C2410_IICCON));
958 * Parse the device tree node and retreive the platform data.
961 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
963 struct s3c2410_platform_i2c *pdata = i2c->pdata;
969 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
970 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
971 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
972 of_property_read_u32(np, "samsung,i2c-max-bus-freq",
973 (u32 *)&pdata->frequency);
975 * Exynos5's legacy i2c controller and new high speed i2c
976 * controller have muxed interrupt sources. By default the
977 * interrupts for 4-channel HS-I2C controller are enabled.
978 * If nodes for first four channels of legacy i2c controller
979 * are available then re-configure the interrupts via the
982 id = of_alias_get_id(np, "i2c");
983 i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
984 "samsung,sysreg-phandle");
985 if (IS_ERR(i2c->sysreg))
988 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
992 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
995 static int s3c24xx_i2c_probe(struct platform_device *pdev)
997 struct s3c24xx_i2c *i2c;
998 struct s3c2410_platform_i2c *pdata = NULL;
999 struct resource *res;
1002 if (!pdev->dev.of_node) {
1003 pdata = dev_get_platdata(&pdev->dev);
1005 dev_err(&pdev->dev, "no platform data\n");
1010 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1014 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1018 i2c->quirks = s3c24xx_get_device_quirks(pdev);
1019 i2c->sysreg = ERR_PTR(-ENOENT);
1021 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1023 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1025 strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1026 i2c->adap.owner = THIS_MODULE;
1027 i2c->adap.algo = &s3c24xx_i2c_algorithm;
1028 i2c->adap.retries = 2;
1029 i2c->adap.class = I2C_CLASS_DEPRECATED;
1032 init_waitqueue_head(&i2c->wait);
1034 /* find the clock and enable it */
1035 i2c->dev = &pdev->dev;
1036 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1037 if (IS_ERR(i2c->clk)) {
1038 dev_err(&pdev->dev, "cannot get clock\n");
1042 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1044 /* map the registers */
1045 i2c->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1046 if (IS_ERR(i2c->regs))
1047 return PTR_ERR(i2c->regs);
1049 dev_dbg(&pdev->dev, "registers %p (%p)\n",
1052 /* setup info block for the i2c core */
1053 i2c->adap.algo_data = i2c;
1054 i2c->adap.dev.parent = &pdev->dev;
1055 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1057 /* inititalise the i2c gpio lines */
1058 if (i2c->pdata->cfg_gpio)
1059 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1060 else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1063 /* initialise the i2c controller */
1064 ret = clk_prepare_enable(i2c->clk);
1066 dev_err(&pdev->dev, "I2C clock enable failed\n");
1070 ret = s3c24xx_i2c_init(i2c);
1071 clk_disable(i2c->clk);
1073 dev_err(&pdev->dev, "I2C controller init failed\n");
1074 clk_unprepare(i2c->clk);
1079 * find the IRQ for this unit (note, this relies on the init call to
1080 * ensure no current IRQs pending
1082 if (!(i2c->quirks & QUIRK_POLL)) {
1083 i2c->irq = ret = platform_get_irq(pdev, 0);
1085 clk_unprepare(i2c->clk);
1089 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1090 0, dev_name(&pdev->dev), i2c);
1092 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1093 clk_unprepare(i2c->clk);
1099 * Note, previous versions of the driver used i2c_add_adapter()
1100 * to add the bus at any number. We now pass the bus number via
1101 * the platform data, so if unset it will now default to always
1104 i2c->adap.nr = i2c->pdata->bus_num;
1105 i2c->adap.dev.of_node = pdev->dev.of_node;
1107 platform_set_drvdata(pdev, i2c);
1109 pm_runtime_enable(&pdev->dev);
1111 ret = i2c_add_numbered_adapter(&i2c->adap);
1113 pm_runtime_disable(&pdev->dev);
1114 clk_unprepare(i2c->clk);
1118 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1122 static void s3c24xx_i2c_remove(struct platform_device *pdev)
1124 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1126 clk_unprepare(i2c->clk);
1128 pm_runtime_disable(&pdev->dev);
1130 i2c_del_adapter(&i2c->adap);
1133 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1135 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1137 i2c_mark_adapter_suspended(&i2c->adap);
1139 if (!IS_ERR(i2c->sysreg))
1140 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1145 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1147 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1150 if (!IS_ERR(i2c->sysreg))
1151 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1153 ret = clk_enable(i2c->clk);
1156 s3c24xx_i2c_init(i2c);
1157 clk_disable(i2c->clk);
1158 i2c_mark_adapter_resumed(&i2c->adap);
1163 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1164 NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1165 s3c24xx_i2c_resume_noirq)
1168 static struct platform_driver s3c24xx_i2c_driver = {
1169 .probe = s3c24xx_i2c_probe,
1170 .remove_new = s3c24xx_i2c_remove,
1171 .id_table = s3c24xx_driver_ids,
1174 .pm = pm_sleep_ptr(&s3c24xx_i2c_dev_pm_ops),
1175 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1179 static int __init i2c_adap_s3c_init(void)
1181 return platform_driver_register(&s3c24xx_i2c_driver);
1183 subsys_initcall(i2c_adap_s3c_init);
1185 static void __exit i2c_adap_s3c_exit(void)
1187 platform_driver_unregister(&s3c24xx_i2c_driver);
1189 module_exit(i2c_adap_s3c_exit);
1191 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1192 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1193 MODULE_LICENSE("GPL");