1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3 * Copyright (C) 2004,2005,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 I2C Controller
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/i2c.h>
27 #include <linux/init.h>
28 #include <linux/time.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/errno.h>
32 #include <linux/err.h>
33 #include <linux/platform_device.h>
34 #include <linux/clk.h>
35 #include <linux/cpufreq.h>
36 #include <linux/slab.h>
38 #include <linux/of_i2c.h>
39 #include <linux/of_gpio.h>
43 #include <plat/regs-iic.h>
46 /* i2c controller state */
48 enum s3c24xx_i2c_state {
56 enum s3c24xx_i2c_type {
63 wait_queue_head_t wait;
64 unsigned int suspended:1;
71 unsigned int tx_setup;
74 enum s3c24xx_i2c_state state;
75 unsigned long clkrate;
80 struct resource *ioarea;
81 struct i2c_adapter adap;
83 struct s3c2410_platform_i2c *pdata;
85 #ifdef CONFIG_CPU_FREQ
86 struct notifier_block freq_transition;
90 /* default platform data removed, dev should always carry data. */
92 /* s3c24xx_i2c_is2440()
94 * return true is this is an s3c2440
97 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
99 struct platform_device *pdev = to_platform_device(i2c->dev);
100 enum s3c24xx_i2c_type type;
103 if (i2c->dev->of_node)
104 return of_device_is_compatible(i2c->dev->of_node,
105 "samsung,s3c2440-i2c");
108 type = platform_get_device_id(pdev)->driver_data;
109 return type == TYPE_S3C2440;
112 /* s3c24xx_i2c_master_complete
114 * complete the message and wake up the caller, using the given return code,
115 * or zero to mean ok.
118 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
120 dev_dbg(i2c->dev, "master_complete %d\n", ret);
132 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
136 tmp = readl(i2c->regs + S3C2410_IICCON);
137 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
140 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
144 tmp = readl(i2c->regs + S3C2410_IICCON);
145 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
148 /* irq enable/disable functions */
150 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
154 tmp = readl(i2c->regs + S3C2410_IICCON);
155 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
158 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
162 tmp = readl(i2c->regs + S3C2410_IICCON);
163 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
167 /* s3c24xx_i2c_message_start
169 * put the start of a message onto the bus
172 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
175 unsigned int addr = (msg->addr & 0x7f) << 1;
177 unsigned long iiccon;
180 stat |= S3C2410_IICSTAT_TXRXEN;
182 if (msg->flags & I2C_M_RD) {
183 stat |= S3C2410_IICSTAT_MASTER_RX;
186 stat |= S3C2410_IICSTAT_MASTER_TX;
188 if (msg->flags & I2C_M_REV_DIR_ADDR)
191 /* todo - check for wether ack wanted or not */
192 s3c24xx_i2c_enable_ack(i2c);
194 iiccon = readl(i2c->regs + S3C2410_IICCON);
195 writel(stat, i2c->regs + S3C2410_IICSTAT);
197 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
198 writeb(addr, i2c->regs + S3C2410_IICDS);
200 /* delay here to ensure the data byte has gotten onto the bus
201 * before the transaction is started */
203 ndelay(i2c->tx_setup);
205 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
206 writel(iiccon, i2c->regs + S3C2410_IICCON);
208 stat |= S3C2410_IICSTAT_START;
209 writel(stat, i2c->regs + S3C2410_IICSTAT);
212 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
214 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
216 dev_dbg(i2c->dev, "STOP\n");
218 /* stop the transfer */
219 iicstat &= ~S3C2410_IICSTAT_START;
220 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
222 i2c->state = STATE_STOP;
224 s3c24xx_i2c_master_complete(i2c, ret);
225 s3c24xx_i2c_disable_irq(i2c);
228 /* helper functions to determine the current state in the set of
229 * messages we are sending */
233 * returns TRUE if the current message is the last in the set
236 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
238 return i2c->msg_idx >= (i2c->msg_num - 1);
243 * returns TRUE if we this is the last byte in the current message
246 static inline int is_msglast(struct s3c24xx_i2c *i2c)
248 return i2c->msg_ptr == i2c->msg->len-1;
253 * returns TRUE if we reached the end of the current message
256 static inline int is_msgend(struct s3c24xx_i2c *i2c)
258 return i2c->msg_ptr >= i2c->msg->len;
261 /* i2c_s3c_irq_nextbyte
263 * process an interrupt and work out what to do
266 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
272 switch (i2c->state) {
275 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
279 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
280 s3c24xx_i2c_disable_irq(i2c);
284 /* last thing we did was send a start condition on the
285 * bus, or started a new i2c message
288 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
289 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
290 /* ack was not received... */
292 dev_dbg(i2c->dev, "ack was not received\n");
293 s3c24xx_i2c_stop(i2c, -ENXIO);
297 if (i2c->msg->flags & I2C_M_RD)
298 i2c->state = STATE_READ;
300 i2c->state = STATE_WRITE;
302 /* terminate the transfer if there is nothing to do
303 * as this is used by the i2c probe to find devices. */
305 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
306 s3c24xx_i2c_stop(i2c, 0);
310 if (i2c->state == STATE_READ)
313 /* fall through to the write state, as we will need to
314 * send a byte as well */
317 /* we are writing data to the device... check for the
318 * end of the message, and if so, work out what to do
321 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
322 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
323 dev_dbg(i2c->dev, "WRITE: No Ack\n");
325 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
332 if (!is_msgend(i2c)) {
333 byte = i2c->msg->buf[i2c->msg_ptr++];
334 writeb(byte, i2c->regs + S3C2410_IICDS);
336 /* delay after writing the byte to allow the
337 * data setup time on the bus, as writing the
338 * data to the register causes the first bit
339 * to appear on SDA, and SCL will change as
340 * soon as the interrupt is acknowledged */
342 ndelay(i2c->tx_setup);
344 } else if (!is_lastmsg(i2c)) {
345 /* we need to go to the next i2c message */
347 dev_dbg(i2c->dev, "WRITE: Next Message\n");
353 /* check to see if we need to do another message */
354 if (i2c->msg->flags & I2C_M_NOSTART) {
356 if (i2c->msg->flags & I2C_M_RD) {
357 /* cannot do this, the controller
358 * forces us to send a new START
359 * when we change direction */
361 s3c24xx_i2c_stop(i2c, -EINVAL);
366 /* send the new start */
367 s3c24xx_i2c_message_start(i2c, i2c->msg);
368 i2c->state = STATE_START;
374 s3c24xx_i2c_stop(i2c, 0);
379 /* we have a byte of data in the data register, do
380 * something with it, and then work out wether we are
381 * going to do any more read/write
384 byte = readb(i2c->regs + S3C2410_IICDS);
385 i2c->msg->buf[i2c->msg_ptr++] = byte;
388 if (is_msglast(i2c)) {
389 /* last byte of buffer */
392 s3c24xx_i2c_disable_ack(i2c);
394 } else if (is_msgend(i2c)) {
395 /* ok, we've read the entire buffer, see if there
396 * is anything else we need to do */
398 if (is_lastmsg(i2c)) {
399 /* last message, send stop and complete */
400 dev_dbg(i2c->dev, "READ: Send Stop\n");
402 s3c24xx_i2c_stop(i2c, 0);
404 /* go to the next transfer */
405 dev_dbg(i2c->dev, "READ: Next Transfer\n");
416 /* acknowlegde the IRQ and get back on with the work */
419 tmp = readl(i2c->regs + S3C2410_IICCON);
420 tmp &= ~S3C2410_IICCON_IRQPEND;
421 writel(tmp, i2c->regs + S3C2410_IICCON);
428 * top level IRQ servicing routine
431 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
433 struct s3c24xx_i2c *i2c = dev_id;
434 unsigned long status;
437 status = readl(i2c->regs + S3C2410_IICSTAT);
439 if (status & S3C2410_IICSTAT_ARBITR) {
440 /* deal with arbitration loss */
441 dev_err(i2c->dev, "deal with arbitration loss\n");
444 if (i2c->state == STATE_IDLE) {
445 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
447 tmp = readl(i2c->regs + S3C2410_IICCON);
448 tmp &= ~S3C2410_IICCON_IRQPEND;
449 writel(tmp, i2c->regs + S3C2410_IICCON);
453 /* pretty much this leaves us with the fact that we've
454 * transmitted or received whatever byte we last sent */
456 i2c_s3c_irq_nextbyte(i2c, status);
463 /* s3c24xx_i2c_set_master
465 * get the i2c bus for a master transaction
468 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
470 unsigned long iicstat;
473 while (timeout-- > 0) {
474 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
476 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
485 /* s3c24xx_i2c_doxfer
487 * this starts an i2c transfer
490 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
491 struct i2c_msg *msgs, int num)
493 unsigned long iicstat, timeout;
500 ret = s3c24xx_i2c_set_master(i2c);
502 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
507 spin_lock_irq(&i2c->lock);
513 i2c->state = STATE_START;
515 s3c24xx_i2c_enable_irq(i2c);
516 s3c24xx_i2c_message_start(i2c, msgs);
517 spin_unlock_irq(&i2c->lock);
519 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
523 /* having these next two as dev_err() makes life very
524 * noisy when doing an i2cdetect */
527 dev_dbg(i2c->dev, "timeout\n");
529 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
531 /* ensure the stop has been through the bus */
533 dev_dbg(i2c->dev, "waiting for bus idle\n");
535 /* first, try busy waiting briefly */
538 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
539 } while ((iicstat & S3C2410_IICSTAT_START) && --spins);
541 /* if that timed out sleep */
544 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
547 if (iicstat & S3C2410_IICSTAT_START)
548 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
556 * first port of call from the i2c bus code when an message needs
557 * transferring across the i2c bus.
560 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
561 struct i2c_msg *msgs, int num)
563 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
567 clk_enable(i2c->clk);
569 for (retry = 0; retry < adap->retries; retry++) {
571 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
573 if (ret != -EAGAIN) {
574 clk_disable(i2c->clk);
578 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
583 clk_disable(i2c->clk);
587 /* declare our i2c functionality */
588 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
590 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
593 /* i2c bus registration info */
595 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
596 .master_xfer = s3c24xx_i2c_xfer,
597 .functionality = s3c24xx_i2c_func,
600 /* s3c24xx_i2c_calcdivisor
602 * return the divisor settings for a given frequency
605 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
606 unsigned int *div1, unsigned int *divs)
608 unsigned int calc_divs = clkin / wanted;
609 unsigned int calc_div1;
611 if (calc_divs > (16*16))
616 calc_divs += calc_div1-1;
617 calc_divs /= calc_div1;
627 return clkin / (calc_divs * calc_div1);
630 /* s3c24xx_i2c_clockrate
632 * work out a divisor for the user requested frequency setting,
633 * either by the requested frequency, or scanning the acceptable
634 * range of frequencies until something is found
637 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
639 struct s3c2410_platform_i2c *pdata = i2c->pdata;
640 unsigned long clkin = clk_get_rate(i2c->clk);
641 unsigned int divs, div1;
642 unsigned long target_frequency;
646 i2c->clkrate = clkin;
647 clkin /= 1000; /* clkin now in KHz */
649 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
651 target_frequency = pdata->frequency ? pdata->frequency : 100000;
653 target_frequency /= 1000; /* Target frequency now in KHz */
655 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
657 if (freq > target_frequency) {
659 "Unable to achieve desired frequency %luKHz." \
660 " Lowest achievable %dKHz\n", target_frequency, freq);
666 iiccon = readl(i2c->regs + S3C2410_IICCON);
667 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
671 iiccon |= S3C2410_IICCON_TXDIV_512;
673 writel(iiccon, i2c->regs + S3C2410_IICCON);
675 if (s3c24xx_i2c_is2440(i2c)) {
676 unsigned long sda_delay;
678 if (pdata->sda_delay) {
679 sda_delay = clkin * pdata->sda_delay;
680 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
681 sda_delay = DIV_ROUND_UP(sda_delay, 5);
684 sda_delay |= S3C2410_IICLC_FILTER_ON;
688 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
689 writel(sda_delay, i2c->regs + S3C2440_IICLC);
695 #ifdef CONFIG_CPU_FREQ
697 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
699 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
700 unsigned long val, void *data)
702 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
708 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
710 /* if we're post-change and the input clock has slowed down
711 * or at pre-change and the clock is about to speed up, then
712 * adjust our clock rate. <0 is slow, >0 speedup.
715 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
716 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
717 spin_lock_irqsave(&i2c->lock, flags);
718 ret = s3c24xx_i2c_clockrate(i2c, &got);
719 spin_unlock_irqrestore(&i2c->lock, flags);
722 dev_err(i2c->dev, "cannot find frequency\n");
724 dev_info(i2c->dev, "setting freq %d\n", got);
730 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
732 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
734 return cpufreq_register_notifier(&i2c->freq_transition,
735 CPUFREQ_TRANSITION_NOTIFIER);
738 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
740 cpufreq_unregister_notifier(&i2c->freq_transition,
741 CPUFREQ_TRANSITION_NOTIFIER);
745 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
750 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
756 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
760 for (idx = 0; idx < 2; idx++) {
761 gpio = of_get_gpio(i2c->dev->of_node, idx);
762 if (!gpio_is_valid(gpio)) {
763 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
767 ret = gpio_request(gpio, "i2c-bus");
769 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);
777 gpio_free(i2c->gpios[idx]);
781 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
784 for (idx = 0; idx < 2; idx++)
785 gpio_free(i2c->gpios[idx]);
788 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
793 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
800 * initialise the controller, set the IO lines and frequency
803 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
805 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
806 struct s3c2410_platform_i2c *pdata;
809 /* get the plafrom data */
813 /* inititalise the gpio */
816 pdata->cfg_gpio(to_platform_device(i2c->dev));
818 if (s3c24xx_i2c_parse_dt_gpio(i2c))
821 /* write slave address */
823 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
825 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
827 writel(iicon, i2c->regs + S3C2410_IICCON);
829 /* we need to work out the divisors for the clock... */
831 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
832 writel(0, i2c->regs + S3C2410_IICCON);
833 dev_err(i2c->dev, "cannot meet bus frequency required\n");
837 /* todo - check that the i2c lines aren't being dragged anywhere */
839 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
840 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
846 /* s3c24xx_i2c_parse_dt
848 * Parse the device tree node and retreive the platform data.
852 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
854 struct s3c2410_platform_i2c *pdata = i2c->pdata;
859 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
860 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
861 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
862 of_property_read_u32(np, "samsung,i2c-max-bus-freq",
863 (u32 *)&pdata->frequency);
867 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
875 * called by the bus driver when a suitable device is found
878 static int s3c24xx_i2c_probe(struct platform_device *pdev)
880 struct s3c24xx_i2c *i2c;
881 struct s3c2410_platform_i2c *pdata = NULL;
882 struct resource *res;
885 if (!pdev->dev.of_node) {
886 pdata = pdev->dev.platform_data;
888 dev_err(&pdev->dev, "no platform data\n");
893 i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
895 dev_err(&pdev->dev, "no memory for state\n");
899 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
906 memcpy(i2c->pdata, pdata, sizeof(*pdata));
908 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
910 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
911 i2c->adap.owner = THIS_MODULE;
912 i2c->adap.algo = &s3c24xx_i2c_algorithm;
913 i2c->adap.retries = 2;
914 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
917 spin_lock_init(&i2c->lock);
918 init_waitqueue_head(&i2c->wait);
920 /* find the clock and enable it */
922 i2c->dev = &pdev->dev;
923 i2c->clk = clk_get(&pdev->dev, "i2c");
924 if (IS_ERR(i2c->clk)) {
925 dev_err(&pdev->dev, "cannot get clock\n");
930 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
932 clk_enable(i2c->clk);
934 /* map the registers */
936 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
938 dev_err(&pdev->dev, "cannot find IO resource\n");
943 i2c->ioarea = request_mem_region(res->start, resource_size(res),
946 if (i2c->ioarea == NULL) {
947 dev_err(&pdev->dev, "cannot request IO\n");
952 i2c->regs = ioremap(res->start, resource_size(res));
954 if (i2c->regs == NULL) {
955 dev_err(&pdev->dev, "cannot map IO\n");
960 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
961 i2c->regs, i2c->ioarea, res);
963 /* setup info block for the i2c core */
965 i2c->adap.algo_data = i2c;
966 i2c->adap.dev.parent = &pdev->dev;
968 /* initialise the i2c controller */
970 ret = s3c24xx_i2c_init(i2c);
974 /* find the IRQ for this unit (note, this relies on the init call to
975 * ensure no current IRQs pending
978 i2c->irq = ret = platform_get_irq(pdev, 0);
980 dev_err(&pdev->dev, "cannot find IRQ\n");
984 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0,
985 dev_name(&pdev->dev), i2c);
988 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
992 ret = s3c24xx_i2c_register_cpufreq(i2c);
994 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
998 /* Note, previous versions of the driver used i2c_add_adapter()
999 * to add the bus at any number. We now pass the bus number via
1000 * the platform data, so if unset it will now default to always
1004 i2c->adap.nr = i2c->pdata->bus_num;
1005 i2c->adap.dev.of_node = pdev->dev.of_node;
1007 ret = i2c_add_numbered_adapter(&i2c->adap);
1009 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
1013 of_i2c_register_devices(&i2c->adap);
1014 platform_set_drvdata(pdev, i2c);
1016 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1017 clk_disable(i2c->clk);
1021 s3c24xx_i2c_deregister_cpufreq(i2c);
1024 free_irq(i2c->irq, i2c);
1030 release_resource(i2c->ioarea);
1034 clk_disable(i2c->clk);
1042 /* s3c24xx_i2c_remove
1044 * called when device is removed from the bus
1047 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1049 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1051 s3c24xx_i2c_deregister_cpufreq(i2c);
1053 i2c_del_adapter(&i2c->adap);
1054 free_irq(i2c->irq, i2c);
1056 clk_disable(i2c->clk);
1061 release_resource(i2c->ioarea);
1062 s3c24xx_i2c_dt_gpio_free(i2c);
1070 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1072 struct platform_device *pdev = to_platform_device(dev);
1073 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1080 static int s3c24xx_i2c_resume(struct device *dev)
1082 struct platform_device *pdev = to_platform_device(dev);
1083 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1086 clk_enable(i2c->clk);
1087 s3c24xx_i2c_init(i2c);
1088 clk_disable(i2c->clk);
1093 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1094 .suspend_noirq = s3c24xx_i2c_suspend_noirq,
1095 .resume = s3c24xx_i2c_resume,
1098 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1100 #define S3C24XX_DEV_PM_OPS NULL
1103 /* device driver for platform bus bits */
1105 static struct platform_device_id s3c24xx_driver_ids[] = {
1107 .name = "s3c2410-i2c",
1108 .driver_data = TYPE_S3C2410,
1110 .name = "s3c2440-i2c",
1111 .driver_data = TYPE_S3C2440,
1114 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1117 static const struct of_device_id s3c24xx_i2c_match[] = {
1118 { .compatible = "samsung,s3c2410-i2c" },
1119 { .compatible = "samsung,s3c2440-i2c" },
1122 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
1124 #define s3c24xx_i2c_match NULL
1127 static struct platform_driver s3c24xx_i2c_driver = {
1128 .probe = s3c24xx_i2c_probe,
1129 .remove = s3c24xx_i2c_remove,
1130 .id_table = s3c24xx_driver_ids,
1132 .owner = THIS_MODULE,
1134 .pm = S3C24XX_DEV_PM_OPS,
1135 .of_match_table = s3c24xx_i2c_match,
1139 static int __init i2c_adap_s3c_init(void)
1141 return platform_driver_register(&s3c24xx_i2c_driver);
1143 subsys_initcall(i2c_adap_s3c_init);
1145 static void __exit i2c_adap_s3c_exit(void)
1147 platform_driver_unregister(&s3c24xx_i2c_driver);
1149 module_exit(i2c_adap_s3c_exit);
1151 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1152 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1153 MODULE_LICENSE("GPL");