1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
4 * Copyright (C) 2004,2005,2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
7 * S3C2410 I2C Controller
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/time.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/clk.h>
23 #include <linux/cpufreq.h>
24 #include <linux/slab.h>
27 #include <linux/gpio/consumer.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
36 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
38 #define S3C2410_IICCON 0x00
39 #define S3C2410_IICSTAT 0x04
40 #define S3C2410_IICADD 0x08
41 #define S3C2410_IICDS 0x0C
42 #define S3C2440_IICLC 0x10
44 #define S3C2410_IICCON_ACKEN (1 << 7)
45 #define S3C2410_IICCON_TXDIV_16 (0 << 6)
46 #define S3C2410_IICCON_TXDIV_512 (1 << 6)
47 #define S3C2410_IICCON_IRQEN (1 << 5)
48 #define S3C2410_IICCON_IRQPEND (1 << 4)
49 #define S3C2410_IICCON_SCALE(x) ((x) & 0xf)
50 #define S3C2410_IICCON_SCALEMASK (0xf)
52 #define S3C2410_IICSTAT_MASTER_RX (2 << 6)
53 #define S3C2410_IICSTAT_MASTER_TX (3 << 6)
54 #define S3C2410_IICSTAT_SLAVE_RX (0 << 6)
55 #define S3C2410_IICSTAT_SLAVE_TX (1 << 6)
56 #define S3C2410_IICSTAT_MODEMASK (3 << 6)
58 #define S3C2410_IICSTAT_START (1 << 5)
59 #define S3C2410_IICSTAT_BUSBUSY (1 << 5)
60 #define S3C2410_IICSTAT_TXRXEN (1 << 4)
61 #define S3C2410_IICSTAT_ARBITR (1 << 3)
62 #define S3C2410_IICSTAT_ASSLAVE (1 << 2)
63 #define S3C2410_IICSTAT_ADDR0 (1 << 1)
64 #define S3C2410_IICSTAT_LASTBIT (1 << 0)
66 #define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
67 #define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
68 #define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
69 #define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
70 #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
72 #define S3C2410_IICLC_FILTER_ON (1 << 2)
74 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
75 #define QUIRK_S3C2440 (1 << 0)
76 #define QUIRK_HDMIPHY (1 << 1)
77 #define QUIRK_NO_GPIO (1 << 2)
78 #define QUIRK_POLL (1 << 3)
80 /* Max time to wait for bus to become idle after a xfer (in us) */
81 #define S3C2410_IDLE_TIMEOUT 5000
83 /* Exynos5 Sysreg offset */
84 #define EXYNOS5_SYS_I2C_CFG 0x0234
86 /* i2c controller state */
87 enum s3c24xx_i2c_state {
96 wait_queue_head_t wait;
97 kernel_ulong_t quirks;
100 unsigned int msg_num;
101 unsigned int msg_idx;
102 unsigned int msg_ptr;
104 unsigned int tx_setup;
107 enum s3c24xx_i2c_state state;
108 unsigned long clkrate;
113 struct i2c_adapter adap;
115 struct s3c2410_platform_i2c *pdata;
116 struct gpio_desc *gpios[2];
117 struct pinctrl *pctrl;
118 struct regmap *sysreg;
119 unsigned int sys_i2c_cfg;
122 static const struct platform_device_id s3c24xx_driver_ids[] = {
124 .name = "s3c2410-i2c",
127 .name = "s3c2440-i2c",
128 .driver_data = QUIRK_S3C2440,
130 .name = "s3c2440-hdmiphy-i2c",
131 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
134 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
136 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
139 static const struct of_device_id s3c24xx_i2c_match[] = {
140 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
141 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
142 { .compatible = "samsung,s3c2440-hdmiphy-i2c",
143 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
144 { .compatible = "samsung,exynos5-sata-phy-i2c",
145 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
148 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
152 * Get controller type either from device tree or platform device variant.
154 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
156 if (pdev->dev.of_node)
157 return (kernel_ulong_t)of_device_get_match_data(&pdev->dev);
159 return platform_get_device_id(pdev)->driver_data;
163 * Complete the message and wake up the caller, using the given return code,
164 * or zero to mean ok.
166 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
168 dev_dbg(i2c->dev, "master_complete %d\n", ret);
177 if (!(i2c->quirks & QUIRK_POLL))
181 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
185 tmp = readl(i2c->regs + S3C2410_IICCON);
186 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
189 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
193 tmp = readl(i2c->regs + S3C2410_IICCON);
194 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
197 /* irq enable/disable functions */
198 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
202 tmp = readl(i2c->regs + S3C2410_IICCON);
203 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
206 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
210 tmp = readl(i2c->regs + S3C2410_IICCON);
211 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
214 static bool is_ack(struct s3c24xx_i2c *i2c)
218 for (tries = 50; tries; --tries) {
219 if (readl(i2c->regs + S3C2410_IICCON)
220 & S3C2410_IICCON_IRQPEND) {
221 if (!(readl(i2c->regs + S3C2410_IICSTAT)
222 & S3C2410_IICSTAT_LASTBIT))
225 usleep_range(1000, 2000);
227 dev_err(i2c->dev, "ack was not received\n");
232 * put the start of a message onto the bus
234 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
237 unsigned int addr = (msg->addr & 0x7f) << 1;
239 unsigned long iiccon;
242 stat |= S3C2410_IICSTAT_TXRXEN;
244 if (msg->flags & I2C_M_RD) {
245 stat |= S3C2410_IICSTAT_MASTER_RX;
248 stat |= S3C2410_IICSTAT_MASTER_TX;
250 if (msg->flags & I2C_M_REV_DIR_ADDR)
253 /* todo - check for whether ack wanted or not */
254 s3c24xx_i2c_enable_ack(i2c);
256 iiccon = readl(i2c->regs + S3C2410_IICCON);
257 writel(stat, i2c->regs + S3C2410_IICSTAT);
259 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
260 writeb(addr, i2c->regs + S3C2410_IICDS);
263 * delay here to ensure the data byte has gotten onto the bus
264 * before the transaction is started
266 ndelay(i2c->tx_setup);
268 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
269 writel(iiccon, i2c->regs + S3C2410_IICCON);
271 stat |= S3C2410_IICSTAT_START;
272 writel(stat, i2c->regs + S3C2410_IICSTAT);
274 if (i2c->quirks & QUIRK_POLL) {
275 while ((i2c->msg_num != 0) && is_ack(i2c)) {
276 i2c_s3c_irq_nextbyte(i2c, stat);
277 stat = readl(i2c->regs + S3C2410_IICSTAT);
279 if (stat & S3C2410_IICSTAT_ARBITR)
280 dev_err(i2c->dev, "deal with arbitration loss\n");
285 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
287 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
289 dev_dbg(i2c->dev, "STOP\n");
292 * The datasheet says that the STOP sequence should be:
293 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
294 * 2) I2CCON.4 = 0 - Clear IRQPEND
295 * 3) Wait until the stop condition takes effect.
296 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN
298 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
300 * However, after much experimentation, it appears that:
301 * a) normal buses automatically clear BUSY and transition from
302 * Master->Slave when they complete generating a STOP condition.
303 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4
304 * after starting the STOP generation here.
305 * b) HDMIPHY bus does neither, so there is no way to do step 3.
306 * There is no indication when this bus has finished generating
309 * In fact, we have found that as soon as the IRQPEND bit is cleared in
310 * step 2, the HDMIPHY bus generates the STOP condition, and then
311 * immediately starts transferring another data byte, even though the
312 * bus is supposedly stopped. This is presumably because the bus is
313 * still in "Master" mode, and its BUSY bit is still set.
315 * To avoid these extra post-STOP transactions on HDMI phy devices, we
316 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
317 * instead of first generating a proper STOP condition. This should
318 * float SDA & SCK terminating the transfer. Subsequent transfers
319 * start with a proper START condition, and proceed normally.
321 * The HDMIPHY bus is an internal bus that always has exactly two
322 * devices, the host as Master and the HDMIPHY device as the slave.
323 * Skipping the STOP condition has been tested on this bus and works.
325 if (i2c->quirks & QUIRK_HDMIPHY) {
326 /* Stop driving the I2C pins */
327 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
329 /* stop the transfer */
330 iicstat &= ~S3C2410_IICSTAT_START;
332 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
334 i2c->state = STATE_STOP;
336 s3c24xx_i2c_master_complete(i2c, ret);
337 s3c24xx_i2c_disable_irq(i2c);
341 * helper functions to determine the current state in the set of
342 * messages we are sending
346 * returns TRUE if the current message is the last in the set
348 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
350 return i2c->msg_idx >= (i2c->msg_num - 1);
354 * returns TRUE if we this is the last byte in the current message
356 static inline int is_msglast(struct s3c24xx_i2c *i2c)
359 * msg->len is always 1 for the first byte of smbus block read.
360 * Actual length will be read from slave. More bytes will be
361 * read according to the length then.
363 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
366 return i2c->msg_ptr == i2c->msg->len-1;
370 * returns TRUE if we reached the end of the current message
372 static inline int is_msgend(struct s3c24xx_i2c *i2c)
374 return i2c->msg_ptr >= i2c->msg->len;
378 * process an interrupt and work out what to do
380 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
386 switch (i2c->state) {
389 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
393 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
394 s3c24xx_i2c_disable_irq(i2c);
399 * last thing we did was send a start condition on the
400 * bus, or started a new i2c message
402 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
403 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
404 /* ack was not received... */
405 dev_dbg(i2c->dev, "ack was not received\n");
406 s3c24xx_i2c_stop(i2c, -ENXIO);
410 if (i2c->msg->flags & I2C_M_RD)
411 i2c->state = STATE_READ;
413 i2c->state = STATE_WRITE;
416 * Terminate the transfer if there is nothing to do
417 * as this is used by the i2c probe to find devices.
419 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
420 s3c24xx_i2c_stop(i2c, 0);
424 if (i2c->state == STATE_READ)
428 * fall through to the write state, as we will need to
429 * send a byte as well
434 * we are writing data to the device... check for the
435 * end of the message, and if so, work out what to do
437 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
438 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
439 dev_dbg(i2c->dev, "WRITE: No Ack\n");
441 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
448 if (!is_msgend(i2c)) {
449 byte = i2c->msg->buf[i2c->msg_ptr++];
450 writeb(byte, i2c->regs + S3C2410_IICDS);
453 * delay after writing the byte to allow the
454 * data setup time on the bus, as writing the
455 * data to the register causes the first bit
456 * to appear on SDA, and SCL will change as
457 * soon as the interrupt is acknowledged
459 ndelay(i2c->tx_setup);
461 } else if (!is_lastmsg(i2c)) {
462 /* we need to go to the next i2c message */
464 dev_dbg(i2c->dev, "WRITE: Next Message\n");
470 /* check to see if we need to do another message */
471 if (i2c->msg->flags & I2C_M_NOSTART) {
473 if (i2c->msg->flags & I2C_M_RD) {
475 * cannot do this, the controller
476 * forces us to send a new START
477 * when we change direction
480 "missing START before write->read\n");
481 s3c24xx_i2c_stop(i2c, -EINVAL);
487 /* send the new start */
488 s3c24xx_i2c_message_start(i2c, i2c->msg);
489 i2c->state = STATE_START;
494 s3c24xx_i2c_stop(i2c, 0);
500 * we have a byte of data in the data register, do
501 * something with it, and then work out whether we are
502 * going to do any more read/write
504 byte = readb(i2c->regs + S3C2410_IICDS);
505 i2c->msg->buf[i2c->msg_ptr++] = byte;
507 /* Add actual length to read for smbus block read */
508 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
509 i2c->msg->len += byte;
511 if (is_msglast(i2c)) {
512 /* last byte of buffer */
515 s3c24xx_i2c_disable_ack(i2c);
517 } else if (is_msgend(i2c)) {
519 * ok, we've read the entire buffer, see if there
520 * is anything else we need to do
522 if (is_lastmsg(i2c)) {
523 /* last message, send stop and complete */
524 dev_dbg(i2c->dev, "READ: Send Stop\n");
526 s3c24xx_i2c_stop(i2c, 0);
528 /* go to the next transfer */
529 dev_dbg(i2c->dev, "READ: Next Transfer\n");
540 /* acknowlegde the IRQ and get back on with the work */
543 tmp = readl(i2c->regs + S3C2410_IICCON);
544 tmp &= ~S3C2410_IICCON_IRQPEND;
545 writel(tmp, i2c->regs + S3C2410_IICCON);
551 * top level IRQ servicing routine
553 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
555 struct s3c24xx_i2c *i2c = dev_id;
556 unsigned long status;
559 status = readl(i2c->regs + S3C2410_IICSTAT);
561 if (status & S3C2410_IICSTAT_ARBITR) {
562 /* deal with arbitration loss */
563 dev_err(i2c->dev, "deal with arbitration loss\n");
566 if (i2c->state == STATE_IDLE) {
567 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
569 tmp = readl(i2c->regs + S3C2410_IICCON);
570 tmp &= ~S3C2410_IICCON_IRQPEND;
571 writel(tmp, i2c->regs + S3C2410_IICCON);
576 * pretty much this leaves us with the fact that we've
577 * transmitted or received whatever byte we last sent
579 i2c_s3c_irq_nextbyte(i2c, status);
586 * Disable the bus so that we won't get any interrupts from now on, or try
587 * to drive any lines. This is the default state when we don't have
588 * anything to send/receive.
590 * If there is an event on the bus, or we have a pre-existing event at
591 * kernel boot time, we may not notice the event and the I2C controller
592 * will lock the bus with the I2C clock line low indefinitely.
594 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
598 /* Stop driving the I2C pins */
599 tmp = readl(i2c->regs + S3C2410_IICSTAT);
600 tmp &= ~S3C2410_IICSTAT_TXRXEN;
601 writel(tmp, i2c->regs + S3C2410_IICSTAT);
603 /* We don't expect any interrupts now, and don't want send acks */
604 tmp = readl(i2c->regs + S3C2410_IICCON);
605 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
606 S3C2410_IICCON_ACKEN);
607 writel(tmp, i2c->regs + S3C2410_IICCON);
612 * get the i2c bus for a master transaction
614 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
616 unsigned long iicstat;
619 while (timeout-- > 0) {
620 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
622 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
632 * wait for the i2c bus to become idle.
634 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
636 unsigned long iicstat;
641 /* ensure the stop has been through the bus */
643 dev_dbg(i2c->dev, "waiting for bus idle\n");
645 start = now = ktime_get();
648 * Most of the time, the bus is already idle within a few usec of the
649 * end of a transaction. However, really slow i2c devices can stretch
650 * the clock, delaying STOP generation.
652 * On slower SoCs this typically happens within a very small number of
653 * instructions so busy wait briefly to avoid scheduling overhead.
656 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
657 while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
659 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
663 * If we do get an appreciable delay as a compromise between idle
664 * detection latency for the normal, fast case, and system load in the
665 * slow device case, use an exponential back off in the polling loop,
666 * up to 1/10th of the total timeout, then continue to poll at a
667 * constant rate up to the timeout.
670 while ((iicstat & S3C2410_IICSTAT_START) &&
671 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
672 usleep_range(delay, 2 * delay);
673 if (delay < S3C2410_IDLE_TIMEOUT / 10)
676 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
679 if (iicstat & S3C2410_IICSTAT_START)
680 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
684 * this starts an i2c transfer
686 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
687 struct i2c_msg *msgs, int num)
689 unsigned long timeout;
692 ret = s3c24xx_i2c_set_master(i2c);
694 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
703 i2c->state = STATE_START;
705 s3c24xx_i2c_enable_irq(i2c);
706 s3c24xx_i2c_message_start(i2c, msgs);
708 if (i2c->quirks & QUIRK_POLL) {
712 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
717 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
722 * Having these next two as dev_err() makes life very
723 * noisy when doing an i2cdetect
726 dev_dbg(i2c->dev, "timeout\n");
728 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
730 /* For QUIRK_HDMIPHY, bus is already disabled */
731 if (i2c->quirks & QUIRK_HDMIPHY)
734 s3c24xx_i2c_wait_idle(i2c);
736 s3c24xx_i2c_disable_bus(i2c);
739 i2c->state = STATE_IDLE;
745 * first port of call from the i2c bus code when an message needs
746 * transferring across the i2c bus.
748 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
749 struct i2c_msg *msgs, int num)
751 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
755 ret = clk_enable(i2c->clk);
759 for (retry = 0; retry < adap->retries; retry++) {
761 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
763 if (ret != -EAGAIN) {
764 clk_disable(i2c->clk);
768 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
773 clk_disable(i2c->clk);
777 /* declare our i2c functionality */
778 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
780 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL_ALL | I2C_FUNC_NOSTART |
781 I2C_FUNC_PROTOCOL_MANGLING;
784 /* i2c bus registration info */
785 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
786 .master_xfer = s3c24xx_i2c_xfer,
787 .functionality = s3c24xx_i2c_func,
791 * return the divisor settings for a given frequency
793 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
794 unsigned int *div1, unsigned int *divs)
796 unsigned int calc_divs = clkin / wanted;
797 unsigned int calc_div1;
799 if (calc_divs > (16*16))
804 calc_divs += calc_div1-1;
805 calc_divs /= calc_div1;
815 return clkin / (calc_divs * calc_div1);
819 * work out a divisor for the user requested frequency setting,
820 * either by the requested frequency, or scanning the acceptable
821 * range of frequencies until something is found
823 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
825 struct s3c2410_platform_i2c *pdata = i2c->pdata;
826 unsigned long clkin = clk_get_rate(i2c->clk);
827 unsigned int divs, div1;
828 unsigned long target_frequency;
832 i2c->clkrate = clkin;
833 clkin /= 1000; /* clkin now in KHz */
835 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
837 target_frequency = pdata->frequency ?: I2C_MAX_STANDARD_MODE_FREQ;
839 target_frequency /= 1000; /* Target frequency now in KHz */
841 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
843 if (freq > target_frequency) {
845 "Unable to achieve desired frequency %luKHz." \
846 " Lowest achievable %dKHz\n", target_frequency, freq);
852 iiccon = readl(i2c->regs + S3C2410_IICCON);
853 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
857 iiccon |= S3C2410_IICCON_TXDIV_512;
859 if (i2c->quirks & QUIRK_POLL)
860 iiccon |= S3C2410_IICCON_SCALE(2);
862 writel(iiccon, i2c->regs + S3C2410_IICCON);
864 if (i2c->quirks & QUIRK_S3C2440) {
865 unsigned long sda_delay;
867 if (pdata->sda_delay) {
868 sda_delay = clkin * pdata->sda_delay;
869 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
870 sda_delay = DIV_ROUND_UP(sda_delay, 5);
873 sda_delay |= S3C2410_IICLC_FILTER_ON;
877 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
878 writel(sda_delay, i2c->regs + S3C2440_IICLC);
885 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
889 if (i2c->quirks & QUIRK_NO_GPIO)
892 for (i = 0; i < 2; i++) {
893 i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL,
895 if (IS_ERR(i2c->gpios[i])) {
896 dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i);
904 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
911 * initialise the controller, set the IO lines and frequency
913 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
915 struct s3c2410_platform_i2c *pdata;
918 /* get the plafrom data */
922 /* write slave address */
924 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
926 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
928 writel(0, i2c->regs + S3C2410_IICCON);
929 writel(0, i2c->regs + S3C2410_IICSTAT);
931 /* we need to work out the divisors for the clock... */
933 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
934 dev_err(i2c->dev, "cannot meet bus frequency required\n");
938 /* todo - check that the i2c lines aren't being dragged anywhere */
940 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
941 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
942 readl(i2c->regs + S3C2410_IICCON));
949 * Parse the device tree node and retreive the platform data.
952 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
954 struct s3c2410_platform_i2c *pdata = i2c->pdata;
960 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
961 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
962 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
963 of_property_read_u32(np, "samsung,i2c-max-bus-freq",
964 (u32 *)&pdata->frequency);
966 * Exynos5's legacy i2c controller and new high speed i2c
967 * controller have muxed interrupt sources. By default the
968 * interrupts for 4-channel HS-I2C controller are enabled.
969 * If nodes for first four channels of legacy i2c controller
970 * are available then re-configure the interrupts via the
973 id = of_alias_get_id(np, "i2c");
974 i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
975 "samsung,sysreg-phandle");
976 if (IS_ERR(i2c->sysreg))
979 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
983 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
986 static int s3c24xx_i2c_probe(struct platform_device *pdev)
988 struct s3c24xx_i2c *i2c;
989 struct s3c2410_platform_i2c *pdata = NULL;
990 struct resource *res;
993 if (!pdev->dev.of_node) {
994 pdata = dev_get_platdata(&pdev->dev);
996 dev_err(&pdev->dev, "no platform data\n");
1001 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1005 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1009 i2c->quirks = s3c24xx_get_device_quirks(pdev);
1010 i2c->sysreg = ERR_PTR(-ENOENT);
1012 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1014 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1016 strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1017 i2c->adap.owner = THIS_MODULE;
1018 i2c->adap.algo = &s3c24xx_i2c_algorithm;
1019 i2c->adap.retries = 2;
1020 i2c->adap.class = I2C_CLASS_DEPRECATED;
1023 init_waitqueue_head(&i2c->wait);
1025 /* find the clock and enable it */
1026 i2c->dev = &pdev->dev;
1027 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1028 if (IS_ERR(i2c->clk)) {
1029 dev_err(&pdev->dev, "cannot get clock\n");
1033 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1035 /* map the registers */
1036 i2c->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1037 if (IS_ERR(i2c->regs))
1038 return PTR_ERR(i2c->regs);
1040 dev_dbg(&pdev->dev, "registers %p (%p)\n",
1043 /* setup info block for the i2c core */
1044 i2c->adap.algo_data = i2c;
1045 i2c->adap.dev.parent = &pdev->dev;
1046 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1048 /* inititalise the i2c gpio lines */
1049 if (i2c->pdata->cfg_gpio)
1050 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1051 else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1054 /* initialise the i2c controller */
1055 ret = clk_prepare_enable(i2c->clk);
1057 dev_err(&pdev->dev, "I2C clock enable failed\n");
1061 ret = s3c24xx_i2c_init(i2c);
1062 clk_disable(i2c->clk);
1064 dev_err(&pdev->dev, "I2C controller init failed\n");
1065 clk_unprepare(i2c->clk);
1070 * find the IRQ for this unit (note, this relies on the init call to
1071 * ensure no current IRQs pending
1073 if (!(i2c->quirks & QUIRK_POLL)) {
1074 i2c->irq = ret = platform_get_irq(pdev, 0);
1076 clk_unprepare(i2c->clk);
1080 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1081 0, dev_name(&pdev->dev), i2c);
1083 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1084 clk_unprepare(i2c->clk);
1090 * Note, previous versions of the driver used i2c_add_adapter()
1091 * to add the bus at any number. We now pass the bus number via
1092 * the platform data, so if unset it will now default to always
1095 i2c->adap.nr = i2c->pdata->bus_num;
1096 i2c->adap.dev.of_node = pdev->dev.of_node;
1098 platform_set_drvdata(pdev, i2c);
1100 pm_runtime_enable(&pdev->dev);
1102 ret = i2c_add_numbered_adapter(&i2c->adap);
1104 pm_runtime_disable(&pdev->dev);
1105 clk_unprepare(i2c->clk);
1109 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1113 static void s3c24xx_i2c_remove(struct platform_device *pdev)
1115 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1117 clk_unprepare(i2c->clk);
1119 pm_runtime_disable(&pdev->dev);
1121 i2c_del_adapter(&i2c->adap);
1124 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1126 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1128 i2c_mark_adapter_suspended(&i2c->adap);
1130 if (!IS_ERR(i2c->sysreg))
1131 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1136 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1138 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1141 if (!IS_ERR(i2c->sysreg))
1142 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1144 ret = clk_enable(i2c->clk);
1147 s3c24xx_i2c_init(i2c);
1148 clk_disable(i2c->clk);
1149 i2c_mark_adapter_resumed(&i2c->adap);
1154 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1155 NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1156 s3c24xx_i2c_resume_noirq)
1159 static struct platform_driver s3c24xx_i2c_driver = {
1160 .probe = s3c24xx_i2c_probe,
1161 .remove_new = s3c24xx_i2c_remove,
1162 .id_table = s3c24xx_driver_ids,
1165 .pm = pm_sleep_ptr(&s3c24xx_i2c_dev_pm_ops),
1166 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1170 static int __init i2c_adap_s3c_init(void)
1172 return platform_driver_register(&s3c24xx_i2c_driver);
1174 subsys_initcall(i2c_adap_s3c_init);
1176 static void __exit i2c_adap_s3c_exit(void)
1178 platform_driver_unregister(&s3c24xx_i2c_driver);
1180 module_exit(i2c_adap_s3c_exit);
1182 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1183 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1184 MODULE_LICENSE("GPL");