drivers/i2c/busses/i2c-s3c2410.c

   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005,2009 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17 */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21
  22 #include <linux/i2c.h>
  23 #include <linux/init.h>
  24 #include <linux/time.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/err.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/clk.h>
  32 #include <linux/cpufreq.h>
  33 #include <linux/slab.h>
  34 #include <linux/io.h>
  35 #include <linux/of.h>
  36 #include <linux/of_gpio.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <asm/irq.h>
  40
  41 #include <linux/platform_data/i2c-s3c2410.h>
  42
  43 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
  44
  45 #define S3C2410_IICCON                  0x00
  46 #define S3C2410_IICSTAT                 0x04
  47 #define S3C2410_IICADD                  0x08
  48 #define S3C2410_IICDS                   0x0C
  49 #define S3C2440_IICLC                   0x10
  50
  51 #define S3C2410_IICCON_ACKEN            (1 << 7)
  52 #define S3C2410_IICCON_TXDIV_16         (0 << 6)
  53 #define S3C2410_IICCON_TXDIV_512        (1 << 6)
  54 #define S3C2410_IICCON_IRQEN            (1 << 5)
  55 #define S3C2410_IICCON_IRQPEND          (1 << 4)
  56 #define S3C2410_IICCON_SCALE(x)         ((x) & 0xf)
  57 #define S3C2410_IICCON_SCALEMASK        (0xf)
  58
  59 #define S3C2410_IICSTAT_MASTER_RX       (2 << 6)
  60 #define S3C2410_IICSTAT_MASTER_TX       (3 << 6)
  61 #define S3C2410_IICSTAT_SLAVE_RX        (0 << 6)
  62 #define S3C2410_IICSTAT_SLAVE_TX        (1 << 6)
  63 #define S3C2410_IICSTAT_MODEMASK        (3 << 6)
  64
  65 #define S3C2410_IICSTAT_START           (1 << 5)
  66 #define S3C2410_IICSTAT_BUSBUSY         (1 << 5)
  67 #define S3C2410_IICSTAT_TXRXEN          (1 << 4)
  68 #define S3C2410_IICSTAT_ARBITR          (1 << 3)
  69 #define S3C2410_IICSTAT_ASSLAVE         (1 << 2)
  70 #define S3C2410_IICSTAT_ADDR0           (1 << 1)
  71 #define S3C2410_IICSTAT_LASTBIT         (1 << 0)
  72
  73 #define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
  74 #define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
  75 #define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
  76 #define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
  77 #define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
  78
  79 #define S3C2410_IICLC_FILTER_ON         (1 << 2)
  80
  81 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
  82 #define QUIRK_S3C2440           (1 << 0)
  83 #define QUIRK_HDMIPHY           (1 << 1)
  84 #define QUIRK_NO_GPIO           (1 << 2)
  85 #define QUIRK_POLL              (1 << 3)
  86
  87 /* Max time to wait for bus to become idle after a xfer (in us) */
  88 #define S3C2410_IDLE_TIMEOUT    5000
  89
  90 /* i2c controller state */
  91 enum s3c24xx_i2c_state {
  92         STATE_IDLE,
  93         STATE_START,
  94         STATE_READ,
  95         STATE_WRITE,
  96         STATE_STOP
  97 };
  98
  99 struct s3c24xx_i2c {
 100         wait_queue_head_t       wait;
 101         kernel_ulong_t          quirks;
 102         unsigned int            suspended:1;
 103
 104         struct i2c_msg          *msg;
 105         unsigned int            msg_num;
 106         unsigned int            msg_idx;
 107         unsigned int            msg_ptr;
 108
 109         unsigned int            tx_setup;
 110         unsigned int            irq;
 111
 112         enum s3c24xx_i2c_state  state;
 113         unsigned long           clkrate;
 114
 115         void __iomem            *regs;
 116         struct clk              *clk;
 117         struct device           *dev;
 118         struct i2c_adapter      adap;
 119
 120         struct s3c2410_platform_i2c     *pdata;
 121         int                     gpios[2];
 122         struct pinctrl          *pctrl;
 123 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 124         struct notifier_block   freq_transition;
 125 #endif
 126 };
 127
 128 static struct platform_device_id s3c24xx_driver_ids[] = {
 129         {
 130                 .name           = "s3c2410-i2c",
 131                 .driver_data    = 0,
 132         }, {
 133                 .name           = "s3c2440-i2c",
 134                 .driver_data    = QUIRK_S3C2440,
 135         }, {
 136                 .name           = "s3c2440-hdmiphy-i2c",
 137                 .driver_data    = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
 138         }, { },
 139 };
 140 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 141
 142 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
 143
 144 #ifdef CONFIG_OF
 145 static const struct of_device_id s3c24xx_i2c_match[] = {
 146         { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
 147         { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
 148         { .compatible = "samsung,s3c2440-hdmiphy-i2c",
 149           .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
 150         { .compatible = "samsung,exynos5440-i2c",
 151           .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
 152         { .compatible = "samsung,exynos5-sata-phy-i2c",
 153           .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
 154         {},
 155 };
 156 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
 157 #endif
 158
 159 /* s3c24xx_get_device_quirks
 160  *
 161  * Get controller type either from device tree or platform device variant.
 162 */
 163
 164 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
 165 {
 166         if (pdev->dev.of_node) {
 167                 const struct of_device_id *match;
 168                 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
 169                 return (kernel_ulong_t)match->data;
 170         }
 171
 172         return platform_get_device_id(pdev)->driver_data;
 173 }
 174
 175 /* s3c24xx_i2c_master_complete
 176  *
 177  * complete the message and wake up the caller, using the given return code,
 178  * or zero to mean ok.
 179 */
 180
 181 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 182 {
 183         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 184
 185         i2c->msg_ptr = 0;
 186         i2c->msg = NULL;
 187         i2c->msg_idx++;
 188         i2c->msg_num = 0;
 189         if (ret)
 190                 i2c->msg_idx = ret;
 191
 192         if (!(i2c->quirks & QUIRK_POLL))
 193                 wake_up(&i2c->wait);
 194 }
 195
 196 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 197 {
 198         unsigned long tmp;
 199
 200         tmp = readl(i2c->regs + S3C2410_IICCON);
 201         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 202 }
 203
 204 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 205 {
 206         unsigned long tmp;
 207
 208         tmp = readl(i2c->regs + S3C2410_IICCON);
 209         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 210 }
 211
 212 /* irq enable/disable functions */
 213
 214 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 215 {
 216         unsigned long tmp;
 217
 218         tmp = readl(i2c->regs + S3C2410_IICCON);
 219         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 220 }
 221
 222 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 223 {
 224         unsigned long tmp;
 225
 226         tmp = readl(i2c->regs + S3C2410_IICCON);
 227         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 228 }
 229
 230 static bool is_ack(struct s3c24xx_i2c *i2c)
 231 {
 232         int tries;
 233
 234         for (tries = 50; tries; --tries) {
 235                 if (readl(i2c->regs + S3C2410_IICCON)
 236                         & S3C2410_IICCON_IRQPEND) {
 237                         if (!(readl(i2c->regs + S3C2410_IICSTAT)
 238                                 & S3C2410_IICSTAT_LASTBIT))
 239                                 return true;
 240                 }
 241                 usleep_range(1000, 2000);
 242         }
 243         dev_err(i2c->dev, "ack was not recieved\n");
 244         return false;
 245 }
 246
 247 /* s3c24xx_i2c_message_start
 248  *
 249  * put the start of a message onto the bus
 250 */
 251
 252 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 253                                       struct i2c_msg *msg)
 254 {
 255         unsigned int addr = (msg->addr & 0x7f) << 1;
 256         unsigned long stat;
 257         unsigned long iiccon;
 258
 259         stat = 0;
 260         stat |=  S3C2410_IICSTAT_TXRXEN;
 261
 262         if (msg->flags & I2C_M_RD) {
 263                 stat |= S3C2410_IICSTAT_MASTER_RX;
 264                 addr |= 1;
 265         } else
 266                 stat |= S3C2410_IICSTAT_MASTER_TX;
 267
 268         if (msg->flags & I2C_M_REV_DIR_ADDR)
 269                 addr ^= 1;
 270
 271         /* todo - check for whether ack wanted or not */
 272         s3c24xx_i2c_enable_ack(i2c);
 273
 274         iiccon = readl(i2c->regs + S3C2410_IICCON);
 275         writel(stat, i2c->regs + S3C2410_IICSTAT);
 276
 277         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 278         writeb(addr, i2c->regs + S3C2410_IICDS);
 279
 280         /* delay here to ensure the data byte has gotten onto the bus
 281          * before the transaction is started */
 282
 283         ndelay(i2c->tx_setup);
 284
 285         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 286         writel(iiccon, i2c->regs + S3C2410_IICCON);
 287
 288         stat |= S3C2410_IICSTAT_START;
 289         writel(stat, i2c->regs + S3C2410_IICSTAT);
 290
 291         if (i2c->quirks & QUIRK_POLL) {
 292                 while ((i2c->msg_num != 0) && is_ack(i2c)) {
 293                         i2c_s3c_irq_nextbyte(i2c, stat);
 294                         stat = readl(i2c->regs + S3C2410_IICSTAT);
 295
 296                         if (stat & S3C2410_IICSTAT_ARBITR)
 297                                 dev_err(i2c->dev, "deal with arbitration loss\n");
 298                 }
 299         }
 300 }
 301
 302 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 303 {
 304         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 305
 306         dev_dbg(i2c->dev, "STOP\n");
 307
 308         /*
 309          * The datasheet says that the STOP sequence should be:
 310          *  1) I2CSTAT.5 = 0    - Clear BUSY (or 'generate STOP')
 311          *  2) I2CCON.4 = 0     - Clear IRQPEND
 312          *  3) Wait until the stop condition takes effect.
 313          *  4*) I2CSTAT.4 = 0   - Clear TXRXEN
 314          *
 315          * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
 316          *
 317          * However, after much experimentation, it appears that:
 318          * a) normal buses automatically clear BUSY and transition from
 319          *    Master->Slave when they complete generating a STOP condition.
 320          *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
 321          *    after starting the STOP generation here.
 322          * b) HDMIPHY bus does neither, so there is no way to do step 3.
 323          *    There is no indication when this bus has finished generating
 324          *    STOP.
 325          *
 326          * In fact, we have found that as soon as the IRQPEND bit is cleared in
 327          * step 2, the HDMIPHY bus generates the STOP condition, and then
 328          * immediately starts transferring another data byte, even though the
 329          * bus is supposedly stopped.  This is presumably because the bus is
 330          * still in "Master" mode, and its BUSY bit is still set.
 331          *
 332          * To avoid these extra post-STOP transactions on HDMI phy devices, we
 333          * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
 334          * instead of first generating a proper STOP condition.  This should
 335          * float SDA & SCK terminating the transfer.  Subsequent transfers
 336          *  start with a proper START condition, and proceed normally.
 337          *
 338          * The HDMIPHY bus is an internal bus that always has exactly two
 339          * devices, the host as Master and the HDMIPHY device as the slave.
 340          * Skipping the STOP condition has been tested on this bus and works.
 341          */
 342         if (i2c->quirks & QUIRK_HDMIPHY) {
 343                 /* Stop driving the I2C pins */
 344                 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
 345         } else {
 346                 /* stop the transfer */
 347                 iicstat &= ~S3C2410_IICSTAT_START;
 348         }
 349         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 350
 351         i2c->state = STATE_STOP;
 352
 353         s3c24xx_i2c_master_complete(i2c, ret);
 354         s3c24xx_i2c_disable_irq(i2c);
 355 }
 356
 357 /* helper functions to determine the current state in the set of
 358  * messages we are sending */
 359
 360 /* is_lastmsg()
 361  *
 362  * returns TRUE if the current message is the last in the set
 363 */
 364
 365 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 366 {
 367         return i2c->msg_idx >= (i2c->msg_num - 1);
 368 }
 369
 370 /* is_msglast
 371  *
 372  * returns TRUE if we this is the last byte in the current message
 373 */
 374
 375 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 376 {
 377         /* msg->len is always 1 for the first byte of smbus block read.
 378          * Actual length will be read from slave. More bytes will be
 379          * read according to the length then. */
 380         if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 381                 return 0;
 382
 383         return i2c->msg_ptr == i2c->msg->len-1;
 384 }
 385
 386 /* is_msgend
 387  *
 388  * returns TRUE if we reached the end of the current message
 389 */
 390
 391 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 392 {
 393         return i2c->msg_ptr >= i2c->msg->len;
 394 }
 395
 396 /* i2c_s3c_irq_nextbyte
 397  *
 398  * process an interrupt and work out what to do
 399  */
 400
 401 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 402 {
 403         unsigned long tmp;
 404         unsigned char byte;
 405         int ret = 0;
 406
 407         switch (i2c->state) {
 408
 409         case STATE_IDLE:
 410                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 411                 goto out;
 412
 413         case STATE_STOP:
 414                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 415                 s3c24xx_i2c_disable_irq(i2c);
 416                 goto out_ack;
 417
 418         case STATE_START:
 419                 /* last thing we did was send a start condition on the
 420                  * bus, or started a new i2c message
 421                  */
 422
 423                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 424                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 425                         /* ack was not received... */
 426
 427                         dev_dbg(i2c->dev, "ack was not received\n");
 428                         s3c24xx_i2c_stop(i2c, -ENXIO);
 429                         goto out_ack;
 430                 }
 431
 432                 if (i2c->msg->flags & I2C_M_RD)
 433                         i2c->state = STATE_READ;
 434                 else
 435                         i2c->state = STATE_WRITE;
 436
 437                 /* terminate the transfer if there is nothing to do
 438                  * as this is used by the i2c probe to find devices. */
 439
 440                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 441                         s3c24xx_i2c_stop(i2c, 0);
 442                         goto out_ack;
 443                 }
 444
 445                 if (i2c->state == STATE_READ)
 446                         goto prepare_read;
 447
 448                 /* fall through to the write state, as we will need to
 449                  * send a byte as well */
 450
 451         case STATE_WRITE:
 452                 /* we are writing data to the device... check for the
 453                  * end of the message, and if so, work out what to do
 454                  */
 455
 456                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 457                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 458                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 459
 460                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 461                                 goto out_ack;
 462                         }
 463                 }
 464
 465  retry_write:
 466
 467                 if (!is_msgend(i2c)) {
 468                         byte = i2c->msg->buf[i2c->msg_ptr++];
 469                         writeb(byte, i2c->regs + S3C2410_IICDS);
 470
 471                         /* delay after writing the byte to allow the
 472                          * data setup time on the bus, as writing the
 473                          * data to the register causes the first bit
 474                          * to appear on SDA, and SCL will change as
 475                          * soon as the interrupt is acknowledged */
 476
 477                         ndelay(i2c->tx_setup);
 478
 479                 } else if (!is_lastmsg(i2c)) {
 480                         /* we need to go to the next i2c message */
 481
 482                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 483
 484                         i2c->msg_ptr = 0;
 485                         i2c->msg_idx++;
 486                         i2c->msg++;
 487
 488                         /* check to see if we need to do another message */
 489                         if (i2c->msg->flags & I2C_M_NOSTART) {
 490
 491                                 if (i2c->msg->flags & I2C_M_RD) {
 492                                         /* cannot do this, the controller
 493                                          * forces us to send a new START
 494                                          * when we change direction */
 495
 496                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 497                                 }
 498
 499                                 goto retry_write;
 500                         } else {
 501                                 /* send the new start */
 502                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 503                                 i2c->state = STATE_START;
 504                         }
 505
 506                 } else {
 507                         /* send stop */
 508
 509                         s3c24xx_i2c_stop(i2c, 0);
 510                 }
 511                 break;
 512
 513         case STATE_READ:
 514                 /* we have a byte of data in the data register, do
 515                  * something with it, and then work out whether we are
 516                  * going to do any more read/write
 517                  */
 518
 519                 byte = readb(i2c->regs + S3C2410_IICDS);
 520                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 521
 522                 /* Add actual length to read for smbus block read */
 523                 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 524                         i2c->msg->len += byte;
 525  prepare_read:
 526                 if (is_msglast(i2c)) {
 527                         /* last byte of buffer */
 528
 529                         if (is_lastmsg(i2c))
 530                                 s3c24xx_i2c_disable_ack(i2c);
 531
 532                 } else if (is_msgend(i2c)) {
 533                         /* ok, we've read the entire buffer, see if there
 534                          * is anything else we need to do */
 535
 536                         if (is_lastmsg(i2c)) {
 537                                 /* last message, send stop and complete */
 538                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 539
 540                                 s3c24xx_i2c_stop(i2c, 0);
 541                         } else {
 542                                 /* go to the next transfer */
 543                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 544
 545                                 i2c->msg_ptr = 0;
 546                                 i2c->msg_idx++;
 547                                 i2c->msg++;
 548                         }
 549                 }
 550
 551                 break;
 552         }
 553
 554         /* acknowlegde the IRQ and get back on with the work */
 555
 556  out_ack:
 557         tmp = readl(i2c->regs + S3C2410_IICCON);
 558         tmp &= ~S3C2410_IICCON_IRQPEND;
 559         writel(tmp, i2c->regs + S3C2410_IICCON);
 560  out:
 561         return ret;
 562 }
 563
 564 /* s3c24xx_i2c_irq
 565  *
 566  * top level IRQ servicing routine
 567 */
 568
 569 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 570 {
 571         struct s3c24xx_i2c *i2c = dev_id;
 572         unsigned long status;
 573         unsigned long tmp;
 574
 575         status = readl(i2c->regs + S3C2410_IICSTAT);
 576
 577         if (status & S3C2410_IICSTAT_ARBITR) {
 578                 /* deal with arbitration loss */
 579                 dev_err(i2c->dev, "deal with arbitration loss\n");
 580         }
 581
 582         if (i2c->state == STATE_IDLE) {
 583                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 584
 585                 tmp = readl(i2c->regs + S3C2410_IICCON);
 586                 tmp &= ~S3C2410_IICCON_IRQPEND;
 587                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 588                 goto out;
 589         }
 590
 591         /* pretty much this leaves us with the fact that we've
 592          * transmitted or received whatever byte we last sent */
 593
 594         i2c_s3c_irq_nextbyte(i2c, status);
 595
 596  out:
 597         return IRQ_HANDLED;
 598 }
 599
 600
 601 /* s3c24xx_i2c_set_master
 602  *
 603  * get the i2c bus for a master transaction
 604 */
 605
 606 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 607 {
 608         unsigned long iicstat;
 609         int timeout = 400;
 610
 611         while (timeout-- > 0) {
 612                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 613
 614                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 615                         return 0;
 616
 617                 msleep(1);
 618         }
 619
 620         return -ETIMEDOUT;
 621 }
 622
 623 /* s3c24xx_i2c_wait_idle
 624  *
 625  * wait for the i2c bus to become idle.
 626 */
 627
 628 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
 629 {
 630         unsigned long iicstat;
 631         ktime_t start, now;
 632         unsigned long delay;
 633         int spins;
 634
 635         /* ensure the stop has been through the bus */
 636
 637         dev_dbg(i2c->dev, "waiting for bus idle\n");
 638
 639         start = now = ktime_get();
 640
 641         /*
 642          * Most of the time, the bus is already idle within a few usec of the
 643          * end of a transaction.  However, really slow i2c devices can stretch
 644          * the clock, delaying STOP generation.
 645          *
 646          * On slower SoCs this typically happens within a very small number of
 647          * instructions so busy wait briefly to avoid scheduling overhead.
 648          */
 649         spins = 3;
 650         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 651         while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
 652                 cpu_relax();
 653                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 654         }
 655
 656         /*
 657          * If we do get an appreciable delay as a compromise between idle
 658          * detection latency for the normal, fast case, and system load in the
 659          * slow device case, use an exponential back off in the polling loop,
 660          * up to 1/10th of the total timeout, then continue to poll at a
 661          * constant rate up to the timeout.
 662          */
 663         delay = 1;
 664         while ((iicstat & S3C2410_IICSTAT_START) &&
 665                ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
 666                 usleep_range(delay, 2 * delay);
 667                 if (delay < S3C2410_IDLE_TIMEOUT / 10)
 668                         delay <<= 1;
 669                 now = ktime_get();
 670                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 671         }
 672
 673         if (iicstat & S3C2410_IICSTAT_START)
 674                 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
 675 }
 676
 677 /* s3c24xx_i2c_doxfer
 678  *
 679  * this starts an i2c transfer
 680 */
 681
 682 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 683                               struct i2c_msg *msgs, int num)
 684 {
 685         unsigned long timeout;
 686         int ret;
 687
 688         if (i2c->suspended)
 689                 return -EIO;
 690
 691         ret = s3c24xx_i2c_set_master(i2c);
 692         if (ret != 0) {
 693                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 694                 ret = -EAGAIN;
 695                 goto out;
 696         }
 697
 698         i2c->msg     = msgs;
 699         i2c->msg_num = num;
 700         i2c->msg_ptr = 0;
 701         i2c->msg_idx = 0;
 702         i2c->state   = STATE_START;
 703
 704         s3c24xx_i2c_enable_irq(i2c);
 705         s3c24xx_i2c_message_start(i2c, msgs);
 706
 707         if (i2c->quirks & QUIRK_POLL) {
 708                 ret = i2c->msg_idx;
 709
 710                 if (ret != num)
 711                         dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 712
 713                 goto out;
 714         }
 715
 716         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 717
 718         ret = i2c->msg_idx;
 719
 720         /* having these next two as dev_err() makes life very
 721          * noisy when doing an i2cdetect */
 722
 723         if (timeout == 0)
 724                 dev_dbg(i2c->dev, "timeout\n");
 725         else if (ret != num)
 726                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 727
 728         /* For QUIRK_HDMIPHY, bus is already disabled */
 729         if (i2c->quirks & QUIRK_HDMIPHY)
 730                 goto out;
 731
 732         s3c24xx_i2c_wait_idle(i2c);
 733
 734  out:
 735         return ret;
 736 }
 737
 738 /* s3c24xx_i2c_xfer
 739  *
 740  * first port of call from the i2c bus code when an message needs
 741  * transferring across the i2c bus.
 742 */
 743
 744 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 745                         struct i2c_msg *msgs, int num)
 746 {
 747         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 748         int retry;
 749         int ret;
 750
 751         pm_runtime_get_sync(&adap->dev);
 752         clk_prepare_enable(i2c->clk);
 753
 754         for (retry = 0; retry < adap->retries; retry++) {
 755
 756                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 757
 758                 if (ret != -EAGAIN) {
 759                         clk_disable_unprepare(i2c->clk);
 760                         pm_runtime_put(&adap->dev);
 761                         return ret;
 762                 }
 763
 764                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 765
 766                 udelay(100);
 767         }
 768
 769         clk_disable_unprepare(i2c->clk);
 770         pm_runtime_put(&adap->dev);
 771         return -EREMOTEIO;
 772 }
 773
 774 /* declare our i2c functionality */
 775 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 776 {
 777         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
 778                 I2C_FUNC_PROTOCOL_MANGLING;
 779 }
 780
 781 /* i2c bus registration info */
 782
 783 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 784         .master_xfer            = s3c24xx_i2c_xfer,
 785         .functionality          = s3c24xx_i2c_func,
 786 };
 787
 788 /* s3c24xx_i2c_calcdivisor
 789  *
 790  * return the divisor settings for a given frequency
 791 */
 792
 793 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 794                                    unsigned int *div1, unsigned int *divs)
 795 {
 796         unsigned int calc_divs = clkin / wanted;
 797         unsigned int calc_div1;
 798
 799         if (calc_divs > (16*16))
 800                 calc_div1 = 512;
 801         else
 802                 calc_div1 = 16;
 803
 804         calc_divs += calc_div1-1;
 805         calc_divs /= calc_div1;
 806
 807         if (calc_divs == 0)
 808                 calc_divs = 1;
 809         if (calc_divs > 17)
 810                 calc_divs = 17;
 811
 812         *divs = calc_divs;
 813         *div1 = calc_div1;
 814
 815         return clkin / (calc_divs * calc_div1);
 816 }
 817
 818 /* s3c24xx_i2c_clockrate
 819  *
 820  * work out a divisor for the user requested frequency setting,
 821  * either by the requested frequency, or scanning the acceptable
 822  * range of frequencies until something is found
 823 */
 824
 825 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 826 {
 827         struct s3c2410_platform_i2c *pdata = i2c->pdata;
 828         unsigned long clkin = clk_get_rate(i2c->clk);
 829         unsigned int divs, div1;
 830         unsigned long target_frequency;
 831         u32 iiccon;
 832         int freq;
 833
 834         i2c->clkrate = clkin;
 835         clkin /= 1000;          /* clkin now in KHz */
 836
 837         dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
 838
 839         target_frequency = pdata->frequency ? pdata->frequency : 100000;
 840
 841         target_frequency /= 1000; /* Target frequency now in KHz */
 842
 843         freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
 844
 845         if (freq > target_frequency) {
 846                 dev_err(i2c->dev,
 847                         "Unable to achieve desired frequency %luKHz."   \
 848                         " Lowest achievable %dKHz\n", target_frequency, freq);
 849                 return -EINVAL;
 850         }
 851
 852         *got = freq;
 853
 854         iiccon = readl(i2c->regs + S3C2410_IICCON);
 855         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 856         iiccon |= (divs-1);
 857
 858         if (div1 == 512)
 859                 iiccon |= S3C2410_IICCON_TXDIV_512;
 860
 861         if (i2c->quirks & QUIRK_POLL)
 862                 iiccon |= S3C2410_IICCON_SCALE(2);
 863
 864         writel(iiccon, i2c->regs + S3C2410_IICCON);
 865
 866         if (i2c->quirks & QUIRK_S3C2440) {
 867                 unsigned long sda_delay;
 868
 869                 if (pdata->sda_delay) {
 870                         sda_delay = clkin * pdata->sda_delay;
 871                         sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
 872                         sda_delay = DIV_ROUND_UP(sda_delay, 5);
 873                         if (sda_delay > 3)
 874                                 sda_delay = 3;
 875                         sda_delay |= S3C2410_IICLC_FILTER_ON;
 876                 } else
 877                         sda_delay = 0;
 878
 879                 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
 880                 writel(sda_delay, i2c->regs + S3C2440_IICLC);
 881         }
 882
 883         return 0;
 884 }
 885
 886 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 887
 888 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 889
 890 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 891                                           unsigned long val, void *data)
 892 {
 893         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 894         unsigned int got;
 895         int delta_f;
 896         int ret;
 897
 898         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 899
 900         /* if we're post-change and the input clock has slowed down
 901          * or at pre-change and the clock is about to speed up, then
 902          * adjust our clock rate. <0 is slow, >0 speedup.
 903          */
 904
 905         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 906             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 907                 i2c_lock_adapter(&i2c->adap);
 908                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 909                 i2c_unlock_adapter(&i2c->adap);
 910
 911                 if (ret < 0)
 912                         dev_err(i2c->dev, "cannot find frequency\n");
 913                 else
 914                         dev_info(i2c->dev, "setting freq %d\n", got);
 915         }
 916
 917         return 0;
 918 }
 919
 920 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 921 {
 922         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 923
 924         return cpufreq_register_notifier(&i2c->freq_transition,
 925                                          CPUFREQ_TRANSITION_NOTIFIER);
 926 }
 927
 928 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 929 {
 930         cpufreq_unregister_notifier(&i2c->freq_transition,
 931                                     CPUFREQ_TRANSITION_NOTIFIER);
 932 }
 933
 934 #else
 935 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 936 {
 937         return 0;
 938 }
 939
 940 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 941 {
 942 }
 943 #endif
 944
 945 #ifdef CONFIG_OF
 946 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 947 {
 948         int idx, gpio, ret;
 949
 950         if (i2c->quirks & QUIRK_NO_GPIO)
 951                 return 0;
 952
 953         for (idx = 0; idx < 2; idx++) {
 954                 gpio = of_get_gpio(i2c->dev->of_node, idx);
 955                 if (!gpio_is_valid(gpio)) {
 956                         dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
 957                         goto free_gpio;
 958                 }
 959                 i2c->gpios[idx] = gpio;
 960
 961                 ret = gpio_request(gpio, "i2c-bus");
 962                 if (ret) {
 963                         dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);
 964                         goto free_gpio;
 965                 }
 966         }
 967         return 0;
 968
 969 free_gpio:
 970         while (--idx >= 0)
 971                 gpio_free(i2c->gpios[idx]);
 972         return -EINVAL;
 973 }
 974
 975 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
 976 {
 977         unsigned int idx;
 978
 979         if (i2c->quirks & QUIRK_NO_GPIO)
 980                 return;
 981
 982         for (idx = 0; idx < 2; idx++)
 983                 gpio_free(i2c->gpios[idx]);
 984 }
 985 #else
 986 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 987 {
 988         return 0;
 989 }
 990
 991 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
 992 {
 993 }
 994 #endif
 995
 996 /* s3c24xx_i2c_init
 997  *
 998  * initialise the controller, set the IO lines and frequency
 999 */
1000
1001 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
1002 {
1003         unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
1004         struct s3c2410_platform_i2c *pdata;
1005         unsigned int freq;
1006
1007         /* get the plafrom data */
1008
1009         pdata = i2c->pdata;
1010
1011         /* write slave address */
1012
1013         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
1014
1015         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
1016
1017         writel(iicon, i2c->regs + S3C2410_IICCON);
1018
1019         /* we need to work out the divisors for the clock... */
1020
1021         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
1022                 writel(0, i2c->regs + S3C2410_IICCON);
1023                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
1024                 return -EINVAL;
1025         }
1026
1027         /* todo - check that the i2c lines aren't being dragged anywhere */
1028
1029         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1030         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
1031
1032         return 0;
1033 }
1034
1035 #ifdef CONFIG_OF
1036 /* s3c24xx_i2c_parse_dt
1037  *
1038  * Parse the device tree node and retreive the platform data.
1039 */
1040
1041 static void
1042 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1043 {
1044         struct s3c2410_platform_i2c *pdata = i2c->pdata;
1045
1046         if (!np)
1047                 return;
1048
1049         pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1050         of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1051         of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1052         of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1053                                 (u32 *)&pdata->frequency);
1054 }
1055 #else
1056 static void
1057 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1058 {
1059         return;
1060 }
1061 #endif
1062
1063 /* s3c24xx_i2c_probe
1064  *
1065  * called by the bus driver when a suitable device is found
1066 */
1067
1068 static int s3c24xx_i2c_probe(struct platform_device *pdev)
1069 {
1070         struct s3c24xx_i2c *i2c;
1071         struct s3c2410_platform_i2c *pdata = NULL;
1072         struct resource *res;
1073         int ret;
1074
1075         if (!pdev->dev.of_node) {
1076                 pdata = dev_get_platdata(&pdev->dev);
1077                 if (!pdata) {
1078                         dev_err(&pdev->dev, "no platform data\n");
1079                         return -EINVAL;
1080                 }
1081         }
1082
1083         i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1084         if (!i2c)
1085                 return -ENOMEM;
1086
1087         i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1088         if (!i2c->pdata)
1089                 return -ENOMEM;
1090
1091         i2c->quirks = s3c24xx_get_device_quirks(pdev);
1092         if (pdata)
1093                 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1094         else
1095                 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1096
1097         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1098         i2c->adap.owner   = THIS_MODULE;
1099         i2c->adap.algo    = &s3c24xx_i2c_algorithm;
1100         i2c->adap.retries = 2;
1101         i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1102         i2c->tx_setup     = 50;
1103
1104         init_waitqueue_head(&i2c->wait);
1105
1106         /* find the clock and enable it */
1107
1108         i2c->dev = &pdev->dev;
1109         i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1110         if (IS_ERR(i2c->clk)) {
1111                 dev_err(&pdev->dev, "cannot get clock\n");
1112                 return -ENOENT;
1113         }
1114
1115         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1116
1117
1118         /* map the registers */
1119
1120         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1121         i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1122
1123         if (IS_ERR(i2c->regs))
1124                 return PTR_ERR(i2c->regs);
1125
1126         dev_dbg(&pdev->dev, "registers %p (%p)\n",
1127                 i2c->regs, res);
1128
1129         /* setup info block for the i2c core */
1130
1131         i2c->adap.algo_data = i2c;
1132         i2c->adap.dev.parent = &pdev->dev;
1133
1134         i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1135
1136         /* inititalise the i2c gpio lines */
1137
1138         if (i2c->pdata->cfg_gpio) {
1139                 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1140         } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) {
1141                 return -EINVAL;
1142         }
1143
1144         /* initialise the i2c controller */
1145
1146         clk_prepare_enable(i2c->clk);
1147         ret = s3c24xx_i2c_init(i2c);
1148         clk_disable_unprepare(i2c->clk);
1149         if (ret != 0) {
1150                 dev_err(&pdev->dev, "I2C controller init failed\n");
1151                 return ret;
1152         }
1153         /* find the IRQ for this unit (note, this relies on the init call to
1154          * ensure no current IRQs pending
1155          */
1156
1157         if (!(i2c->quirks & QUIRK_POLL)) {
1158                 i2c->irq = ret = platform_get_irq(pdev, 0);
1159                 if (ret <= 0) {
1160                         dev_err(&pdev->dev, "cannot find IRQ\n");
1161                         return ret;
1162                 }
1163
1164         ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0,
1165                                 dev_name(&pdev->dev), i2c);
1166
1167                 if (ret != 0) {
1168                         dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1169                         return ret;
1170                 }
1171         }
1172
1173         ret = s3c24xx_i2c_register_cpufreq(i2c);
1174         if (ret < 0) {
1175                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1176                 return ret;
1177         }
1178
1179         /* Note, previous versions of the driver used i2c_add_adapter()
1180          * to add the bus at any number. We now pass the bus number via
1181          * the platform data, so if unset it will now default to always
1182          * being bus 0.
1183          */
1184
1185         i2c->adap.nr = i2c->pdata->bus_num;
1186         i2c->adap.dev.of_node = pdev->dev.of_node;
1187
1188         ret = i2c_add_numbered_adapter(&i2c->adap);
1189         if (ret < 0) {
1190                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
1191                 s3c24xx_i2c_deregister_cpufreq(i2c);
1192                 return ret;
1193         }
1194
1195         platform_set_drvdata(pdev, i2c);
1196
1197         pm_runtime_enable(&pdev->dev);
1198         pm_runtime_enable(&i2c->adap.dev);
1199
1200         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1201         return 0;
1202 }
1203
1204 /* s3c24xx_i2c_remove
1205  *
1206  * called when device is removed from the bus
1207 */
1208
1209 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1210 {
1211         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1212
1213         pm_runtime_disable(&i2c->adap.dev);
1214         pm_runtime_disable(&pdev->dev);
1215
1216         s3c24xx_i2c_deregister_cpufreq(i2c);
1217
1218         i2c_del_adapter(&i2c->adap);
1219
1220         if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1221                 s3c24xx_i2c_dt_gpio_free(i2c);
1222
1223         return 0;
1224 }
1225
1226 #ifdef CONFIG_PM_SLEEP
1227 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1228 {
1229         struct platform_device *pdev = to_platform_device(dev);
1230         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1231
1232         i2c->suspended = 1;
1233
1234         return 0;
1235 }
1236
1237 static int s3c24xx_i2c_resume(struct device *dev)
1238 {
1239         struct platform_device *pdev = to_platform_device(dev);
1240         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1241
1242         clk_prepare_enable(i2c->clk);
1243         s3c24xx_i2c_init(i2c);
1244         clk_disable_unprepare(i2c->clk);
1245         i2c->suspended = 0;
1246
1247         return 0;
1248 }
1249 #endif
1250
1251 #ifdef CONFIG_PM
1252 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1253 #ifdef CONFIG_PM_SLEEP
1254         .suspend_noirq = s3c24xx_i2c_suspend_noirq,
1255         .resume = s3c24xx_i2c_resume,
1256 #endif
1257 };
1258
1259 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1260 #else
1261 #define S3C24XX_DEV_PM_OPS NULL
1262 #endif
1263
1264 /* device driver for platform bus bits */
1265
1266 static struct platform_driver s3c24xx_i2c_driver = {
1267         .probe          = s3c24xx_i2c_probe,
1268         .remove         = s3c24xx_i2c_remove,
1269         .id_table       = s3c24xx_driver_ids,
1270         .driver         = {
1271                 .owner  = THIS_MODULE,
1272                 .name   = "s3c-i2c",
1273                 .pm     = S3C24XX_DEV_PM_OPS,
1274                 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1275         },
1276 };
1277
1278 static int __init i2c_adap_s3c_init(void)
1279 {
1280         return platform_driver_register(&s3c24xx_i2c_driver);
1281 }
1282 subsys_initcall(i2c_adap_s3c_init);
1283
1284 static void __exit i2c_adap_s3c_exit(void)
1285 {
1286         platform_driver_unregister(&s3c24xx_i2c_driver);
1287 }
1288 module_exit(i2c_adap_s3c_exit);
1289
1290 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1291 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1292 MODULE_LICENSE("GPL");