2 * drivers/i2c/busses/i2c-rcar.c
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
8 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
10 * This file used out-of-tree driver i2c-rcar.c
11 * Copyright (C) 2011-2012 Renesas Electronics Corporation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 #include <linux/interrupt.h>
31 #include <linux/i2c.h>
32 #include <linux/i2c/i2c-rcar.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/slab.h>
39 #include <linux/spinlock.h>
41 /* register offsets */
42 #define ICSCR 0x00 /* slave ctrl */
43 #define ICMCR 0x04 /* master ctrl */
44 #define ICSSR 0x08 /* slave status */
45 #define ICMSR 0x0C /* master status */
46 #define ICSIER 0x10 /* slave irq enable */
47 #define ICMIER 0x14 /* master irq enable */
48 #define ICCCR 0x18 /* clock dividers */
49 #define ICSAR 0x1C /* slave address */
50 #define ICMAR 0x20 /* master address */
51 #define ICRXTX 0x24 /* data port */
54 #define MDBS (1 << 7) /* non-fifo mode switch */
55 #define FSCL (1 << 6) /* override SCL pin */
56 #define FSDA (1 << 5) /* override SDA pin */
57 #define OBPC (1 << 4) /* override pins */
58 #define MIE (1 << 3) /* master if enable */
60 #define FSB (1 << 1) /* force stop bit */
61 #define ESG (1 << 0) /* en startbit gen */
64 #define MNR (1 << 6) /* nack received */
65 #define MAL (1 << 5) /* arbitration lost */
66 #define MST (1 << 4) /* sent a stop */
70 #define MAT (1 << 0) /* slave addr xfer done */
73 #define MNRE (1 << 6) /* nack irq en */
74 #define MALE (1 << 5) /* arblos irq en */
75 #define MSTE (1 << 4) /* stop irq en */
79 #define MATE (1 << 0) /* address sent irq en */
90 RCAR_IRQ_OPEN_FOR_SEND,
91 RCAR_IRQ_OPEN_FOR_RECV,
92 RCAR_IRQ_OPEN_FOR_STOP,
98 #define ID_LAST_MSG (1 << 0)
99 #define ID_IOERROR (1 << 1)
100 #define ID_DONE (1 << 2)
101 #define ID_ARBLOST (1 << 3)
102 #define ID_NACK (1 << 4)
109 struct rcar_i2c_priv {
111 struct i2c_adapter adap;
115 wait_queue_head_t wait;
121 enum rcar_i2c_type devtype;
124 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
125 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
127 #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f))
128 #define rcar_i2c_flags_has(p, f) ((p)->flags & (f))
130 #define LOOP_TIMEOUT 1024
135 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
137 writel(val, priv->io + reg);
140 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
142 return readl(priv->io + reg);
145 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
149 * slave mode is not used on this driver
151 rcar_i2c_write(priv, ICSIER, 0);
152 rcar_i2c_write(priv, ICSAR, 0);
153 rcar_i2c_write(priv, ICSCR, 0);
154 rcar_i2c_write(priv, ICSSR, 0);
156 /* reset master mode */
157 rcar_i2c_write(priv, ICMIER, 0);
158 rcar_i2c_write(priv, ICMCR, 0);
159 rcar_i2c_write(priv, ICMSR, 0);
160 rcar_i2c_write(priv, ICMAR, 0);
163 static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open)
165 u32 val = MNRE | MALE | MSTE | MATE; /* default */
168 case RCAR_IRQ_OPEN_FOR_SEND:
169 val |= MDEE; /* default + send */
171 case RCAR_IRQ_OPEN_FOR_RECV:
172 val |= MDRE; /* default + read */
174 case RCAR_IRQ_OPEN_FOR_STOP:
175 val = MSTE; /* stop irq only */
179 val = 0; /* all close */
182 rcar_i2c_write(priv, ICMIER, val);
185 static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv)
187 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv);
191 * bus control functions
193 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
197 for (i = 0; i < LOOP_TIMEOUT; i++) {
198 /* make sure that bus is not busy */
199 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
207 static void rcar_i2c_bus_phase(struct rcar_i2c_priv *priv, int phase)
210 case RCAR_BUS_PHASE_ADDR:
211 rcar_i2c_write(priv, ICMCR, MDBS | MIE | ESG);
213 case RCAR_BUS_PHASE_DATA:
214 rcar_i2c_write(priv, ICMCR, MDBS | MIE);
216 case RCAR_BUS_PHASE_STOP:
217 rcar_i2c_write(priv, ICMCR, MDBS | MIE | FSB);
225 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
229 struct clk *clkp = clk_get(dev, NULL);
237 dev_err(dev, "couldn't get clock\n");
238 return PTR_ERR(clkp);
241 switch (priv->devtype) {
249 dev_err(dev, "device type error\n");
254 * calculate SCL clock
258 * ick = clkp / (1 + CDF)
259 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
261 * ick : I2C internal clock < 20 MHz
262 * ticf : I2C SCL falling time = 35 ns here
263 * tr : I2C SCL rising time = 200 ns here
264 * intd : LSI internal delay = 50 ns here
265 * clkp : peripheral_clk
266 * F[] : integer up-valuation
268 rate = clk_get_rate(clkp);
269 cdf = rate / 20000000;
270 if (cdf >= 1 << cdf_width) {
271 dev_err(dev, "Input clock %lu too high\n", rate);
274 ick = rate / (cdf + 1);
277 * it is impossible to calculate large scale
278 * number on u32. separate it
280 * F[(ticf + tr + intd) * ick]
281 * = F[(35 + 200 + 50)ns * ick]
282 * = F[285 * ick / 1000000000]
283 * = F[(ick / 1000000) * 285 / 1000]
285 round = (ick + 500000) / 1000000 * 285;
286 round = (round + 500) / 1000;
289 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
291 * Calculation result (= SCL) should be less than
292 * bus_speed for hardware safety
294 * We could use something along the lines of
295 * div = ick / (bus_speed + 1) + 1;
296 * scgd = (div - 20 - round + 7) / 8;
297 * scl = ick / (20 + (scgd * 8) + round);
298 * (not fully verified) but that would get pretty involved
300 for (scgd = 0; scgd < 0x40; scgd++) {
301 scl = ick / (20 + (scgd * 8) + round);
302 if (scl <= bus_speed)
305 dev_err(dev, "it is impossible to calculate best SCL\n");
309 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
310 scl, bus_speed, clk_get_rate(clkp), round, cdf, scgd);
315 priv->icccr = scgd << cdf_width | cdf;
320 static void rcar_i2c_clock_start(struct rcar_i2c_priv *priv)
322 rcar_i2c_write(priv, ICCCR, priv->icccr);
328 static u32 rcar_i2c_status_get(struct rcar_i2c_priv *priv)
330 return rcar_i2c_read(priv, ICMSR);
333 #define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff)
334 static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit)
336 rcar_i2c_write(priv, ICMSR, ~bit);
340 * recv/send functions
342 static int rcar_i2c_recv(struct rcar_i2c_priv *priv)
344 rcar_i2c_set_addr(priv, 1);
345 rcar_i2c_status_clear(priv);
346 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR);
347 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV);
352 static int rcar_i2c_send(struct rcar_i2c_priv *priv)
357 * It should check bus status when send case
359 ret = rcar_i2c_bus_barrier(priv);
363 rcar_i2c_set_addr(priv, 0);
364 rcar_i2c_status_clear(priv);
365 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR);
366 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND);
371 #define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE))
372 #define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR))
375 * interrupt functions
377 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
379 struct i2c_msg *msg = priv->msg;
383 * sometimes, unknown interrupt happened.
390 * If address transfer phase finished,
394 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA);
396 if (priv->pos < msg->len) {
398 * Prepare next data to ICRXTX register.
399 * This data will go to _SHIFT_ register.
402 * [ICRXTX] -> [SHIFT] -> [I2C bus]
404 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
409 * The last data was pushed to ICRXTX on _PREV_ empty irq.
410 * It is on _SHIFT_ register, and will sent to I2C bus.
413 * [ICRXTX] -> [SHIFT] -> [I2C bus]
416 if (priv->flags & ID_LAST_MSG)
418 * If current msg is the _LAST_ msg,
419 * prepare stop condition here.
420 * ID_DONE will be set on STOP irq.
422 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
425 * If current msg is _NOT_ last msg,
426 * it doesn't call stop phase.
427 * thus, there is no STOP irq.
428 * return ID_DONE here.
433 rcar_i2c_send_restart(priv);
438 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
440 struct i2c_msg *msg = priv->msg;
444 * sometimes, unknown interrupt happened.
452 * Address transfer phase finished,
453 * but, there is no data at this point.
456 } else if (priv->pos < msg->len) {
460 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
465 * If next received data is the _LAST_,
467 * otherwise, go to DATA phase.
469 if (priv->pos + 1 >= msg->len)
470 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
472 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA);
474 rcar_i2c_recv_restart(priv);
479 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
481 struct rcar_i2c_priv *priv = ptr;
482 struct device *dev = rcar_i2c_priv_to_dev(priv);
485 /*-------------- spin lock -----------------*/
486 spin_lock(&priv->lock);
488 msr = rcar_i2c_status_get(priv);
497 * When arbitration lost, device become _slave_ mode.
499 dev_dbg(dev, "Arbitration Lost\n");
500 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
508 dev_dbg(dev, "Stop\n");
509 rcar_i2c_flags_set(priv, ID_DONE);
517 dev_dbg(dev, "Nack\n");
519 /* go to stop phase */
520 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
521 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP);
522 rcar_i2c_flags_set(priv, ID_NACK);
529 if (rcar_i2c_is_recv(priv))
530 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
532 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
535 if (rcar_i2c_flags_has(priv, ID_DONE)) {
536 rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE);
537 rcar_i2c_status_clear(priv);
538 wake_up(&priv->wait);
541 spin_unlock(&priv->lock);
542 /*-------------- spin unlock -----------------*/
547 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
548 struct i2c_msg *msgs,
551 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
552 struct device *dev = rcar_i2c_priv_to_dev(priv);
556 pm_runtime_get_sync(dev);
558 /*-------------- spin lock -----------------*/
559 spin_lock_irqsave(&priv->lock, flags);
562 rcar_i2c_clock_start(priv);
564 spin_unlock_irqrestore(&priv->lock, flags);
565 /*-------------- spin unlock -----------------*/
568 for (i = 0; i < num; i++) {
569 /*-------------- spin lock -----------------*/
570 spin_lock_irqsave(&priv->lock, flags);
573 priv->msg = &msgs[i];
576 if (priv->msg == &msgs[num - 1])
577 rcar_i2c_flags_set(priv, ID_LAST_MSG);
579 /* start send/recv */
580 if (rcar_i2c_is_recv(priv))
581 ret = rcar_i2c_recv(priv);
583 ret = rcar_i2c_send(priv);
585 spin_unlock_irqrestore(&priv->lock, flags);
586 /*-------------- spin unlock -----------------*/
594 timeout = wait_event_timeout(priv->wait,
595 rcar_i2c_flags_has(priv, ID_DONE),
605 if (rcar_i2c_flags_has(priv, ID_NACK)) {
610 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
615 if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
620 ret = i + 1; /* The number of transfer */
625 if (ret < 0 && ret != -EREMOTEIO)
626 dev_err(dev, "error %d : %x\n", ret, priv->flags);
631 static u32 rcar_i2c_func(struct i2c_adapter *adap)
633 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
636 static const struct i2c_algorithm rcar_i2c_algo = {
637 .master_xfer = rcar_i2c_master_xfer,
638 .functionality = rcar_i2c_func,
641 static const struct of_device_id rcar_i2c_dt_ids[] = {
642 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
643 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
644 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
645 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
648 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
650 static int rcar_i2c_probe(struct platform_device *pdev)
652 struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
653 struct rcar_i2c_priv *priv;
654 struct i2c_adapter *adap;
655 struct resource *res;
656 struct device *dev = &pdev->dev;
660 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
662 dev_err(dev, "no mem for private data\n");
666 bus_speed = 100000; /* default 100 kHz */
667 ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
668 if (ret < 0 && pdata && pdata->bus_speed)
669 bus_speed = pdata->bus_speed;
671 if (pdev->dev.of_node)
672 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
675 priv->devtype = platform_get_device_id(pdev)->driver_data;
677 ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
681 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
682 priv->io = devm_ioremap_resource(dev, res);
683 if (IS_ERR(priv->io))
684 return PTR_ERR(priv->io);
686 priv->irq = platform_get_irq(pdev, 0);
687 init_waitqueue_head(&priv->wait);
688 spin_lock_init(&priv->lock);
692 adap->algo = &rcar_i2c_algo;
693 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
695 adap->dev.parent = dev;
696 adap->dev.of_node = dev->of_node;
697 i2c_set_adapdata(adap, priv);
698 strlcpy(adap->name, pdev->name, sizeof(adap->name));
700 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0,
701 dev_name(dev), priv);
703 dev_err(dev, "cannot get irq %d\n", priv->irq);
707 ret = i2c_add_numbered_adapter(adap);
709 dev_err(dev, "reg adap failed: %d\n", ret);
713 pm_runtime_enable(dev);
714 platform_set_drvdata(pdev, priv);
716 dev_info(dev, "probed\n");
721 static int rcar_i2c_remove(struct platform_device *pdev)
723 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
724 struct device *dev = &pdev->dev;
726 i2c_del_adapter(&priv->adap);
727 pm_runtime_disable(dev);
732 static struct platform_device_id rcar_i2c_id_table[] = {
733 { "i2c-rcar", I2C_RCAR_GEN1 },
734 { "i2c-rcar_gen1", I2C_RCAR_GEN1 },
735 { "i2c-rcar_gen2", I2C_RCAR_GEN2 },
738 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
740 static struct platform_driver rcar_i2c_driver = {
743 .owner = THIS_MODULE,
744 .of_match_table = rcar_i2c_dt_ids,
746 .probe = rcar_i2c_probe,
747 .remove = rcar_i2c_remove,
748 .id_table = rcar_i2c_id_table,
751 module_platform_driver(rcar_i2c_driver);
753 MODULE_LICENSE("GPL");
754 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
755 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");