2 * drivers/i2c/busses/i2c-rcar.c
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
8 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
10 * This file used out-of-tree driver i2c-rcar.c
11 * Copyright (C) 2011-2012 Renesas Electronics Corporation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 #include <linux/interrupt.h>
31 #include <linux/i2c.h>
32 #include <linux/i2c/i2c-rcar.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/slab.h>
40 /* register offsets */
41 #define ICSCR 0x00 /* slave ctrl */
42 #define ICMCR 0x04 /* master ctrl */
43 #define ICSSR 0x08 /* slave status */
44 #define ICMSR 0x0C /* master status */
45 #define ICSIER 0x10 /* slave irq enable */
46 #define ICMIER 0x14 /* master irq enable */
47 #define ICCCR 0x18 /* clock dividers */
48 #define ICSAR 0x1C /* slave address */
49 #define ICMAR 0x20 /* master address */
50 #define ICRXTX 0x24 /* data port */
53 #define MDBS (1 << 7) /* non-fifo mode switch */
54 #define FSCL (1 << 6) /* override SCL pin */
55 #define FSDA (1 << 5) /* override SDA pin */
56 #define OBPC (1 << 4) /* override pins */
57 #define MIE (1 << 3) /* master if enable */
59 #define FSB (1 << 1) /* force stop bit */
60 #define ESG (1 << 0) /* en startbit gen */
63 #define MNR (1 << 6) /* nack received */
64 #define MAL (1 << 5) /* arbitration lost */
65 #define MST (1 << 4) /* sent a stop */
69 #define MAT (1 << 0) /* slave addr xfer done */
72 #define MNRE (1 << 6) /* nack irq en */
73 #define MALE (1 << 5) /* arblos irq en */
74 #define MSTE (1 << 4) /* stop irq en */
78 #define MATE (1 << 0) /* address sent irq en */
81 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
82 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
83 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
85 #define RCAR_IRQ_SEND (MNRE | MALE | MSTE | MATE | MDEE)
86 #define RCAR_IRQ_RECV (MNRE | MALE | MSTE | MATE | MDRE)
87 #define RCAR_IRQ_STOP (MSTE)
89 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE))
90 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR))
95 #define ID_LAST_MSG (1 << 0)
96 #define ID_IOERROR (1 << 1)
97 #define ID_DONE (1 << 2)
98 #define ID_ARBLOST (1 << 3)
99 #define ID_NACK (1 << 4)
106 struct rcar_i2c_priv {
108 struct i2c_adapter adap;
112 wait_queue_head_t wait;
117 enum rcar_i2c_type devtype;
120 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
121 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
123 #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f))
124 #define rcar_i2c_flags_has(p, f) ((p)->flags & (f))
126 #define LOOP_TIMEOUT 1024
131 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
133 writel(val, priv->io + reg);
136 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
138 return readl(priv->io + reg);
141 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
145 * slave mode is not used on this driver
147 rcar_i2c_write(priv, ICSIER, 0);
148 rcar_i2c_write(priv, ICSAR, 0);
149 rcar_i2c_write(priv, ICSCR, 0);
150 rcar_i2c_write(priv, ICSSR, 0);
152 /* reset master mode */
153 rcar_i2c_write(priv, ICMIER, 0);
154 rcar_i2c_write(priv, ICMCR, 0);
155 rcar_i2c_write(priv, ICMSR, 0);
156 rcar_i2c_write(priv, ICMAR, 0);
160 * bus control functions
162 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
166 for (i = 0; i < LOOP_TIMEOUT; i++) {
167 /* make sure that bus is not busy */
168 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
179 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
189 switch (priv->devtype) {
197 dev_err(dev, "device type error\n");
202 * calculate SCL clock
206 * ick = clkp / (1 + CDF)
207 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
209 * ick : I2C internal clock < 20 MHz
210 * ticf : I2C SCL falling time = 35 ns here
211 * tr : I2C SCL rising time = 200 ns here
212 * intd : LSI internal delay = 50 ns here
213 * clkp : peripheral_clk
214 * F[] : integer up-valuation
216 rate = clk_get_rate(priv->clk);
217 cdf = rate / 20000000;
218 if (cdf >= 1 << cdf_width) {
219 dev_err(dev, "Input clock %lu too high\n", rate);
222 ick = rate / (cdf + 1);
225 * it is impossible to calculate large scale
226 * number on u32. separate it
228 * F[(ticf + tr + intd) * ick]
229 * = F[(35 + 200 + 50)ns * ick]
230 * = F[285 * ick / 1000000000]
231 * = F[(ick / 1000000) * 285 / 1000]
233 round = (ick + 500000) / 1000000 * 285;
234 round = (round + 500) / 1000;
237 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
239 * Calculation result (= SCL) should be less than
240 * bus_speed for hardware safety
242 * We could use something along the lines of
243 * div = ick / (bus_speed + 1) + 1;
244 * scgd = (div - 20 - round + 7) / 8;
245 * scl = ick / (20 + (scgd * 8) + round);
246 * (not fully verified) but that would get pretty involved
248 for (scgd = 0; scgd < 0x40; scgd++) {
249 scl = ick / (20 + (scgd * 8) + round);
250 if (scl <= bus_speed)
253 dev_err(dev, "it is impossible to calculate best SCL\n");
257 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
258 scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
263 priv->icccr = scgd << cdf_width | cdf;
272 static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
274 int read = !!rcar_i2c_is_recv(priv);
276 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
277 rcar_i2c_write(priv, ICMSR, 0);
278 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
279 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
285 * interrupt functions
287 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
289 struct i2c_msg *msg = priv->msg;
293 * sometimes, unknown interrupt happened.
300 * If address transfer phase finished,
304 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
306 if (priv->pos < msg->len) {
308 * Prepare next data to ICRXTX register.
309 * This data will go to _SHIFT_ register.
312 * [ICRXTX] -> [SHIFT] -> [I2C bus]
314 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
319 * The last data was pushed to ICRXTX on _PREV_ empty irq.
320 * It is on _SHIFT_ register, and will sent to I2C bus.
323 * [ICRXTX] -> [SHIFT] -> [I2C bus]
326 if (priv->flags & ID_LAST_MSG)
328 * If current msg is the _LAST_ msg,
329 * prepare stop condition here.
330 * ID_DONE will be set on STOP irq.
332 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
335 * If current msg is _NOT_ last msg,
336 * it doesn't call stop phase.
337 * thus, there is no STOP irq.
338 * return ID_DONE here.
343 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
348 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
350 struct i2c_msg *msg = priv->msg;
354 * sometimes, unknown interrupt happened.
362 * Address transfer phase finished,
363 * but, there is no data at this point.
366 } else if (priv->pos < msg->len) {
370 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
375 * If next received data is the _LAST_,
377 * otherwise, go to DATA phase.
379 if (priv->pos + 1 >= msg->len)
380 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
382 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
384 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
389 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
391 struct rcar_i2c_priv *priv = ptr;
392 struct device *dev = rcar_i2c_priv_to_dev(priv);
395 msr = rcar_i2c_read(priv, ICMSR);
404 * When arbitration lost, device become _slave_ mode.
406 dev_dbg(dev, "Arbitration Lost\n");
407 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
415 dev_dbg(dev, "Stop\n");
416 rcar_i2c_flags_set(priv, ID_DONE);
424 dev_dbg(dev, "Nack\n");
426 /* go to stop phase */
427 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
428 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
429 rcar_i2c_flags_set(priv, ID_NACK);
436 if (rcar_i2c_is_recv(priv))
437 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
439 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
442 if (rcar_i2c_flags_has(priv, ID_DONE)) {
443 rcar_i2c_write(priv, ICMIER, 0);
444 rcar_i2c_write(priv, ICMSR, 0);
445 wake_up(&priv->wait);
451 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
452 struct i2c_msg *msgs,
455 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
456 struct device *dev = rcar_i2c_priv_to_dev(priv);
459 pm_runtime_get_sync(dev);
463 rcar_i2c_write(priv, ICCCR, priv->icccr);
465 ret = rcar_i2c_bus_barrier(priv);
469 for (i = 0; i < num; i++) {
470 /* This HW can't send STOP after address phase */
471 if (msgs[i].len == 0) {
477 priv->msg = &msgs[i];
480 if (priv->msg == &msgs[num - 1])
481 rcar_i2c_flags_set(priv, ID_LAST_MSG);
483 ret = rcar_i2c_prepare_msg(priv);
491 timeout = wait_event_timeout(priv->wait,
492 rcar_i2c_flags_has(priv, ID_DONE),
502 if (rcar_i2c_flags_has(priv, ID_NACK)) {
507 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
512 if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
517 ret = i + 1; /* The number of transfer */
522 if (ret < 0 && ret != -ENXIO)
523 dev_err(dev, "error %d : %x\n", ret, priv->flags);
528 static u32 rcar_i2c_func(struct i2c_adapter *adap)
530 /* This HW can't do SMBUS_QUICK and NOSTART */
531 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
534 static const struct i2c_algorithm rcar_i2c_algo = {
535 .master_xfer = rcar_i2c_master_xfer,
536 .functionality = rcar_i2c_func,
539 static const struct of_device_id rcar_i2c_dt_ids[] = {
540 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
541 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
542 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
543 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
544 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
545 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
546 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
547 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
550 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
552 static int rcar_i2c_probe(struct platform_device *pdev)
554 struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
555 struct rcar_i2c_priv *priv;
556 struct i2c_adapter *adap;
557 struct resource *res;
558 struct device *dev = &pdev->dev;
562 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
564 dev_err(dev, "no mem for private data\n");
568 priv->clk = devm_clk_get(dev, NULL);
569 if (IS_ERR(priv->clk)) {
570 dev_err(dev, "cannot get clock\n");
571 return PTR_ERR(priv->clk);
574 bus_speed = 100000; /* default 100 kHz */
575 ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
576 if (ret < 0 && pdata && pdata->bus_speed)
577 bus_speed = pdata->bus_speed;
579 if (pdev->dev.of_node)
580 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
583 priv->devtype = platform_get_device_id(pdev)->driver_data;
585 ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
589 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
590 priv->io = devm_ioremap_resource(dev, res);
591 if (IS_ERR(priv->io))
592 return PTR_ERR(priv->io);
594 irq = platform_get_irq(pdev, 0);
595 init_waitqueue_head(&priv->wait);
599 adap->algo = &rcar_i2c_algo;
600 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED;
602 adap->dev.parent = dev;
603 adap->dev.of_node = dev->of_node;
604 i2c_set_adapdata(adap, priv);
605 strlcpy(adap->name, pdev->name, sizeof(adap->name));
607 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
608 dev_name(dev), priv);
610 dev_err(dev, "cannot get irq %d\n", irq);
614 ret = i2c_add_numbered_adapter(adap);
616 dev_err(dev, "reg adap failed: %d\n", ret);
620 pm_runtime_enable(dev);
621 platform_set_drvdata(pdev, priv);
623 dev_info(dev, "probed\n");
628 static int rcar_i2c_remove(struct platform_device *pdev)
630 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
631 struct device *dev = &pdev->dev;
633 i2c_del_adapter(&priv->adap);
634 pm_runtime_disable(dev);
639 static struct platform_device_id rcar_i2c_id_table[] = {
640 { "i2c-rcar", I2C_RCAR_GEN1 },
641 { "i2c-rcar_gen1", I2C_RCAR_GEN1 },
642 { "i2c-rcar_gen2", I2C_RCAR_GEN2 },
645 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
647 static struct platform_driver rcar_i2c_driver = {
650 .owner = THIS_MODULE,
651 .of_match_table = rcar_i2c_dt_ids,
653 .probe = rcar_i2c_probe,
654 .remove = rcar_i2c_remove,
655 .id_table = rcar_i2c_id_table,
658 module_platform_driver(rcar_i2c_driver);
660 MODULE_LICENSE("GPL");
661 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
662 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");