2 * drivers/i2c/busses/i2c-rcar.c
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
8 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
10 * This file used out-of-tree driver i2c-rcar.c
11 * Copyright (C) 2011-2012 Renesas Electronics Corporation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 #include <linux/interrupt.h>
31 #include <linux/i2c.h>
32 #include <linux/i2c/i2c-rcar.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/slab.h>
39 #include <linux/spinlock.h>
41 /* register offsets */
42 #define ICSCR 0x00 /* slave ctrl */
43 #define ICMCR 0x04 /* master ctrl */
44 #define ICSSR 0x08 /* slave status */
45 #define ICMSR 0x0C /* master status */
46 #define ICSIER 0x10 /* slave irq enable */
47 #define ICMIER 0x14 /* master irq enable */
48 #define ICCCR 0x18 /* clock dividers */
49 #define ICSAR 0x1C /* slave address */
50 #define ICMAR 0x20 /* master address */
51 #define ICRXTX 0x24 /* data port */
54 #define MDBS (1 << 7) /* non-fifo mode switch */
55 #define FSCL (1 << 6) /* override SCL pin */
56 #define FSDA (1 << 5) /* override SDA pin */
57 #define OBPC (1 << 4) /* override pins */
58 #define MIE (1 << 3) /* master if enable */
60 #define FSB (1 << 1) /* force stop bit */
61 #define ESG (1 << 0) /* en startbit gen */
64 #define MNR (1 << 6) /* nack received */
65 #define MAL (1 << 5) /* arbitration lost */
66 #define MST (1 << 4) /* sent a stop */
70 #define MAT (1 << 0) /* slave addr xfer done */
73 #define MNRE (1 << 6) /* nack irq en */
74 #define MALE (1 << 5) /* arblos irq en */
75 #define MSTE (1 << 4) /* stop irq en */
79 #define MATE (1 << 0) /* address sent irq en */
90 RCAR_IRQ_OPEN_FOR_SEND,
91 RCAR_IRQ_OPEN_FOR_RECV,
92 RCAR_IRQ_OPEN_FOR_STOP,
98 #define ID_LAST_MSG (1 << 0)
99 #define ID_IOERROR (1 << 1)
100 #define ID_DONE (1 << 2)
101 #define ID_ARBLOST (1 << 3)
102 #define ID_NACK (1 << 4)
109 struct rcar_i2c_priv {
111 struct i2c_adapter adap;
116 wait_queue_head_t wait;
122 enum rcar_i2c_type devtype;
125 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
126 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
128 #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f))
129 #define rcar_i2c_flags_has(p, f) ((p)->flags & (f))
131 #define LOOP_TIMEOUT 1024
136 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
138 writel(val, priv->io + reg);
141 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
143 return readl(priv->io + reg);
146 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
150 * slave mode is not used on this driver
152 rcar_i2c_write(priv, ICSIER, 0);
153 rcar_i2c_write(priv, ICSAR, 0);
154 rcar_i2c_write(priv, ICSCR, 0);
155 rcar_i2c_write(priv, ICSSR, 0);
157 /* reset master mode */
158 rcar_i2c_write(priv, ICMIER, 0);
159 rcar_i2c_write(priv, ICMCR, 0);
160 rcar_i2c_write(priv, ICMSR, 0);
161 rcar_i2c_write(priv, ICMAR, 0);
164 static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open)
166 u32 val = MNRE | MALE | MSTE | MATE; /* default */
169 case RCAR_IRQ_OPEN_FOR_SEND:
170 val |= MDEE; /* default + send */
172 case RCAR_IRQ_OPEN_FOR_RECV:
173 val |= MDRE; /* default + read */
175 case RCAR_IRQ_OPEN_FOR_STOP:
176 val = MSTE; /* stop irq only */
180 val = 0; /* all close */
183 rcar_i2c_write(priv, ICMIER, val);
186 static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv)
188 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv);
192 * bus control functions
194 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
198 for (i = 0; i < LOOP_TIMEOUT; i++) {
199 /* make sure that bus is not busy */
200 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
208 static void rcar_i2c_bus_phase(struct rcar_i2c_priv *priv, int phase)
211 case RCAR_BUS_PHASE_ADDR:
212 rcar_i2c_write(priv, ICMCR, MDBS | MIE | ESG);
214 case RCAR_BUS_PHASE_DATA:
215 rcar_i2c_write(priv, ICMCR, MDBS | MIE);
217 case RCAR_BUS_PHASE_STOP:
218 rcar_i2c_write(priv, ICMCR, MDBS | MIE | FSB);
226 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
236 switch (priv->devtype) {
244 dev_err(dev, "device type error\n");
249 * calculate SCL clock
253 * ick = clkp / (1 + CDF)
254 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
256 * ick : I2C internal clock < 20 MHz
257 * ticf : I2C SCL falling time = 35 ns here
258 * tr : I2C SCL rising time = 200 ns here
259 * intd : LSI internal delay = 50 ns here
260 * clkp : peripheral_clk
261 * F[] : integer up-valuation
263 rate = clk_get_rate(priv->clk);
264 cdf = rate / 20000000;
265 if (cdf >= 1 << cdf_width) {
266 dev_err(dev, "Input clock %lu too high\n", rate);
269 ick = rate / (cdf + 1);
272 * it is impossible to calculate large scale
273 * number on u32. separate it
275 * F[(ticf + tr + intd) * ick]
276 * = F[(35 + 200 + 50)ns * ick]
277 * = F[285 * ick / 1000000000]
278 * = F[(ick / 1000000) * 285 / 1000]
280 round = (ick + 500000) / 1000000 * 285;
281 round = (round + 500) / 1000;
284 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
286 * Calculation result (= SCL) should be less than
287 * bus_speed for hardware safety
289 * We could use something along the lines of
290 * div = ick / (bus_speed + 1) + 1;
291 * scgd = (div - 20 - round + 7) / 8;
292 * scl = ick / (20 + (scgd * 8) + round);
293 * (not fully verified) but that would get pretty involved
295 for (scgd = 0; scgd < 0x40; scgd++) {
296 scl = ick / (20 + (scgd * 8) + round);
297 if (scl <= bus_speed)
300 dev_err(dev, "it is impossible to calculate best SCL\n");
304 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
305 scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
310 priv->icccr = scgd << cdf_width | cdf;
319 #define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff)
320 static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit)
322 rcar_i2c_write(priv, ICMSR, ~bit);
326 * recv/send functions
328 static int rcar_i2c_recv(struct rcar_i2c_priv *priv)
330 rcar_i2c_set_addr(priv, 1);
331 rcar_i2c_status_clear(priv);
332 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR);
333 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV);
338 static int rcar_i2c_send(struct rcar_i2c_priv *priv)
343 * It should check bus status when send case
345 ret = rcar_i2c_bus_barrier(priv);
349 rcar_i2c_set_addr(priv, 0);
350 rcar_i2c_status_clear(priv);
351 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR);
352 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND);
357 #define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE))
358 #define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR))
361 * interrupt functions
363 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
365 struct i2c_msg *msg = priv->msg;
369 * sometimes, unknown interrupt happened.
376 * If address transfer phase finished,
380 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA);
382 if (priv->pos < msg->len) {
384 * Prepare next data to ICRXTX register.
385 * This data will go to _SHIFT_ register.
388 * [ICRXTX] -> [SHIFT] -> [I2C bus]
390 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
395 * The last data was pushed to ICRXTX on _PREV_ empty irq.
396 * It is on _SHIFT_ register, and will sent to I2C bus.
399 * [ICRXTX] -> [SHIFT] -> [I2C bus]
402 if (priv->flags & ID_LAST_MSG)
404 * If current msg is the _LAST_ msg,
405 * prepare stop condition here.
406 * ID_DONE will be set on STOP irq.
408 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
411 * If current msg is _NOT_ last msg,
412 * it doesn't call stop phase.
413 * thus, there is no STOP irq.
414 * return ID_DONE here.
419 rcar_i2c_send_restart(priv);
424 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
426 struct i2c_msg *msg = priv->msg;
430 * sometimes, unknown interrupt happened.
438 * Address transfer phase finished,
439 * but, there is no data at this point.
442 } else if (priv->pos < msg->len) {
446 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
451 * If next received data is the _LAST_,
453 * otherwise, go to DATA phase.
455 if (priv->pos + 1 >= msg->len)
456 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
458 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA);
460 rcar_i2c_recv_restart(priv);
465 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
467 struct rcar_i2c_priv *priv = ptr;
468 struct device *dev = rcar_i2c_priv_to_dev(priv);
471 /*-------------- spin lock -----------------*/
472 spin_lock(&priv->lock);
474 msr = rcar_i2c_read(priv, ICMSR);
483 * When arbitration lost, device become _slave_ mode.
485 dev_dbg(dev, "Arbitration Lost\n");
486 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
494 dev_dbg(dev, "Stop\n");
495 rcar_i2c_flags_set(priv, ID_DONE);
503 dev_dbg(dev, "Nack\n");
505 /* go to stop phase */
506 rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
507 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP);
508 rcar_i2c_flags_set(priv, ID_NACK);
515 if (rcar_i2c_is_recv(priv))
516 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
518 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
521 if (rcar_i2c_flags_has(priv, ID_DONE)) {
522 rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE);
523 rcar_i2c_status_clear(priv);
524 wake_up(&priv->wait);
527 spin_unlock(&priv->lock);
528 /*-------------- spin unlock -----------------*/
533 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
534 struct i2c_msg *msgs,
537 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
538 struct device *dev = rcar_i2c_priv_to_dev(priv);
542 pm_runtime_get_sync(dev);
544 /*-------------- spin lock -----------------*/
545 spin_lock_irqsave(&priv->lock, flags);
549 rcar_i2c_write(priv, ICCCR, priv->icccr);
551 spin_unlock_irqrestore(&priv->lock, flags);
552 /*-------------- spin unlock -----------------*/
555 for (i = 0; i < num; i++) {
556 /* This HW can't send STOP after address phase */
557 if (msgs[i].len == 0) {
562 /*-------------- spin lock -----------------*/
563 spin_lock_irqsave(&priv->lock, flags);
566 priv->msg = &msgs[i];
569 if (priv->msg == &msgs[num - 1])
570 rcar_i2c_flags_set(priv, ID_LAST_MSG);
572 /* start send/recv */
573 if (rcar_i2c_is_recv(priv))
574 ret = rcar_i2c_recv(priv);
576 ret = rcar_i2c_send(priv);
578 spin_unlock_irqrestore(&priv->lock, flags);
579 /*-------------- spin unlock -----------------*/
587 timeout = wait_event_timeout(priv->wait,
588 rcar_i2c_flags_has(priv, ID_DONE),
598 if (rcar_i2c_flags_has(priv, ID_NACK)) {
603 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
608 if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
613 ret = i + 1; /* The number of transfer */
618 if (ret < 0 && ret != -ENXIO)
619 dev_err(dev, "error %d : %x\n", ret, priv->flags);
624 static u32 rcar_i2c_func(struct i2c_adapter *adap)
626 /* This HW can't do SMBUS_QUICK and NOSTART */
627 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
630 static const struct i2c_algorithm rcar_i2c_algo = {
631 .master_xfer = rcar_i2c_master_xfer,
632 .functionality = rcar_i2c_func,
635 static const struct of_device_id rcar_i2c_dt_ids[] = {
636 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
637 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
638 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
639 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
640 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
641 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
642 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
643 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
646 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
648 static int rcar_i2c_probe(struct platform_device *pdev)
650 struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
651 struct rcar_i2c_priv *priv;
652 struct i2c_adapter *adap;
653 struct resource *res;
654 struct device *dev = &pdev->dev;
658 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
660 dev_err(dev, "no mem for private data\n");
664 priv->clk = devm_clk_get(dev, NULL);
665 if (IS_ERR(priv->clk)) {
666 dev_err(dev, "cannot get clock\n");
667 return PTR_ERR(priv->clk);
670 bus_speed = 100000; /* default 100 kHz */
671 ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
672 if (ret < 0 && pdata && pdata->bus_speed)
673 bus_speed = pdata->bus_speed;
675 if (pdev->dev.of_node)
676 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
679 priv->devtype = platform_get_device_id(pdev)->driver_data;
681 ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
685 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
686 priv->io = devm_ioremap_resource(dev, res);
687 if (IS_ERR(priv->io))
688 return PTR_ERR(priv->io);
690 priv->irq = platform_get_irq(pdev, 0);
691 init_waitqueue_head(&priv->wait);
692 spin_lock_init(&priv->lock);
696 adap->algo = &rcar_i2c_algo;
697 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED;
699 adap->dev.parent = dev;
700 adap->dev.of_node = dev->of_node;
701 i2c_set_adapdata(adap, priv);
702 strlcpy(adap->name, pdev->name, sizeof(adap->name));
704 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0,
705 dev_name(dev), priv);
707 dev_err(dev, "cannot get irq %d\n", priv->irq);
711 ret = i2c_add_numbered_adapter(adap);
713 dev_err(dev, "reg adap failed: %d\n", ret);
717 pm_runtime_enable(dev);
718 platform_set_drvdata(pdev, priv);
720 dev_info(dev, "probed\n");
725 static int rcar_i2c_remove(struct platform_device *pdev)
727 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
728 struct device *dev = &pdev->dev;
730 i2c_del_adapter(&priv->adap);
731 pm_runtime_disable(dev);
736 static struct platform_device_id rcar_i2c_id_table[] = {
737 { "i2c-rcar", I2C_RCAR_GEN1 },
738 { "i2c-rcar_gen1", I2C_RCAR_GEN1 },
739 { "i2c-rcar_gen2", I2C_RCAR_GEN2 },
742 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
744 static struct platform_driver rcar_i2c_driver = {
747 .owner = THIS_MODULE,
748 .of_match_table = rcar_i2c_dt_ids,
750 .probe = rcar_i2c_probe,
751 .remove = rcar_i2c_remove,
752 .id_table = rcar_i2c_id_table,
755 module_platform_driver(rcar_i2c_driver);
757 MODULE_LICENSE("GPL");
758 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
759 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");